Line Coverage for Module :
adc_ctrl_intr
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 26 | 26 | 100.00 |
| CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
| ALWAYS | 51 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| ALWAYS | 68 | 6 | 6 | 100.00 |
| ALWAYS | 95 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
38 logic [NumAonIntrEvents-1:0] aon_reqs;
39 1/1 assign aon_reqs = {aon_fsm_trans_i, aon_filter_match_i};
Tests: T1 T2 T3
40
41 // aon interrupt requests are split into staging and request portions.
42 // The staging portion always absorbs the incoming event pulse.
43 // The request portion on the other hand does not change until
44 // a request/ack handshake cycle has completed.
45 logic [NumAonIntrEvents-1:0] aon_staging_reqs_q;
46 logic aon_ld_req;
47
48 // staging portion takes on the value of the incoming event match
49 // and clears when it is snapshot into request hold.
50 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
51 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
52 1/1 aon_staging_reqs_q <= '0;
Tests: T1 T2 T3
53 1/1 end else if (aon_ld_req) begin
Tests: T1 T2 T3
54 1/1 aon_staging_reqs_q <= aon_reqs;
Tests: T5 T7 T8
55 1/1 end else if (|aon_reqs) begin
Tests: T1 T2 T3
56 1/1 aon_staging_reqs_q <= aon_staging_reqs_q | aon_reqs;
Tests: T5 T7 T8
57 end
MISSING_ELSE
58 end
59
60 logic [NumAonIntrEvents-1:0] aon_req_hold_q;
61 logic aon_ack;
62
63 // staging has pending requsts
64 1/1 assign aon_ld_req = (aon_req_hold_q == '0) && |aon_staging_reqs_q;
Tests: T1 T2 T3
65
66 // request hold self clears when the handshake cycle is complete
67 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
68 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
69 1/1 aon_req_hold_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (aon_ld_req) begin
Tests: T1 T2 T3
71 1/1 aon_req_hold_q <= aon_staging_reqs_q;
Tests: T5 T7 T8
72 1/1 end else if (aon_ack) begin
Tests: T1 T2 T3
73 1/1 aon_req_hold_q <= '0;
Tests: T5 T7 T8
74 end
MISSING_ELSE
75 end
76
77 logic dst_ack;
78 prim_sync_reqack u_match_sync (
79 .clk_src_i(clk_aon_i),
80 .rst_src_ni(rst_aon_ni),
81 .clk_dst_i(clk_i),
82 .rst_dst_ni(rst_ni),
83 .req_chk_i(1'b1),
84 .src_req_i(|aon_req_hold_q),
85 .src_ack_o(aon_ack),
86 .dst_req_o(dst_ack),
87 .dst_ack_i(dst_ack)
88 );
89
90 // Holding reg after the CDC. Note that aon_req_hold_q does not change until the handshake has
91 // been completed, hence we can sample it safely upon a dst_ack pulse.
92 logic dst_ack_q;
93 logic [NumAonIntrEvents-1:0] req_hold_q;
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
96 1/1 req_hold_q <= '0;
Tests: T1 T2 T3
97 1/1 dst_ack_q <= 1'b0;
Tests: T1 T2 T3
98 end else begin
99 1/1 dst_ack_q <= dst_ack;
Tests: T1 T2 T3
100 1/1 if (dst_ack) begin
Tests: T1 T2 T3
101 1/1 req_hold_q <= aon_req_hold_q;
Tests: T5 T7 T8
102 end
MISSING_ELSE
103 end
104 end
105
106 1/1 assign adc_intr_status_o.trans.de = cfg_intr_trans_en_i && dst_ack_q && req_hold_q[8];
Tests: T1 T2 T3
107 assign adc_intr_status_o.trans.d = 1'b1;
108 // Since interrupt events are pulsed, when successive events arrive we need to make sure to
109 // hold the previously latched values
110 logic [NumAdcFilter-1:0] match_events;
111 1/1 assign match_events = cfg_intr_en_i & {NumAdcFilter{dst_ack_q}} & req_hold_q[NumAdcFilter-1:0];
Tests: T1 T2 T3
112 1/1 assign adc_intr_status_o.match.de = |match_events;
Tests: T1 T2 T3
113 1/1 assign adc_intr_status_o.match.d = match_events | adc_intr_status_i.match.q;
Tests: T1 T2 T3
114 // Note that we're also adding the non-AON interrupt source cfg_oneshot_done_i at this point.
115 1/1 assign adc_intr_status_o.oneshot.de = cfg_oneshot_done_i && cfg_oneshot_done_en_i;
Tests: T1 T2 T3
116 assign adc_intr_status_o.oneshot.d = 1'b1;
117
118 logic status_irq_value;
119 1/1 assign status_irq_value = |{adc_intr_status_i.oneshot.q,
Tests: T1 T2 T3
Cond Coverage for Module :
adc_ctrl_intr
| Total | Covered | Percent |
|---|
| Conditions | 12 | 12 | 100.00 |
| Logical | 12 | 12 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION ((aon_req_hold_q == '0) && ((|aon_staging_reqs_q)))
-----------1---------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T41,T59 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T5,T7,T8 |
LINE 64
SUB-EXPRESSION (aon_req_hold_q == '0)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 106
EXPRESSION (cfg_intr_trans_en_i && dst_ack_q && req_hold_q[8])
---------1--------- ----2---- ------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T12,T13,T16 |
| 1 | 0 | 1 | Covered | T7,T59,T129 |
| 1 | 1 | 0 | Covered | T7,T8,T10 |
| 1 | 1 | 1 | Covered | T7,T59,T129 |
LINE 115
EXPRESSION (cfg_oneshot_done_i && cfg_oneshot_done_en_i)
---------1-------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T7 |
| 1 | 0 | Covered | T2,T6,T7 |
| 1 | 1 | Covered | T1,T4,T9 |
Branch Coverage for Module :
adc_ctrl_intr
| Line No. | Total | Covered | Percent |
| Branches |
|
11 |
11 |
100.00 |
| IF |
51 |
4 |
4 |
100.00 |
| IF |
68 |
4 |
4 |
100.00 |
| IF |
95 |
3 |
3 |
100.00 |
51 if (!rst_aon_ni) begin
-1-
52 aon_staging_reqs_q <= '0;
==>
53 end else if (aon_ld_req) begin
-2-
54 aon_staging_reqs_q <= aon_reqs;
==>
55 end else if (|aon_reqs) begin
-3-
56 aon_staging_reqs_q <= aon_staging_reqs_q | aon_reqs;
==>
57 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T5,T7,T8 |
| 0 |
0 |
1 |
Covered |
T5,T7,T8 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
68 if (!rst_aon_ni) begin
-1-
69 aon_req_hold_q <= '0;
==>
70 end else if (aon_ld_req) begin
-2-
71 aon_req_hold_q <= aon_staging_reqs_q;
==>
72 end else if (aon_ack) begin
-3-
73 aon_req_hold_q <= '0;
==>
74 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T5,T7,T8 |
| 0 |
0 |
1 |
Covered |
T5,T7,T8 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
95 if (!rst_ni) begin
-1-
96 req_hold_q <= '0;
==>
97 dst_ack_q <= 1'b0;
98 end else begin
99 dst_ack_q <= dst_ack;
100 if (dst_ack) begin
-2-
101 req_hold_q <= aon_req_hold_q;
==>
102 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
