Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2333	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2347	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2346	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2200	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2420	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2200	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2323	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2415	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2355	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2327	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2422	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2399	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2335	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2356	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2158	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2589	0	0
adc_en_ctl_rd_A	2147483647	1972	0	0
adc_fsm_rst_rd_A	2147483647	1799	0	0
adc_intr_ctl_rd_A	2147483647	2119	0	0
adc_lp_sample_ctl_rd_A	2147483647	1880	0	0
adc_pd_ctl_rd_A	2147483647	2117	0	0
adc_sample_ctl_rd_A	2147483647	1678	0	0
adc_wakeup_ctl_rd_A	2147483647	1933	0	0
intr_enable_rd_A	2147483647	2277	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2333	0	0
T7	427421	27	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	26	0	0
T22	0	20	0	0
T23	0	26	0	0
T24	0	17	0	0
T25	0	22	0	0
T26	0	5	0	0
T27	0	19	0	0
T28	0	14	0	0
T29	0	42	0	0
T30	126431	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2347	0	0
T7	427421	33	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	7	0	0
T22	0	20	0	0
T23	0	15	0	0
T24	0	15	0	0
T25	0	8	0	0
T26	0	10	0	0
T27	0	24	0	0
T28	0	21	0	0
T29	0	31	0	0
T30	126431	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2346	0	0
T7	427421	33	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	18	0	0
T22	0	16	0	0
T23	0	24	0	0
T24	0	23	0	0
T25	0	28	0	0
T26	0	7	0	0
T27	0	20	0	0
T28	0	35	0	0
T29	0	31	0	0
T30	126431	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2200	0	0
T7	427421	46	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	27	0	0
T22	0	23	0	0
T23	0	19	0	0
T24	0	23	0	0
T25	0	17	0	0
T26	0	14	0	0
T27	0	24	0	0
T28	0	7	0	0
T29	0	39	0	0
T30	126431	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2420	0	0
T7	427421	27	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	13	0	0
T22	0	18	0	0
T23	0	20	0	0
T24	0	30	0	0
T25	0	33	0	0
T26	0	3	0	0
T27	0	18	0	0
T28	0	33	0	0
T29	0	38	0	0
T30	126431	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2200	0	0
T7	427421	14	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	15	0	0
T22	0	19	0	0
T23	0	21	0	0
T24	0	12	0	0
T25	0	8	0	0
T26	0	15	0	0
T27	0	18	0	0
T28	0	13	0	0
T29	0	43	0	0
T30	126431	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2323	0	0
T7	427421	44	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	13	0	0
T22	0	11	0	0
T23	0	19	0	0
T24	0	25	0	0
T25	0	21	0	0
T26	0	7	0	0
T27	0	14	0	0
T28	0	26	0	0
T29	0	29	0	0
T30	126431	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2415	0	0
T7	427421	32	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	21	0	0
T22	0	23	0	0
T23	0	11	0	0
T24	0	28	0	0
T25	0	26	0	0
T26	0	4	0	0
T27	0	16	0	0
T28	0	18	0	0
T29	0	30	0	0
T30	126431	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2355	0	0
T7	427421	32	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	18	0	0
T22	0	12	0	0
T23	0	38	0	0
T24	0	16	0	0
T25	0	11	0	0
T26	0	10	0	0
T27	0	15	0	0
T28	0	19	0	0
T29	0	36	0	0
T30	126431	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2327	0	0
T7	427421	44	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	23	0	0
T22	0	9	0	0
T23	0	20	0	0
T24	0	28	0	0
T25	0	7	0	0
T26	0	12	0	0
T27	0	24	0	0
T28	0	15	0	0
T29	0	34	0	0
T30	126431	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2422	0	0
T7	427421	37	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	4	0	0
T22	0	21	0	0
T23	0	19	0	0
T24	0	22	0	0
T25	0	15	0	0
T26	0	17	0	0
T27	0	20	0	0
T28	0	13	0	0
T29	0	42	0	0
T30	126431	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2399	0	0
T7	427421	29	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	25	0	0
T22	0	18	0	0
T23	0	14	0	0
T24	0	25	0	0
T25	0	18	0	0
T26	0	11	0	0
T27	0	20	0	0
T28	0	27	0	0
T29	0	43	0	0
T30	126431	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2335	0	0
T7	427421	23	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	26	0	0
T22	0	23	0	0
T23	0	28	0	0
T24	0	17	0	0
T25	0	13	0	0
T26	0	18	0	0
T27	0	21	0	0
T28	0	14	0	0
T29	0	45	0	0
T30	126431	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2356	0	0
T7	427421	33	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	29	0	0
T22	0	17	0	0
T23	0	22	0	0
T24	0	31	0	0
T25	0	17	0	0
T26	0	19	0	0
T27	0	19	0	0
T28	0	30	0	0
T29	0	46	0	0
T30	126431	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2158	0	0
T7	427421	38	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	20	0	0
T22	0	16	0	0
T23	0	11	0	0
T24	0	22	0	0
T25	0	17	0	0
T26	0	13	0	0
T27	0	14	0	0
T28	0	26	0	0
T29	0	52	0	0
T30	126431	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2589	0	0
T7	427421	51	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	18	0	0
T22	0	11	0	0
T23	0	33	0	0
T24	0	25	0	0
T25	0	27	0	0
T26	0	14	0	0
T27	0	16	0	0
T28	0	26	0	0
T29	0	25	0	0
T30	126431	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1972	0	0
T7	427421	33	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	17	0	0
T22	0	11	0	0
T23	0	14	0	0
T24	0	18	0	0
T25	0	19	0	0
T26	0	13	0	0
T27	0	29	0	0
T28	0	20	0	0
T29	0	34	0	0
T30	126431	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1799	0	0
T7	427421	44	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	15	0	0
T22	0	18	0	0
T23	0	6	0	0
T24	0	21	0	0
T25	0	25	0	0
T26	0	26	0	0
T27	0	21	0	0
T28	0	17	0	0
T29	0	54	0	0
T30	126431	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2119	0	0
T7	427421	29	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	18	0	0
T22	0	19	0	0
T23	0	19	0	0
T24	0	17	0	0
T25	0	25	0	0
T26	0	12	0	0
T27	0	13	0	0
T28	0	15	0	0
T29	0	37	0	0
T30	126431	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1880	0	0
T7	427421	31	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	25	0	0
T22	0	14	0	0
T23	0	37	0	0
T24	0	14	0	0
T25	0	26	0	0
T26	0	11	0	0
T27	0	16	0	0
T28	0	21	0	0
T29	0	40	0	0
T30	126431	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2117	0	0
T7	427421	29	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	13	0	0
T22	0	11	0	0
T23	0	36	0	0
T24	0	27	0	0
T25	0	23	0	0
T26	0	10	0	0
T27	0	30	0	0
T28	0	23	0	0
T29	0	35	0	0
T30	126431	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1678	0	0
T7	427421	38	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	12	0	0
T22	0	27	0	0
T23	0	10	0	0
T24	0	12	0	0
T25	0	17	0	0
T26	0	1	0	0
T27	0	27	0	0
T28	0	19	0	0
T29	0	31	0	0
T30	126431	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1933	0	0
T7	427421	40	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	25	0	0
T22	0	15	0	0
T23	0	16	0	0
T24	0	19	0	0
T25	0	8	0	0
T26	0	3	0	0
T27	0	22	0	0
T28	0	7	0	0
T29	0	36	0	0
T30	126431	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2277	0	0
T7	427421	30	0	0
T8	158023	0	0	0
T9	280162	0	0	0
T10	390013	0	0	0
T11	389392	0	0	0
T12	471565	0	0	0
T13	377259	0	0	0
T19	27813	0	0	0
T20	388272	0	0	0
T21	0	20	0	0
T22	0	23	0	0
T23	0	22	0	0
T24	0	30	0	0
T25	0	46	0	0
T26	0	2	0	0
T27	0	13	0	0
T30	126431	0	0	0
T31	0	11	0	0
T32	0	7	0	0