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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.07


Total test records in report: 920
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T330 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.2424045619 Aug 23 05:49:21 AM UTC 24 Aug 23 06:08:12 AM UTC 24 497156760160 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2767160931 Aug 23 05:56:38 AM UTC 24 Aug 23 06:08:14 AM UTC 24 330519003691 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3406759111 Aug 23 05:57:05 AM UTC 24 Aug 23 06:13:49 AM UTC 24 414650489247 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.3036847103 Aug 23 05:57:01 AM UTC 24 Aug 23 06:14:58 AM UTC 24 539955729692 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.789684856 Aug 23 05:51:03 AM UTC 24 Aug 23 06:16:09 AM UTC 24 659198039969 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.522575188 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:06 AM UTC 24 338843466 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2152585981 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:06 AM UTC 24 478783446 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1711615825 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:07 AM UTC 24 1287400180 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.36374112 Aug 23 03:22:05 AM UTC 24 Aug 23 03:22:07 AM UTC 24 634883169 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1576651222 Aug 23 03:22:05 AM UTC 24 Aug 23 03:22:07 AM UTC 24 2326541358 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2416087176 Aug 23 03:22:05 AM UTC 24 Aug 23 03:22:07 AM UTC 24 488529938 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3907790679 Aug 23 03:22:06 AM UTC 24 Aug 23 03:22:08 AM UTC 24 439714033 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2055697372 Aug 23 03:22:07 AM UTC 24 Aug 23 03:22:09 AM UTC 24 388962735 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4244380159 Aug 23 03:22:05 AM UTC 24 Aug 23 03:22:09 AM UTC 24 950445146 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2699523584 Aug 23 03:22:08 AM UTC 24 Aug 23 03:22:10 AM UTC 24 343662923 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2782182350 Aug 23 03:22:08 AM UTC 24 Aug 23 03:22:10 AM UTC 24 320068835 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1793716423 Aug 23 03:22:06 AM UTC 24 Aug 23 03:22:10 AM UTC 24 529399086 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2994365181 Aug 23 03:22:09 AM UTC 24 Aug 23 03:22:11 AM UTC 24 511224646 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2652168148 Aug 23 03:22:06 AM UTC 24 Aug 23 03:22:11 AM UTC 24 1241918030 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3217736708 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:11 AM UTC 24 9302788019 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2310272347 Aug 23 03:22:09 AM UTC 24 Aug 23 03:22:11 AM UTC 24 1099248346 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1371459413 Aug 23 03:22:07 AM UTC 24 Aug 23 03:22:11 AM UTC 24 1364335315 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3724290768 Aug 23 03:22:08 AM UTC 24 Aug 23 03:22:12 AM UTC 24 5019742457 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.615515641 Aug 23 03:22:10 AM UTC 24 Aug 23 03:22:12 AM UTC 24 338815654 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.883944470 Aug 23 03:22:11 AM UTC 24 Aug 23 03:22:14 AM UTC 24 916909390 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.396490834 Aug 23 03:22:12 AM UTC 24 Aug 23 03:22:14 AM UTC 24 301375658 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1174497229 Aug 23 03:22:11 AM UTC 24 Aug 23 03:22:14 AM UTC 24 443811403 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2707816189 Aug 23 03:22:08 AM UTC 24 Aug 23 03:22:14 AM UTC 24 8624892554 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1360116194 Aug 23 03:22:12 AM UTC 24 Aug 23 03:22:14 AM UTC 24 465939225 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3694626729 Aug 23 03:22:12 AM UTC 24 Aug 23 03:22:15 AM UTC 24 635029414 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3846798520 Aug 23 03:22:11 AM UTC 24 Aug 23 03:22:15 AM UTC 24 406114193 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1942169226 Aug 23 03:22:05 AM UTC 24 Aug 23 03:22:16 AM UTC 24 26511305682 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3650760698 Aug 23 03:22:14 AM UTC 24 Aug 23 03:22:16 AM UTC 24 530369471 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2654167237 Aug 23 03:22:14 AM UTC 24 Aug 23 03:22:17 AM UTC 24 475560237 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1085783492 Aug 23 03:22:11 AM UTC 24 Aug 23 03:22:17 AM UTC 24 2048922475 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2356878744 Aug 23 03:22:15 AM UTC 24 Aug 23 03:22:17 AM UTC 24 410886865 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3298673824 Aug 23 03:22:15 AM UTC 24 Aug 23 03:22:18 AM UTC 24 493075535 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3659268370 Aug 23 03:22:06 AM UTC 24 Aug 23 03:22:19 AM UTC 24 4497136352 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3050580485 Aug 23 03:22:14 AM UTC 24 Aug 23 03:22:19 AM UTC 24 2144128716 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3930644558 Aug 23 03:22:15 AM UTC 24 Aug 23 03:22:19 AM UTC 24 828884809 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3273091181 Aug 23 03:22:13 AM UTC 24 Aug 23 03:22:19 AM UTC 24 1200541835 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3326218110 Aug 23 03:22:18 AM UTC 24 Aug 23 03:22:20 AM UTC 24 594541450 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4145256860 Aug 23 03:22:19 AM UTC 24 Aug 23 03:22:21 AM UTC 24 650642834 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2087400650 Aug 23 03:22:18 AM UTC 24 Aug 23 03:22:21 AM UTC 24 2321419462 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.881214823 Aug 23 03:22:20 AM UTC 24 Aug 23 03:22:22 AM UTC 24 472830914 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.863693393 Aug 23 03:22:20 AM UTC 24 Aug 23 03:22:22 AM UTC 24 448010095 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2338776485 Aug 23 03:22:18 AM UTC 24 Aug 23 03:22:22 AM UTC 24 862381744 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1581112325 Aug 23 03:22:20 AM UTC 24 Aug 23 03:22:22 AM UTC 24 600379925 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2268212167 Aug 23 03:22:12 AM UTC 24 Aug 23 03:22:23 AM UTC 24 4060482798 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.849151890 Aug 23 03:22:14 AM UTC 24 Aug 23 03:22:24 AM UTC 24 4156764775 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.496372979 Aug 23 03:22:21 AM UTC 24 Aug 23 03:22:25 AM UTC 24 1011686733 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2282740090 Aug 23 03:22:23 AM UTC 24 Aug 23 03:22:26 AM UTC 24 567701145 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.1087236907 Aug 23 03:22:23 AM UTC 24 Aug 23 03:22:26 AM UTC 24 302997410 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1655072106 Aug 23 03:22:24 AM UTC 24 Aug 23 03:22:26 AM UTC 24 428077822 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1800490853 Aug 23 03:22:24 AM UTC 24 Aug 23 03:22:26 AM UTC 24 576198939 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1409391094 Aug 23 03:22:24 AM UTC 24 Aug 23 03:22:27 AM UTC 24 579544750 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4245314455 Aug 23 03:22:25 AM UTC 24 Aug 23 03:22:27 AM UTC 24 329218259 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1087492552 Aug 23 03:22:26 AM UTC 24 Aug 23 03:22:29 AM UTC 24 450281373 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.1076970948 Aug 23 03:22:27 AM UTC 24 Aug 23 03:22:29 AM UTC 24 487504662 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.508361448 Aug 23 03:22:20 AM UTC 24 Aug 23 03:22:29 AM UTC 24 2276227010 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2658712856 Aug 23 03:22:27 AM UTC 24 Aug 23 03:22:30 AM UTC 24 335948873 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3178938852 Aug 23 03:22:23 AM UTC 24 Aug 23 03:22:30 AM UTC 24 5379770219 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2311648845 Aug 23 03:22:19 AM UTC 24 Aug 23 03:22:30 AM UTC 24 4444805110 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1707856521 Aug 23 03:22:27 AM UTC 24 Aug 23 03:22:30 AM UTC 24 508610695 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3230027006 Aug 23 03:22:28 AM UTC 24 Aug 23 03:22:31 AM UTC 24 520779585 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2856846916 Aug 23 03:22:22 AM UTC 24 Aug 23 03:22:32 AM UTC 24 4160395945 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.250168193 Aug 23 03:22:28 AM UTC 24 Aug 23 03:22:33 AM UTC 24 5152316767 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2635671581 Aug 23 03:22:30 AM UTC 24 Aug 23 03:22:33 AM UTC 24 495151781 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2236545930 Aug 23 03:22:31 AM UTC 24 Aug 23 03:22:33 AM UTC 24 291700273 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1973341840 Aug 23 03:22:31 AM UTC 24 Aug 23 03:22:33 AM UTC 24 595871117 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1666489207 Aug 23 03:22:31 AM UTC 24 Aug 23 03:22:34 AM UTC 24 439535670 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.1022089055 Aug 23 03:22:32 AM UTC 24 Aug 23 03:22:34 AM UTC 24 348120077 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2668603886 Aug 23 03:22:31 AM UTC 24 Aug 23 03:22:35 AM UTC 24 470639754 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2501487131 Aug 23 03:22:25 AM UTC 24 Aug 23 03:22:36 AM UTC 24 4594906418 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3339922213 Aug 23 03:22:33 AM UTC 24 Aug 23 03:22:36 AM UTC 24 321222583 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2997655230 Aug 23 03:22:31 AM UTC 24 Aug 23 03:22:36 AM UTC 24 4364866966 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3123642134 Aug 23 03:22:34 AM UTC 24 Aug 23 03:22:37 AM UTC 24 457758642 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2722650266 Aug 23 03:22:34 AM UTC 24 Aug 23 03:22:37 AM UTC 24 461893134 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.961476294 Aug 23 03:22:31 AM UTC 24 Aug 23 03:22:37 AM UTC 24 4585834787 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3436935673 Aug 23 03:22:30 AM UTC 24 Aug 23 03:22:37 AM UTC 24 8697862058 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4253423287 Aug 23 03:22:34 AM UTC 24 Aug 23 03:22:37 AM UTC 24 386262688 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.553091635 Aug 23 03:22:36 AM UTC 24 Aug 23 03:22:38 AM UTC 24 349412180 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.369990063 Aug 23 03:22:37 AM UTC 24 Aug 23 03:22:39 AM UTC 24 684575977 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3314957602 Aug 23 03:22:34 AM UTC 24 Aug 23 03:22:39 AM UTC 24 2317056033 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.183214553 Aug 23 03:22:36 AM UTC 24 Aug 23 03:22:39 AM UTC 24 526017088 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2297559847 Aug 23 03:22:36 AM UTC 24 Aug 23 03:22:40 AM UTC 24 3353232315 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3274767528 Aug 23 03:22:37 AM UTC 24 Aug 23 03:22:40 AM UTC 24 933258090 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3426239297 Aug 23 03:22:38 AM UTC 24 Aug 23 03:22:41 AM UTC 24 375003148 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1838987348 Aug 23 03:22:38 AM UTC 24 Aug 23 03:22:41 AM UTC 24 334123844 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.3135041561 Aug 23 03:22:39 AM UTC 24 Aug 23 03:22:41 AM UTC 24 302469350 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3518957824 Aug 23 03:22:39 AM UTC 24 Aug 23 03:22:41 AM UTC 24 527477640 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4273172802 Aug 23 03:22:34 AM UTC 24 Aug 23 03:22:41 AM UTC 24 4267098879 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.43327060 Aug 23 03:22:39 AM UTC 24 Aug 23 03:22:42 AM UTC 24 725446520 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3006241719 Aug 23 03:22:38 AM UTC 24 Aug 23 03:22:42 AM UTC 24 514218326 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2763306590 Aug 23 03:22:41 AM UTC 24 Aug 23 03:22:43 AM UTC 24 349749490 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1367754245 Aug 23 03:22:24 AM UTC 24 Aug 23 03:22:44 AM UTC 24 8000825457 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4274279218 Aug 23 03:22:40 AM UTC 24 Aug 23 03:22:44 AM UTC 24 849202630 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.140098602 Aug 23 03:22:41 AM UTC 24 Aug 23 03:22:44 AM UTC 24 376370913 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3072119467 Aug 23 03:22:42 AM UTC 24 Aug 23 03:22:44 AM UTC 24 629731832 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3105236034 Aug 23 03:22:42 AM UTC 24 Aug 23 03:22:45 AM UTC 24 396182318 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3162428135 Aug 23 03:22:38 AM UTC 24 Aug 23 03:22:45 AM UTC 24 4909828140 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3682738406 Aug 23 03:22:42 AM UTC 24 Aug 23 03:22:46 AM UTC 24 361579344 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3852763299 Aug 23 03:22:38 AM UTC 24 Aug 23 03:22:46 AM UTC 24 8585829980 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3412485909 Aug 23 03:22:39 AM UTC 24 Aug 23 03:22:46 AM UTC 24 4698476840 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1449791039 Aug 23 03:22:44 AM UTC 24 Aug 23 03:22:46 AM UTC 24 501937613 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1921649682 Aug 23 03:22:45 AM UTC 24 Aug 23 03:22:47 AM UTC 24 410135627 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1670371377 Aug 23 03:22:42 AM UTC 24 Aug 23 03:22:47 AM UTC 24 2162034279 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.226532548 Aug 23 03:22:46 AM UTC 24 Aug 23 03:22:48 AM UTC 24 368782468 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2611411807 Aug 23 03:22:46 AM UTC 24 Aug 23 03:22:48 AM UTC 24 397766783 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.258056087 Aug 23 03:22:45 AM UTC 24 Aug 23 03:22:48 AM UTC 24 661188331 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.3272719630 Aug 23 03:22:59 AM UTC 24 Aug 23 03:23:01 AM UTC 24 412551062 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.678864710 Aug 23 03:22:27 AM UTC 24 Aug 23 03:22:48 AM UTC 24 8076615220 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3382813367 Aug 23 03:22:37 AM UTC 24 Aug 23 03:22:49 AM UTC 24 4571232768 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2226539164 Aug 23 03:22:47 AM UTC 24 Aug 23 03:22:49 AM UTC 24 2520884684 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1568059803 Aug 23 03:22:47 AM UTC 24 Aug 23 03:22:50 AM UTC 24 960216865 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1070642125 Aug 23 03:22:48 AM UTC 24 Aug 23 03:22:50 AM UTC 24 359604552 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.126183242 Aug 23 03:22:47 AM UTC 24 Aug 23 03:22:50 AM UTC 24 403263276 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2010508402 Aug 23 03:22:48 AM UTC 24 Aug 23 03:22:50 AM UTC 24 581712918 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.3324751432 Aug 23 03:22:48 AM UTC 24 Aug 23 03:22:50 AM UTC 24 474370342 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1201730479 Aug 23 03:22:42 AM UTC 24 Aug 23 03:22:51 AM UTC 24 8507832645 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2894609873 Aug 23 03:22:45 AM UTC 24 Aug 23 03:22:51 AM UTC 24 2651953184 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.2961017246 Aug 23 03:22:50 AM UTC 24 Aug 23 03:22:52 AM UTC 24 397662108 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3959216478 Aug 23 03:22:50 AM UTC 24 Aug 23 03:22:52 AM UTC 24 529948116 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.341868478 Aug 23 03:22:50 AM UTC 24 Aug 23 03:22:52 AM UTC 24 405436952 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1168256537 Aug 23 03:22:49 AM UTC 24 Aug 23 03:22:53 AM UTC 24 942800192 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2582429663 Aug 23 03:22:50 AM UTC 24 Aug 23 03:22:53 AM UTC 24 620316492 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3623454848 Aug 23 03:22:46 AM UTC 24 Aug 23 03:22:53 AM UTC 24 4781310693 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2631051444 Aug 23 03:22:49 AM UTC 24 Aug 23 03:22:53 AM UTC 24 4335468250 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2064493461 Aug 23 03:22:51 AM UTC 24 Aug 23 03:22:53 AM UTC 24 388284916 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3921351664 Aug 23 03:22:51 AM UTC 24 Aug 23 03:22:53 AM UTC 24 380424376 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2628006576 Aug 23 03:22:50 AM UTC 24 Aug 23 03:22:54 AM UTC 24 2339263590 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1751103343 Aug 23 03:22:53 AM UTC 24 Aug 23 03:22:54 AM UTC 24 473905516 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1431065538 Aug 23 03:22:48 AM UTC 24 Aug 23 03:22:54 AM UTC 24 4718943338 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3071827944 Aug 23 03:22:52 AM UTC 24 Aug 23 03:22:55 AM UTC 24 312581702 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.3640403309 Aug 23 03:22:54 AM UTC 24 Aug 23 03:22:55 AM UTC 24 541534461 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.4124237743 Aug 23 03:22:54 AM UTC 24 Aug 23 03:22:56 AM UTC 24 457075879 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1899419611 Aug 23 03:22:54 AM UTC 24 Aug 23 03:22:56 AM UTC 24 459059874 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2346749502 Aug 23 03:22:54 AM UTC 24 Aug 23 03:22:56 AM UTC 24 484426951 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4184903708 Aug 23 03:22:54 AM UTC 24 Aug 23 03:22:56 AM UTC 24 519070533 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.108682414 Aug 23 03:22:52 AM UTC 24 Aug 23 03:22:56 AM UTC 24 2165212424 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3041318448 Aug 23 03:22:54 AM UTC 24 Aug 23 03:22:56 AM UTC 24 438180131 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2162109543 Aug 23 03:22:55 AM UTC 24 Aug 23 03:22:57 AM UTC 24 417625528 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.3950330480 Aug 23 03:22:55 AM UTC 24 Aug 23 03:22:57 AM UTC 24 542014395 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.39919857 Aug 23 03:22:55 AM UTC 24 Aug 23 03:22:57 AM UTC 24 484115717 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.897303236 Aug 23 03:22:51 AM UTC 24 Aug 23 03:23:02 AM UTC 24 4233037624 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.478545234 Aug 23 03:22:55 AM UTC 24 Aug 23 03:22:57 AM UTC 24 442053045 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.848255856 Aug 23 03:22:56 AM UTC 24 Aug 23 03:22:58 AM UTC 24 280625744 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.358793042 Aug 23 03:22:12 AM UTC 24 Aug 23 03:22:58 AM UTC 24 25944144870 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.1307049133 Aug 23 03:22:56 AM UTC 24 Aug 23 03:22:58 AM UTC 24 437815611 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2901288463 Aug 23 03:22:57 AM UTC 24 Aug 23 03:22:59 AM UTC 24 437050213 ps
T901 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.1746768884 Aug 23 03:22:57 AM UTC 24 Aug 23 03:22:59 AM UTC 24 536917511 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2621789430 Aug 23 03:22:57 AM UTC 24 Aug 23 03:22:59 AM UTC 24 580134143 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2988939192 Aug 23 03:22:57 AM UTC 24 Aug 23 03:22:59 AM UTC 24 426180670 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.562677956 Aug 23 03:22:57 AM UTC 24 Aug 23 03:22:59 AM UTC 24 529626349 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.4266090063 Aug 23 03:22:57 AM UTC 24 Aug 23 03:23:00 AM UTC 24 512178212 ps
T906 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.853032170 Aug 23 03:22:57 AM UTC 24 Aug 23 03:23:00 AM UTC 24 492624865 ps
T907 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.458847425 Aug 23 03:22:57 AM UTC 24 Aug 23 03:23:00 AM UTC 24 466264815 ps
T908 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.1181971572 Aug 23 03:22:57 AM UTC 24 Aug 23 03:23:00 AM UTC 24 499848953 ps
T909 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1509860313 Aug 23 03:22:58 AM UTC 24 Aug 23 03:23:00 AM UTC 24 451168458 ps
T910 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.1485297962 Aug 23 03:22:58 AM UTC 24 Aug 23 03:23:00 AM UTC 24 464990687 ps
T911 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.2856437138 Aug 23 03:22:58 AM UTC 24 Aug 23 03:23:01 AM UTC 24 343337032 ps
T912 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.3015821898 Aug 23 03:22:58 AM UTC 24 Aug 23 03:23:01 AM UTC 24 347585056 ps
T913 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.3130930321 Aug 23 03:22:59 AM UTC 24 Aug 23 03:23:01 AM UTC 24 332816671 ps
T914 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.2547431084 Aug 23 03:22:59 AM UTC 24 Aug 23 03:23:02 AM UTC 24 521660664 ps
T915 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2389379311 Aug 23 03:22:41 AM UTC 24 Aug 23 03:23:03 AM UTC 24 8630777318 ps
T916 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.619465722 Aug 23 03:23:00 AM UTC 24 Aug 23 03:23:03 AM UTC 24 429291287 ps
T917 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.170036378 Aug 23 03:22:10 AM UTC 24 Aug 23 03:23:04 AM UTC 24 26257550962 ps
T918 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3270885670 Aug 23 03:22:47 AM UTC 24 Aug 23 03:23:07 AM UTC 24 8020953104 ps
T919 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.555252049 Aug 23 03:22:07 AM UTC 24 Aug 23 03:23:28 AM UTC 24 26251608569 ps
T920 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1190956088 Aug 23 03:22:17 AM UTC 24 Aug 23 03:23:42 AM UTC 24 34982700381 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1378290490
Short name T7
Test name
Test status
Simulation time 409915097080 ps
CPU time 52.41 seconds
Started Aug 23 04:15:05 AM UTC 24
Finished Aug 23 04:15:59 AM UTC 24
Peak memory 228104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1378290490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.adc_ctrl_stress_all_with_rand_reset.1378290490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2536707864
Short name T35
Test name
Test status
Simulation time 65671143386 ps
CPU time 20.16 seconds
Started Aug 23 04:18:18 AM UTC 24
Finished Aug 23 04:18:39 AM UTC 24
Peak memory 222004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2536707864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.adc_ctrl_stress_all_with_rand_reset.2536707864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1663545582
Short name T50
Test name
Test status
Simulation time 624394955264 ps
CPU time 658.37 seconds
Started Aug 23 04:20:47 AM UTC 24
Finished Aug 23 04:31:51 AM UTC 24
Peak memory 222924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663545582 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.1663545582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.409508765
Short name T41
Test name
Test status
Simulation time 326586385044 ps
CPU time 91.83 seconds
Started Aug 23 04:16:26 AM UTC 24
Finished Aug 23 04:17:59 AM UTC 24
Peak memory 211600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409508765 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.409508765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.1487202119
Short name T165
Test name
Test status
Simulation time 532396974957 ps
CPU time 354.12 seconds
Started Aug 23 04:21:47 AM UTC 24
Finished Aug 23 04:27:46 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487202119 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.1487202119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.2719844015
Short name T59
Test name
Test status
Simulation time 501682861644 ps
CPU time 146.76 seconds
Started Aug 23 04:19:39 AM UTC 24
Finished Aug 23 04:22:08 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719844015 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.2719844015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.952765387
Short name T25
Test name
Test status
Simulation time 12570681462 ps
CPU time 7.89 seconds
Started Aug 23 04:51:57 AM UTC 24
Finished Aug 23 04:52:06 AM UTC 24
Peak memory 221756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=952765387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
18.adc_ctrl_stress_all_with_rand_reset.952765387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3577677031
Short name T10
Test name
Test status
Simulation time 163241374972 ps
CPU time 87.48 seconds
Started Aug 23 04:14:55 AM UTC 24
Finished Aug 23 04:16:24 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577677031 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.3577677031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.72868894
Short name T227
Test name
Test status
Simulation time 541305834358 ps
CPU time 226.22 seconds
Started Aug 23 04:34:02 AM UTC 24
Finished Aug 23 04:37:51 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72868894 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.72868894
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.303434543
Short name T244
Test name
Test status
Simulation time 506245536667 ps
CPU time 1023.32 seconds
Started Aug 23 04:16:35 AM UTC 24
Finished Aug 23 04:33:48 AM UTC 24
Peak memory 212876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303434543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.303434543
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.703464080
Short name T21
Test name
Test status
Simulation time 5896093993 ps
CPU time 6.98 seconds
Started Aug 23 04:22:22 AM UTC 24
Finished Aug 23 04:22:30 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=703464080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.adc_ctrl_stress_all_with_rand_reset.703464080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.3670632923
Short name T327
Test name
Test status
Simulation time 259373593114 ps
CPU time 427.55 seconds
Started Aug 23 05:20:50 AM UTC 24
Finished Aug 23 05:28:02 AM UTC 24
Peak memory 221956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670632923 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.3670632923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.997263102
Short name T3
Test name
Test status
Simulation time 8004971936 ps
CPU time 5.38 seconds
Started Aug 23 04:15:08 AM UTC 24
Finished Aug 23 04:15:14 AM UTC 24
Peak memory 243484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997263102 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.997263102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.1269601697
Short name T32
Test name
Test status
Simulation time 605600267115 ps
CPU time 1615.88 seconds
Started Aug 23 04:18:21 AM UTC 24
Finished Aug 23 04:45:33 AM UTC 24
Peak memory 224952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269601697 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.1269601697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2987757108
Short name T138
Test name
Test status
Simulation time 546058957280 ps
CPU time 308.27 seconds
Started Aug 23 04:21:21 AM UTC 24
Finished Aug 23 04:26:33 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987757108 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.2987757108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.241368997
Short name T224
Test name
Test status
Simulation time 330486106723 ps
CPU time 116.41 seconds
Started Aug 23 04:23:24 AM UTC 24
Finished Aug 23 04:25:23 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241368997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.241368997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3846798520
Short name T71
Test name
Test status
Simulation time 406114193 ps
CPU time 2.88 seconds
Started Aug 23 03:22:11 AM UTC 24
Finished Aug 23 03:22:15 AM UTC 24
Peak memory 221436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846798520 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3846798520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3328093125
Short name T84
Test name
Test status
Simulation time 560605322280 ps
CPU time 285.67 seconds
Started Aug 23 04:14:49 AM UTC 24
Finished Aug 23 04:19:38 AM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328093125 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.3328093125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.615515641
Short name T57
Test name
Test status
Simulation time 338815654 ps
CPU time 1.4 seconds
Started Aug 23 03:22:10 AM UTC 24
Finished Aug 23 03:22:12 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615515641 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.615515641
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.3154507599
Short name T166
Test name
Test status
Simulation time 557609175038 ps
CPU time 106.09 seconds
Started Aug 23 04:31:58 AM UTC 24
Finished Aug 23 04:33:46 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154507599 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.3154507599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.512194329
Short name T5
Test name
Test status
Simulation time 161485701758 ps
CPU time 50.77 seconds
Started Aug 23 04:14:44 AM UTC 24
Finished Aug 23 04:15:37 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512194329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.512194329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.3642778114
Short name T148
Test name
Test status
Simulation time 538823870611 ps
CPU time 78.06 seconds
Started Aug 23 04:56:05 AM UTC 24
Finished Aug 23 04:57:25 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642778114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3642778114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.1378970134
Short name T258
Test name
Test status
Simulation time 502501738614 ps
CPU time 348.73 seconds
Started Aug 23 04:51:02 AM UTC 24
Finished Aug 23 04:56:56 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378970134 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.1378970134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.682454852
Short name T60
Test name
Test status
Simulation time 520359123391 ps
CPU time 111.15 seconds
Started Aug 23 04:24:03 AM UTC 24
Finished Aug 23 04:25:56 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682454852 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.682454852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1785414152
Short name T133
Test name
Test status
Simulation time 524797463355 ps
CPU time 590.92 seconds
Started Aug 23 04:14:58 AM UTC 24
Finished Aug 23 04:24:55 AM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785414152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1785414152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3476176771
Short name T225
Test name
Test status
Simulation time 325102260592 ps
CPU time 712.68 seconds
Started Aug 23 04:15:59 AM UTC 24
Finished Aug 23 04:27:59 AM UTC 24
Peak memory 212832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476176771 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.3476176771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.3636758211
Short name T147
Test name
Test status
Simulation time 512885994888 ps
CPU time 257.55 seconds
Started Aug 23 04:47:10 AM UTC 24
Finished Aug 23 04:51:30 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636758211 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.3636758211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.2274865039
Short name T240
Test name
Test status
Simulation time 494303209798 ps
CPU time 167.73 seconds
Started Aug 23 05:25:51 AM UTC 24
Finished Aug 23 05:28:41 AM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274865039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2274865039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.1829420787
Short name T218
Test name
Test status
Simulation time 500872983445 ps
CPU time 1005.48 seconds
Started Aug 23 04:50:16 AM UTC 24
Finished Aug 23 05:07:11 AM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829420787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1829420787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1924313857
Short name T39
Test name
Test status
Simulation time 7322318536 ps
CPU time 5.41 seconds
Started Aug 23 04:28:37 AM UTC 24
Finished Aug 23 04:28:44 AM UTC 24
Peak memory 211600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1924313857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.adc_ctrl_stress_all_with_rand_reset.1924313857
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.4122577323
Short name T279
Test name
Test status
Simulation time 352432533185 ps
CPU time 195.6 seconds
Started Aug 23 05:28:02 AM UTC 24
Finished Aug 23 05:31:21 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122577323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.4122577323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.4101698689
Short name T169
Test name
Test status
Simulation time 574348823996 ps
CPU time 330.63 seconds
Started Aug 23 05:11:31 AM UTC 24
Finished Aug 23 05:17:05 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101698689 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.4101698689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.2586007828
Short name T226
Test name
Test status
Simulation time 341690517019 ps
CPU time 161.94 seconds
Started Aug 23 04:26:10 AM UTC 24
Finished Aug 23 04:28:55 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586007828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2586007828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.1859203191
Short name T288
Test name
Test status
Simulation time 525629064042 ps
CPU time 590.06 seconds
Started Aug 23 05:45:06 AM UTC 24
Finished Aug 23 05:55:02 AM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859203191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1859203191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3217736708
Short name T61
Test name
Test status
Simulation time 9302788019 ps
CPU time 5.98 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:11 AM UTC 24
Peak memory 211656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217736708 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.3217736708
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2116645585
Short name T18
Test name
Test status
Simulation time 343371717 ps
CPU time 0.96 seconds
Started Aug 23 04:15:15 AM UTC 24
Finished Aug 23 04:15:18 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116645585 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2116645585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.3221243188
Short name T142
Test name
Test status
Simulation time 328011119435 ps
CPU time 202.34 seconds
Started Aug 23 04:27:54 AM UTC 24
Finished Aug 23 04:31:19 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221243188 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.3221243188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2699770482
Short name T278
Test name
Test status
Simulation time 492396847992 ps
CPU time 1058.46 seconds
Started Aug 23 04:29:05 AM UTC 24
Finished Aug 23 04:46:53 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699770482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2699770482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.864484203
Short name T156
Test name
Test status
Simulation time 523315302659 ps
CPU time 1014.99 seconds
Started Aug 23 04:55:47 AM UTC 24
Finished Aug 23 05:12:52 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864484203 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.864484203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.1141494102
Short name T271
Test name
Test status
Simulation time 504582014295 ps
CPU time 287.58 seconds
Started Aug 23 04:54:13 AM UTC 24
Finished Aug 23 04:59:03 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141494102 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.1141494102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.1644464398
Short name T282
Test name
Test status
Simulation time 534163528248 ps
CPU time 1217.19 seconds
Started Aug 23 05:29:54 AM UTC 24
Finished Aug 23 05:50:23 AM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644464398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1644464398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.2101634992
Short name T239
Test name
Test status
Simulation time 494828663478 ps
CPU time 1035.03 seconds
Started Aug 23 05:30:25 AM UTC 24
Finished Aug 23 05:47:50 AM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101634992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2101634992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3058192455
Short name T246
Test name
Test status
Simulation time 508353687268 ps
CPU time 568.97 seconds
Started Aug 23 04:46:06 AM UTC 24
Finished Aug 23 04:55:42 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058192455 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.3058192455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.1946990020
Short name T260
Test name
Test status
Simulation time 483068080707 ps
CPU time 1060.73 seconds
Started Aug 23 04:43:17 AM UTC 24
Finished Aug 23 05:01:09 AM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946990020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1946990020
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.2193784551
Short name T193
Test name
Test status
Simulation time 376087561989 ps
CPU time 857.2 seconds
Started Aug 23 05:03:15 AM UTC 24
Finished Aug 23 05:17:41 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193784551 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.2193784551
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.3909795814
Short name T44
Test name
Test status
Simulation time 116069176588 ps
CPU time 593.52 seconds
Started Aug 23 04:15:04 AM UTC 24
Finished Aug 23 04:25:03 AM UTC 24
Peak memory 213040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909795814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3909795814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.1487397534
Short name T295
Test name
Test status
Simulation time 370279371309 ps
CPU time 835.69 seconds
Started Aug 23 05:48:41 AM UTC 24
Finished Aug 23 06:02:45 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487397534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1487397534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.106611372
Short name T272
Test name
Test status
Simulation time 873540883471 ps
CPU time 1039.11 seconds
Started Aug 23 05:12:52 AM UTC 24
Finished Aug 23 05:30:21 AM UTC 24
Peak memory 212376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106611372 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.106611372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2178430768
Short name T223
Test name
Test status
Simulation time 325629488785 ps
CPU time 165.64 seconds
Started Aug 23 04:23:23 AM UTC 24
Finished Aug 23 04:26:11 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178430768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2178430768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2000436979
Short name T284
Test name
Test status
Simulation time 328023038693 ps
CPU time 712.31 seconds
Started Aug 23 04:34:57 AM UTC 24
Finished Aug 23 04:46:57 AM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000436979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2000436979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.44612849
Short name T264
Test name
Test status
Simulation time 335079042010 ps
CPU time 522.68 seconds
Started Aug 23 05:36:48 AM UTC 24
Finished Aug 23 05:45:36 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44612849 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.44612849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2019048931
Short name T13
Test name
Test status
Simulation time 171483340519 ps
CPU time 89.12 seconds
Started Aug 23 04:15:23 AM UTC 24
Finished Aug 23 04:16:54 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019048931 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.2019048931
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.415788622
Short name T168
Test name
Test status
Simulation time 539092826169 ps
CPU time 135.29 seconds
Started Aug 23 05:03:24 AM UTC 24
Finished Aug 23 05:05:41 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415788622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.415788622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.4030193693
Short name T299
Test name
Test status
Simulation time 492260410404 ps
CPU time 947.25 seconds
Started Aug 23 05:01:52 AM UTC 24
Finished Aug 23 05:17:48 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030193693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.4030193693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.312043151
Short name T304
Test name
Test status
Simulation time 342402605653 ps
CPU time 474.48 seconds
Started Aug 23 05:05:20 AM UTC 24
Finished Aug 23 05:13:20 AM UTC 24
Peak memory 211656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312043151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.312043151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.618917119
Short name T297
Test name
Test status
Simulation time 511301616181 ps
CPU time 123.12 seconds
Started Aug 23 05:31:16 AM UTC 24
Finished Aug 23 05:33:21 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618917119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.618917119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.3710680075
Short name T210
Test name
Test status
Simulation time 76349219312 ps
CPU time 421.49 seconds
Started Aug 23 04:42:55 AM UTC 24
Finished Aug 23 04:50:01 AM UTC 24
Peak memory 211960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710680075 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.3710680075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.3478358025
Short name T92
Test name
Test status
Simulation time 513150244257 ps
CPU time 178.76 seconds
Started Aug 23 04:50:24 AM UTC 24
Finished Aug 23 04:53:25 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478358025 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.3478358025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.3043757329
Short name T173
Test name
Test status
Simulation time 583931818151 ps
CPU time 300.96 seconds
Started Aug 23 05:00:34 AM UTC 24
Finished Aug 23 05:05:39 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043757329 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.3043757329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1750015786
Short name T43
Test name
Test status
Simulation time 96645724227 ps
CPU time 318.58 seconds
Started Aug 23 04:18:00 AM UTC 24
Finished Aug 23 04:23:22 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750015786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1750015786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.558185093
Short name T331
Test name
Test status
Simulation time 327809496449 ps
CPU time 105.15 seconds
Started Aug 23 05:24:38 AM UTC 24
Finished Aug 23 05:26:25 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558185093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.558185093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.3003859656
Short name T301
Test name
Test status
Simulation time 327708474491 ps
CPU time 299.9 seconds
Started Aug 23 05:39:56 AM UTC 24
Finished Aug 23 05:45:00 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003859656 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.3003859656
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.1054588647
Short name T308
Test name
Test status
Simulation time 347877369936 ps
CPU time 144.14 seconds
Started Aug 23 05:46:08 AM UTC 24
Finished Aug 23 05:48:34 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054588647 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.1054588647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.2424045619
Short name T330
Test name
Test status
Simulation time 497156760160 ps
CPU time 1119.88 seconds
Started Aug 23 05:49:21 AM UTC 24
Finished Aug 23 06:08:12 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424045619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2424045619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.2777094388
Short name T177
Test name
Test status
Simulation time 490696771667 ps
CPU time 219.9 seconds
Started Aug 23 05:56:31 AM UTC 24
Finished Aug 23 06:00:14 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777094388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2777094388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3852763299
Short name T857
Test name
Test status
Simulation time 8585829980 ps
CPU time 6.66 seconds
Started Aug 23 03:22:38 AM UTC 24
Finished Aug 23 03:22:46 AM UTC 24
Peak memory 211568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852763299 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.3852763299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3890937391
Short name T303
Test name
Test status
Simulation time 491435636110 ps
CPU time 1047.8 seconds
Started Aug 23 04:59:19 AM UTC 24
Finished Aug 23 05:16:57 AM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890937391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3890937391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3108085535
Short name T243
Test name
Test status
Simulation time 355696498768 ps
CPU time 68.75 seconds
Started Aug 23 05:00:40 AM UTC 24
Finished Aug 23 05:01:50 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108085535 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.3108085535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.3017186793
Short name T292
Test name
Test status
Simulation time 167674086578 ps
CPU time 390.75 seconds
Started Aug 23 05:19:15 AM UTC 24
Finished Aug 23 05:25:51 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017186793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3017186793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3270885670
Short name T918
Test name
Test status
Simulation time 8020953104 ps
CPU time 18.5 seconds
Started Aug 23 03:22:47 AM UTC 24
Finished Aug 23 03:23:07 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270885670 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.3270885670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.1250095668
Short name T228
Test name
Test status
Simulation time 617143072982 ps
CPU time 706.47 seconds
Started Aug 23 04:38:01 AM UTC 24
Finished Aug 23 04:49:55 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250095668 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.1250095668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.3798966841
Short name T322
Test name
Test status
Simulation time 337472542426 ps
CPU time 114.68 seconds
Started Aug 23 05:17:58 AM UTC 24
Finished Aug 23 05:19:55 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798966841 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.3798966841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.1081220199
Short name T313
Test name
Test status
Simulation time 495017791537 ps
CPU time 968.5 seconds
Started Aug 23 05:17:09 AM UTC 24
Finished Aug 23 05:33:28 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081220199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1081220199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.967835173
Short name T693
Test name
Test status
Simulation time 143927029767 ps
CPU time 699.95 seconds
Started Aug 23 05:30:16 AM UTC 24
Finished Aug 23 05:42:03 AM UTC 24
Peak memory 213216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967835173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.967835173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.125071448
Short name T215
Test name
Test status
Simulation time 114124718683 ps
CPU time 527.56 seconds
Started Aug 23 05:36:19 AM UTC 24
Finished Aug 23 05:45:12 AM UTC 24
Peak memory 212768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125071448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.125071448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.1925404776
Short name T334
Test name
Test status
Simulation time 310831985809 ps
CPU time 895.16 seconds
Started Aug 23 05:47:03 AM UTC 24
Finished Aug 23 06:02:07 AM UTC 24
Peak memory 212668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925404776 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.1925404776
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.742392763
Short name T336
Test name
Test status
Simulation time 163133376832 ps
CPU time 162.35 seconds
Started Aug 23 05:55:24 AM UTC 24
Finished Aug 23 05:58:09 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742392763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.742392763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1715806343
Short name T40
Test name
Test status
Simulation time 6872850564 ps
CPU time 9.06 seconds
Started Aug 23 04:30:36 AM UTC 24
Finished Aug 23 04:30:46 AM UTC 24
Peak memory 222084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1715806343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.adc_ctrl_stress_all_with_rand_reset.1715806343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2152585981
Short name T65
Test name
Test status
Simulation time 478783446 ps
CPU time 1.55 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:06 AM UTC 24
Peak memory 209916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152585981 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2152585981
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.2816378922
Short name T1
Test name
Test status
Simulation time 5670729375 ps
CPU time 3.67 seconds
Started Aug 23 04:14:35 AM UTC 24
Finished Aug 23 04:14:40 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816378922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2816378922
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.737168717
Short name T277
Test name
Test status
Simulation time 331872389620 ps
CPU time 746.47 seconds
Started Aug 23 04:31:25 AM UTC 24
Finished Aug 23 04:44:00 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737168717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.737168717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.4084987071
Short name T285
Test name
Test status
Simulation time 176250224979 ps
CPU time 173.95 seconds
Started Aug 23 04:44:19 AM UTC 24
Finished Aug 23 04:47:16 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084987071 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.4084987071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3476410647
Short name T238
Test name
Test status
Simulation time 405936460482 ps
CPU time 742.54 seconds
Started Aug 23 04:53:42 AM UTC 24
Finished Aug 23 05:06:12 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476410647 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.3476410647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.952651022
Short name T337
Test name
Test status
Simulation time 352754740634 ps
CPU time 799.79 seconds
Started Aug 23 05:02:27 AM UTC 24
Finished Aug 23 05:15:54 AM UTC 24
Peak memory 212684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952651022 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.952651022
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.705380444
Short name T309
Test name
Test status
Simulation time 325244471927 ps
CPU time 339.43 seconds
Started Aug 23 05:21:10 AM UTC 24
Finished Aug 23 05:26:54 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705380444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.705380444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.1215587109
Short name T294
Test name
Test status
Simulation time 548082077710 ps
CPU time 556.48 seconds
Started Aug 23 05:30:38 AM UTC 24
Finished Aug 23 05:40:01 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215587109 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.1215587109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.3011130701
Short name T291
Test name
Test status
Simulation time 522797993535 ps
CPU time 82.4 seconds
Started Aug 23 05:38:13 AM UTC 24
Finished Aug 23 05:39:37 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011130701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3011130701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.789684856
Short name T213
Test name
Test status
Simulation time 659198039969 ps
CPU time 1492.29 seconds
Started Aug 23 05:51:03 AM UTC 24
Finished Aug 23 06:16:09 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789684856 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.789684856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.1171890932
Short name T296
Test name
Test status
Simulation time 519033737523 ps
CPU time 349.03 seconds
Started Aug 23 05:55:13 AM UTC 24
Finished Aug 23 06:01:06 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171890932 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.1171890932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4244380159
Short name T128
Test name
Test status
Simulation time 950445146 ps
CPU time 3.06 seconds
Started Aug 23 03:22:05 AM UTC 24
Finished Aug 23 03:22:09 AM UTC 24
Peak memory 211364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244380159 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.4244380159
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1942169226
Short name T58
Test name
Test status
Simulation time 26511305682 ps
CPU time 10.19 seconds
Started Aug 23 03:22:05 AM UTC 24
Finished Aug 23 03:22:16 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942169226 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.1942169226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1711615825
Short name T107
Test name
Test status
Simulation time 1287400180 ps
CPU time 2.06 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:07 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711615825 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.1711615825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.36374112
Short name T66
Test name
Test status
Simulation time 634883169 ps
CPU time 1.07 seconds
Started Aug 23 03:22:05 AM UTC 24
Finished Aug 23 03:22:07 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=36374112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_
mem_rw_with_rand_reset.36374112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2416087176
Short name T55
Test name
Test status
Simulation time 488529938 ps
CPU time 1.65 seconds
Started Aug 23 03:22:05 AM UTC 24
Finished Aug 23 03:22:07 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416087176 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2416087176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.522575188
Short name T802
Test name
Test status
Simulation time 338843466 ps
CPU time 1.2 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:06 AM UTC 24
Peak memory 210516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522575188 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.522575188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1576651222
Short name T123
Test name
Test status
Simulation time 2326541358 ps
CPU time 1.31 seconds
Started Aug 23 03:22:05 AM UTC 24
Finished Aug 23 03:22:07 AM UTC 24
Peak memory 210284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576651222 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.1576651222
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1371459413
Short name T111
Test name
Test status
Simulation time 1364335315 ps
CPU time 3.73 seconds
Started Aug 23 03:22:07 AM UTC 24
Finished Aug 23 03:22:11 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371459413 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.1371459413
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.555252049
Short name T919
Test name
Test status
Simulation time 26251608569 ps
CPU time 79.3 seconds
Started Aug 23 03:22:07 AM UTC 24
Finished Aug 23 03:23:28 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555252049 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.555252049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2652168148
Short name T109
Test name
Test status
Simulation time 1241918030 ps
CPU time 3.12 seconds
Started Aug 23 03:22:06 AM UTC 24
Finished Aug 23 03:22:11 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652168148 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.2652168148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2699523584
Short name T74
Test name
Test status
Simulation time 343662923 ps
CPU time 1.02 seconds
Started Aug 23 03:22:08 AM UTC 24
Finished Aug 23 03:22:10 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2699523584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cs
r_mem_rw_with_rand_reset.2699523584
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2055697372
Short name T108
Test name
Test status
Simulation time 388962735 ps
CPU time 1.04 seconds
Started Aug 23 03:22:07 AM UTC 24
Finished Aug 23 03:22:09 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055697372 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2055697372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3907790679
Short name T803
Test name
Test status
Simulation time 439714033 ps
CPU time 0.84 seconds
Started Aug 23 03:22:06 AM UTC 24
Finished Aug 23 03:22:08 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907790679 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3907790679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3724290768
Short name T56
Test name
Test status
Simulation time 5019742457 ps
CPU time 3.05 seconds
Started Aug 23 03:22:08 AM UTC 24
Finished Aug 23 03:22:12 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724290768 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.3724290768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1793716423
Short name T70
Test name
Test status
Simulation time 529399086 ps
CPU time 2.95 seconds
Started Aug 23 03:22:06 AM UTC 24
Finished Aug 23 03:22:10 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793716423 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1793716423
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3659268370
Short name T63
Test name
Test status
Simulation time 4497136352 ps
CPU time 10.98 seconds
Started Aug 23 03:22:06 AM UTC 24
Finished Aug 23 03:22:19 AM UTC 24
Peak memory 211588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659268370 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.3659268370
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2722650266
Short name T837
Test name
Test status
Simulation time 461893134 ps
CPU time 1.8 seconds
Started Aug 23 03:22:34 AM UTC 24
Finished Aug 23 03:22:37 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2722650266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c
sr_mem_rw_with_rand_reset.2722650266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3339922213
Short name T834
Test name
Test status
Simulation time 321222583 ps
CPU time 1.31 seconds
Started Aug 23 03:22:33 AM UTC 24
Finished Aug 23 03:22:36 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339922213 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3339922213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.1022089055
Short name T831
Test name
Test status
Simulation time 348120077 ps
CPU time 0.91 seconds
Started Aug 23 03:22:32 AM UTC 24
Finished Aug 23 03:22:34 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022089055 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1022089055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3314957602
Short name T842
Test name
Test status
Simulation time 2317056033 ps
CPU time 3.15 seconds
Started Aug 23 03:22:34 AM UTC 24
Finished Aug 23 03:22:39 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314957602 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.3314957602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2668603886
Short name T832
Test name
Test status
Simulation time 470639754 ps
CPU time 2.23 seconds
Started Aug 23 03:22:31 AM UTC 24
Finished Aug 23 03:22:35 AM UTC 24
Peak memory 221560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668603886 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2668603886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2997655230
Short name T835
Test name
Test status
Simulation time 4364866966 ps
CPU time 3.66 seconds
Started Aug 23 03:22:31 AM UTC 24
Finished Aug 23 03:22:36 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997655230 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.2997655230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.183214553
Short name T843
Test name
Test status
Simulation time 526017088 ps
CPU time 1.87 seconds
Started Aug 23 03:22:36 AM UTC 24
Finished Aug 23 03:22:39 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=183214553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_cs
r_mem_rw_with_rand_reset.183214553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.553091635
Short name T121
Test name
Test status
Simulation time 349412180 ps
CPU time 0.84 seconds
Started Aug 23 03:22:36 AM UTC 24
Finished Aug 23 03:22:38 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553091635 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.553091635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3123642134
Short name T836
Test name
Test status
Simulation time 457758642 ps
CPU time 1.45 seconds
Started Aug 23 03:22:34 AM UTC 24
Finished Aug 23 03:22:37 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123642134 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3123642134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2297559847
Short name T844
Test name
Test status
Simulation time 3353232315 ps
CPU time 2.98 seconds
Started Aug 23 03:22:36 AM UTC 24
Finished Aug 23 03:22:40 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297559847 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.2297559847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4253423287
Short name T840
Test name
Test status
Simulation time 386262688 ps
CPU time 1.93 seconds
Started Aug 23 03:22:34 AM UTC 24
Finished Aug 23 03:22:37 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253423287 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.4253423287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4273172802
Short name T848
Test name
Test status
Simulation time 4267098879 ps
CPU time 5.78 seconds
Started Aug 23 03:22:34 AM UTC 24
Finished Aug 23 03:22:41 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273172802 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.4273172802
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1838987348
Short name T846
Test name
Test status
Simulation time 334123844 ps
CPU time 1.54 seconds
Started Aug 23 03:22:38 AM UTC 24
Finished Aug 23 03:22:41 AM UTC 24
Peak memory 209984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1838987348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c
sr_mem_rw_with_rand_reset.1838987348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3426239297
Short name T122
Test name
Test status
Simulation time 375003148 ps
CPU time 1.43 seconds
Started Aug 23 03:22:38 AM UTC 24
Finished Aug 23 03:22:41 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426239297 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3426239297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.369990063
Short name T841
Test name
Test status
Simulation time 684575977 ps
CPU time 0.66 seconds
Started Aug 23 03:22:37 AM UTC 24
Finished Aug 23 03:22:39 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369990063 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.369990063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3162428135
Short name T855
Test name
Test status
Simulation time 4909828140 ps
CPU time 5.54 seconds
Started Aug 23 03:22:38 AM UTC 24
Finished Aug 23 03:22:45 AM UTC 24
Peak memory 211656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162428135 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.3162428135
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3274767528
Short name T845
Test name
Test status
Simulation time 933258090 ps
CPU time 2.52 seconds
Started Aug 23 03:22:37 AM UTC 24
Finished Aug 23 03:22:40 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274767528 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3274767528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3382813367
Short name T866
Test name
Test status
Simulation time 4571232768 ps
CPU time 11.05 seconds
Started Aug 23 03:22:37 AM UTC 24
Finished Aug 23 03:22:49 AM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382813367 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.3382813367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.43327060
Short name T849
Test name
Test status
Simulation time 725446520 ps
CPU time 1 seconds
Started Aug 23 03:22:39 AM UTC 24
Finished Aug 23 03:22:42 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=43327060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr
_mem_rw_with_rand_reset.43327060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3518957824
Short name T116
Test name
Test status
Simulation time 527477640 ps
CPU time 0.94 seconds
Started Aug 23 03:22:39 AM UTC 24
Finished Aug 23 03:22:41 AM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518957824 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3518957824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.3135041561
Short name T847
Test name
Test status
Simulation time 302469350 ps
CPU time 0.69 seconds
Started Aug 23 03:22:39 AM UTC 24
Finished Aug 23 03:22:41 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135041561 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3135041561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3412485909
Short name T858
Test name
Test status
Simulation time 4698476840 ps
CPU time 5.54 seconds
Started Aug 23 03:22:39 AM UTC 24
Finished Aug 23 03:22:46 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412485909 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.3412485909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3006241719
Short name T850
Test name
Test status
Simulation time 514218326 ps
CPU time 2.28 seconds
Started Aug 23 03:22:38 AM UTC 24
Finished Aug 23 03:22:42 AM UTC 24
Peak memory 211312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006241719 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3006241719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3105236034
Short name T854
Test name
Test status
Simulation time 396182318 ps
CPU time 1.04 seconds
Started Aug 23 03:22:42 AM UTC 24
Finished Aug 23 03:22:45 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3105236034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_c
sr_mem_rw_with_rand_reset.3105236034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.140098602
Short name T117
Test name
Test status
Simulation time 376370913 ps
CPU time 1.42 seconds
Started Aug 23 03:22:41 AM UTC 24
Finished Aug 23 03:22:44 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140098602 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.140098602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2763306590
Short name T851
Test name
Test status
Simulation time 349749490 ps
CPU time 0.75 seconds
Started Aug 23 03:22:41 AM UTC 24
Finished Aug 23 03:22:43 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763306590 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2763306590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1670371377
Short name T861
Test name
Test status
Simulation time 2162034279 ps
CPU time 3.7 seconds
Started Aug 23 03:22:42 AM UTC 24
Finished Aug 23 03:22:47 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670371377 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.1670371377
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4274279218
Short name T852
Test name
Test status
Simulation time 849202630 ps
CPU time 2.65 seconds
Started Aug 23 03:22:40 AM UTC 24
Finished Aug 23 03:22:44 AM UTC 24
Peak memory 211444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274279218 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4274279218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2389379311
Short name T915
Test name
Test status
Simulation time 8630777318 ps
CPU time 19.92 seconds
Started Aug 23 03:22:41 AM UTC 24
Finished Aug 23 03:23:03 AM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389379311 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.2389379311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1921649682
Short name T860
Test name
Test status
Simulation time 410135627 ps
CPU time 1.16 seconds
Started Aug 23 03:22:45 AM UTC 24
Finished Aug 23 03:22:47 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1921649682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_c
sr_mem_rw_with_rand_reset.1921649682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1449791039
Short name T859
Test name
Test status
Simulation time 501937613 ps
CPU time 0.88 seconds
Started Aug 23 03:22:44 AM UTC 24
Finished Aug 23 03:22:46 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449791039 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1449791039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3072119467
Short name T853
Test name
Test status
Simulation time 629731832 ps
CPU time 0.63 seconds
Started Aug 23 03:22:42 AM UTC 24
Finished Aug 23 03:22:44 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072119467 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3072119467
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2894609873
Short name T872
Test name
Test status
Simulation time 2651953184 ps
CPU time 5.74 seconds
Started Aug 23 03:22:45 AM UTC 24
Finished Aug 23 03:22:51 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894609873 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.2894609873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3682738406
Short name T856
Test name
Test status
Simulation time 361579344 ps
CPU time 2.09 seconds
Started Aug 23 03:22:42 AM UTC 24
Finished Aug 23 03:22:46 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682738406 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3682738406
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1201730479
Short name T350
Test name
Test status
Simulation time 8507832645 ps
CPU time 7.08 seconds
Started Aug 23 03:22:42 AM UTC 24
Finished Aug 23 03:22:51 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201730479 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.1201730479
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.126183242
Short name T869
Test name
Test status
Simulation time 403263276 ps
CPU time 1.92 seconds
Started Aug 23 03:22:47 AM UTC 24
Finished Aug 23 03:22:50 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=126183242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_cs
r_mem_rw_with_rand_reset.126183242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2611411807
Short name T863
Test name
Test status
Simulation time 397766783 ps
CPU time 0.89 seconds
Started Aug 23 03:22:46 AM UTC 24
Finished Aug 23 03:22:48 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611411807 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2611411807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.226532548
Short name T862
Test name
Test status
Simulation time 368782468 ps
CPU time 0.87 seconds
Started Aug 23 03:22:46 AM UTC 24
Finished Aug 23 03:22:48 AM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226532548 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.226532548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2226539164
Short name T867
Test name
Test status
Simulation time 2520884684 ps
CPU time 1.44 seconds
Started Aug 23 03:22:47 AM UTC 24
Finished Aug 23 03:22:49 AM UTC 24
Peak memory 209984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226539164 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.2226539164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.258056087
Short name T864
Test name
Test status
Simulation time 661188331 ps
CPU time 2.62 seconds
Started Aug 23 03:22:45 AM UTC 24
Finished Aug 23 03:22:48 AM UTC 24
Peak memory 221388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258056087 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.258056087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3623454848
Short name T878
Test name
Test status
Simulation time 4781310693 ps
CPU time 6.26 seconds
Started Aug 23 03:22:46 AM UTC 24
Finished Aug 23 03:22:53 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623454848 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.3623454848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2010508402
Short name T870
Test name
Test status
Simulation time 581712918 ps
CPU time 1.09 seconds
Started Aug 23 03:22:48 AM UTC 24
Finished Aug 23 03:22:50 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2010508402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c
sr_mem_rw_with_rand_reset.2010508402
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1070642125
Short name T118
Test name
Test status
Simulation time 359604552 ps
CPU time 0.8 seconds
Started Aug 23 03:22:48 AM UTC 24
Finished Aug 23 03:22:50 AM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070642125 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1070642125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.3324751432
Short name T871
Test name
Test status
Simulation time 474370342 ps
CPU time 1.57 seconds
Started Aug 23 03:22:48 AM UTC 24
Finished Aug 23 03:22:50 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324751432 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3324751432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1431065538
Short name T884
Test name
Test status
Simulation time 4718943338 ps
CPU time 5.32 seconds
Started Aug 23 03:22:48 AM UTC 24
Finished Aug 23 03:22:54 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431065538 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.1431065538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1568059803
Short name T868
Test name
Test status
Simulation time 960216865 ps
CPU time 1.67 seconds
Started Aug 23 03:22:47 AM UTC 24
Finished Aug 23 03:22:50 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568059803 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1568059803
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.341868478
Short name T875
Test name
Test status
Simulation time 405436952 ps
CPU time 1.16 seconds
Started Aug 23 03:22:50 AM UTC 24
Finished Aug 23 03:22:52 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=341868478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_cs
r_mem_rw_with_rand_reset.341868478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3959216478
Short name T874
Test name
Test status
Simulation time 529948116 ps
CPU time 0.93 seconds
Started Aug 23 03:22:50 AM UTC 24
Finished Aug 23 03:22:52 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959216478 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3959216478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.2961017246
Short name T873
Test name
Test status
Simulation time 397662108 ps
CPU time 0.79 seconds
Started Aug 23 03:22:50 AM UTC 24
Finished Aug 23 03:22:52 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961017246 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2961017246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2628006576
Short name T882
Test name
Test status
Simulation time 2339263590 ps
CPU time 2.69 seconds
Started Aug 23 03:22:50 AM UTC 24
Finished Aug 23 03:22:54 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628006576 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.2628006576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1168256537
Short name T876
Test name
Test status
Simulation time 942800192 ps
CPU time 2.47 seconds
Started Aug 23 03:22:49 AM UTC 24
Finished Aug 23 03:22:53 AM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168256537 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1168256537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2631051444
Short name T879
Test name
Test status
Simulation time 4335468250 ps
CPU time 2.95 seconds
Started Aug 23 03:22:49 AM UTC 24
Finished Aug 23 03:22:53 AM UTC 24
Peak memory 211656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631051444 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.2631051444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3071827944
Short name T885
Test name
Test status
Simulation time 312581702 ps
CPU time 1.36 seconds
Started Aug 23 03:22:52 AM UTC 24
Finished Aug 23 03:22:55 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3071827944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_c
sr_mem_rw_with_rand_reset.3071827944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3921351664
Short name T881
Test name
Test status
Simulation time 380424376 ps
CPU time 1.05 seconds
Started Aug 23 03:22:51 AM UTC 24
Finished Aug 23 03:22:53 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921351664 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3921351664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2064493461
Short name T880
Test name
Test status
Simulation time 388284916 ps
CPU time 0.68 seconds
Started Aug 23 03:22:51 AM UTC 24
Finished Aug 23 03:22:53 AM UTC 24
Peak memory 209364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064493461 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2064493461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.108682414
Short name T891
Test name
Test status
Simulation time 2165212424 ps
CPU time 2.56 seconds
Started Aug 23 03:22:52 AM UTC 24
Finished Aug 23 03:22:56 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108682414 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.108682414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2582429663
Short name T877
Test name
Test status
Simulation time 620316492 ps
CPU time 1.59 seconds
Started Aug 23 03:22:50 AM UTC 24
Finished Aug 23 03:22:53 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582429663 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2582429663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.897303236
Short name T896
Test name
Test status
Simulation time 4233037624 ps
CPU time 9.75 seconds
Started Aug 23 03:22:51 AM UTC 24
Finished Aug 23 03:23:02 AM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897303236 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.897303236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.883944470
Short name T805
Test name
Test status
Simulation time 916909390 ps
CPU time 1.55 seconds
Started Aug 23 03:22:11 AM UTC 24
Finished Aug 23 03:22:14 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883944470 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.883944470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.170036378
Short name T917
Test name
Test status
Simulation time 26257550962 ps
CPU time 52.31 seconds
Started Aug 23 03:22:10 AM UTC 24
Finished Aug 23 03:23:04 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170036378 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.170036378
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2310272347
Short name T110
Test name
Test status
Simulation time 1099248346 ps
CPU time 1.29 seconds
Started Aug 23 03:22:09 AM UTC 24
Finished Aug 23 03:22:11 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310272347 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.2310272347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1174497229
Short name T75
Test name
Test status
Simulation time 443811403 ps
CPU time 1.81 seconds
Started Aug 23 03:22:11 AM UTC 24
Finished Aug 23 03:22:14 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1174497229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs
r_mem_rw_with_rand_reset.1174497229
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2994365181
Short name T804
Test name
Test status
Simulation time 511224646 ps
CPU time 0.85 seconds
Started Aug 23 03:22:09 AM UTC 24
Finished Aug 23 03:22:11 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994365181 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2994365181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1085783492
Short name T124
Test name
Test status
Simulation time 2048922475 ps
CPU time 4.73 seconds
Started Aug 23 03:22:11 AM UTC 24
Finished Aug 23 03:22:17 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085783492 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.1085783492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2782182350
Short name T69
Test name
Test status
Simulation time 320068835 ps
CPU time 1.69 seconds
Started Aug 23 03:22:08 AM UTC 24
Finished Aug 23 03:22:10 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782182350 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2782182350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2707816189
Short name T62
Test name
Test status
Simulation time 8624892554 ps
CPU time 5.13 seconds
Started Aug 23 03:22:08 AM UTC 24
Finished Aug 23 03:22:14 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707816189 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.2707816189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1751103343
Short name T883
Test name
Test status
Simulation time 473905516 ps
CPU time 0.82 seconds
Started Aug 23 03:22:53 AM UTC 24
Finished Aug 23 03:22:54 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751103343 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1751103343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.4124237743
Short name T887
Test name
Test status
Simulation time 457075879 ps
CPU time 1.07 seconds
Started Aug 23 03:22:54 AM UTC 24
Finished Aug 23 03:22:56 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124237743 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4124237743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.3640403309
Short name T886
Test name
Test status
Simulation time 541534461 ps
CPU time 0.88 seconds
Started Aug 23 03:22:54 AM UTC 24
Finished Aug 23 03:22:55 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640403309 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3640403309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1899419611
Short name T888
Test name
Test status
Simulation time 459059874 ps
CPU time 1.11 seconds
Started Aug 23 03:22:54 AM UTC 24
Finished Aug 23 03:22:56 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899419611 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1899419611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2346749502
Short name T889
Test name
Test status
Simulation time 484426951 ps
CPU time 1.15 seconds
Started Aug 23 03:22:54 AM UTC 24
Finished Aug 23 03:22:56 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346749502 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2346749502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3041318448
Short name T892
Test name
Test status
Simulation time 438180131 ps
CPU time 1.47 seconds
Started Aug 23 03:22:54 AM UTC 24
Finished Aug 23 03:22:56 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041318448 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3041318448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4184903708
Short name T890
Test name
Test status
Simulation time 519070533 ps
CPU time 1.14 seconds
Started Aug 23 03:22:54 AM UTC 24
Finished Aug 23 03:22:56 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184903708 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4184903708
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.39919857
Short name T895
Test name
Test status
Simulation time 484115717 ps
CPU time 0.8 seconds
Started Aug 23 03:22:55 AM UTC 24
Finished Aug 23 03:22:57 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39919857 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.39919857
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.3950330480
Short name T894
Test name
Test status
Simulation time 542014395 ps
CPU time 0.78 seconds
Started Aug 23 03:22:55 AM UTC 24
Finished Aug 23 03:22:57 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950330480 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3950330480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2162109543
Short name T893
Test name
Test status
Simulation time 417625528 ps
CPU time 0.74 seconds
Started Aug 23 03:22:55 AM UTC 24
Finished Aug 23 03:22:57 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162109543 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2162109543
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3273091181
Short name T114
Test name
Test status
Simulation time 1200541835 ps
CPU time 4.99 seconds
Started Aug 23 03:22:13 AM UTC 24
Finished Aug 23 03:22:19 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273091181 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.3273091181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.358793042
Short name T119
Test name
Test status
Simulation time 25944144870 ps
CPU time 44.27 seconds
Started Aug 23 03:22:12 AM UTC 24
Finished Aug 23 03:22:58 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358793042 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.358793042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3694626729
Short name T113
Test name
Test status
Simulation time 635029414 ps
CPU time 1.38 seconds
Started Aug 23 03:22:12 AM UTC 24
Finished Aug 23 03:22:15 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694626729 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.3694626729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3650760698
Short name T95
Test name
Test status
Simulation time 530369471 ps
CPU time 1.13 seconds
Started Aug 23 03:22:14 AM UTC 24
Finished Aug 23 03:22:16 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3650760698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cs
r_mem_rw_with_rand_reset.3650760698
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1360116194
Short name T112
Test name
Test status
Simulation time 465939225 ps
CPU time 0.91 seconds
Started Aug 23 03:22:12 AM UTC 24
Finished Aug 23 03:22:14 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360116194 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1360116194
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.396490834
Short name T806
Test name
Test status
Simulation time 301375658 ps
CPU time 0.7 seconds
Started Aug 23 03:22:12 AM UTC 24
Finished Aug 23 03:22:14 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396490834 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.396490834
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3050580485
Short name T126
Test name
Test status
Simulation time 2144128716 ps
CPU time 3.66 seconds
Started Aug 23 03:22:14 AM UTC 24
Finished Aug 23 03:22:19 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050580485 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.3050580485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2268212167
Short name T346
Test name
Test status
Simulation time 4060482798 ps
CPU time 9.45 seconds
Started Aug 23 03:22:12 AM UTC 24
Finished Aug 23 03:22:23 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268212167 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.2268212167
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.478545234
Short name T897
Test name
Test status
Simulation time 442053045 ps
CPU time 1.49 seconds
Started Aug 23 03:22:55 AM UTC 24
Finished Aug 23 03:22:57 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478545234 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.478545234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.848255856
Short name T898
Test name
Test status
Simulation time 280625744 ps
CPU time 1.05 seconds
Started Aug 23 03:22:56 AM UTC 24
Finished Aug 23 03:22:58 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848255856 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.848255856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.1307049133
Short name T899
Test name
Test status
Simulation time 437815611 ps
CPU time 0.98 seconds
Started Aug 23 03:22:56 AM UTC 24
Finished Aug 23 03:22:58 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307049133 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1307049133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.1746768884
Short name T901
Test name
Test status
Simulation time 536917511 ps
CPU time 0.84 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:22:59 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746768884 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1746768884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.4266090063
Short name T905
Test name
Test status
Simulation time 512178212 ps
CPU time 1.55 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:23:00 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266090063 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.4266090063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.853032170
Short name T906
Test name
Test status
Simulation time 492624865 ps
CPU time 1.54 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:23:00 AM UTC 24
Peak memory 209656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853032170 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.853032170
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2988939192
Short name T903
Test name
Test status
Simulation time 426180670 ps
CPU time 1.3 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:22:59 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988939192 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2988939192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.458847425
Short name T907
Test name
Test status
Simulation time 466264815 ps
CPU time 1.63 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:23:00 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458847425 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.458847425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2901288463
Short name T900
Test name
Test status
Simulation time 437050213 ps
CPU time 0.72 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:22:59 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901288463 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2901288463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.562677956
Short name T904
Test name
Test status
Simulation time 529626349 ps
CPU time 1.34 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:22:59 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562677956 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.562677956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2338776485
Short name T813
Test name
Test status
Simulation time 862381744 ps
CPU time 3.05 seconds
Started Aug 23 03:22:18 AM UTC 24
Finished Aug 23 03:22:22 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338776485 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.2338776485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1190956088
Short name T920
Test name
Test status
Simulation time 34982700381 ps
CPU time 84 seconds
Started Aug 23 03:22:17 AM UTC 24
Finished Aug 23 03:23:42 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190956088 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.1190956088
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3930644558
Short name T808
Test name
Test status
Simulation time 828884809 ps
CPU time 2.54 seconds
Started Aug 23 03:22:15 AM UTC 24
Finished Aug 23 03:22:19 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930644558 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.3930644558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3326218110
Short name T809
Test name
Test status
Simulation time 594541450 ps
CPU time 1.4 seconds
Started Aug 23 03:22:18 AM UTC 24
Finished Aug 23 03:22:20 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3326218110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cs
r_mem_rw_with_rand_reset.3326218110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2356878744
Short name T125
Test name
Test status
Simulation time 410886865 ps
CPU time 0.95 seconds
Started Aug 23 03:22:15 AM UTC 24
Finished Aug 23 03:22:17 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356878744 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2356878744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3298673824
Short name T807
Test name
Test status
Simulation time 493075535 ps
CPU time 1 seconds
Started Aug 23 03:22:15 AM UTC 24
Finished Aug 23 03:22:18 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298673824 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3298673824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2087400650
Short name T127
Test name
Test status
Simulation time 2321419462 ps
CPU time 2.46 seconds
Started Aug 23 03:22:18 AM UTC 24
Finished Aug 23 03:22:21 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087400650 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.2087400650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2654167237
Short name T73
Test name
Test status
Simulation time 475560237 ps
CPU time 1.35 seconds
Started Aug 23 03:22:14 AM UTC 24
Finished Aug 23 03:22:17 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654167237 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2654167237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.849151890
Short name T76
Test name
Test status
Simulation time 4156764775 ps
CPU time 8.82 seconds
Started Aug 23 03:22:14 AM UTC 24
Finished Aug 23 03:22:24 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849151890 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.849151890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2621789430
Short name T902
Test name
Test status
Simulation time 580134143 ps
CPU time 0.64 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:22:59 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621789430 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2621789430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.1181971572
Short name T908
Test name
Test status
Simulation time 499848953 ps
CPU time 1.57 seconds
Started Aug 23 03:22:57 AM UTC 24
Finished Aug 23 03:23:00 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181971572 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1181971572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.3015821898
Short name T912
Test name
Test status
Simulation time 347585056 ps
CPU time 1.23 seconds
Started Aug 23 03:22:58 AM UTC 24
Finished Aug 23 03:23:01 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015821898 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3015821898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.1485297962
Short name T910
Test name
Test status
Simulation time 464990687 ps
CPU time 0.82 seconds
Started Aug 23 03:22:58 AM UTC 24
Finished Aug 23 03:23:00 AM UTC 24
Peak memory 209916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485297962 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1485297962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.2856437138
Short name T911
Test name
Test status
Simulation time 343337032 ps
CPU time 1.28 seconds
Started Aug 23 03:22:58 AM UTC 24
Finished Aug 23 03:23:01 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856437138 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2856437138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1509860313
Short name T909
Test name
Test status
Simulation time 451168458 ps
CPU time 0.63 seconds
Started Aug 23 03:22:58 AM UTC 24
Finished Aug 23 03:23:00 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509860313 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1509860313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.3130930321
Short name T913
Test name
Test status
Simulation time 332816671 ps
CPU time 0.7 seconds
Started Aug 23 03:22:59 AM UTC 24
Finished Aug 23 03:23:01 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130930321 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3130930321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.3272719630
Short name T865
Test name
Test status
Simulation time 412551062 ps
CPU time 0.78 seconds
Started Aug 23 03:22:59 AM UTC 24
Finished Aug 23 03:23:01 AM UTC 24
Peak memory 209916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272719630 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3272719630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.2547431084
Short name T914
Test name
Test status
Simulation time 521660664 ps
CPU time 1.62 seconds
Started Aug 23 03:22:59 AM UTC 24
Finished Aug 23 03:23:02 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547431084 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2547431084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.619465722
Short name T916
Test name
Test status
Simulation time 429291287 ps
CPU time 1.58 seconds
Started Aug 23 03:23:00 AM UTC 24
Finished Aug 23 03:23:03 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619465722 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.619465722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1581112325
Short name T814
Test name
Test status
Simulation time 600379925 ps
CPU time 1.49 seconds
Started Aug 23 03:22:20 AM UTC 24
Finished Aug 23 03:22:22 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1581112325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_cs
r_mem_rw_with_rand_reset.1581112325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.863693393
Short name T812
Test name
Test status
Simulation time 448010095 ps
CPU time 1.17 seconds
Started Aug 23 03:22:20 AM UTC 24
Finished Aug 23 03:22:22 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863693393 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.863693393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.881214823
Short name T811
Test name
Test status
Simulation time 472830914 ps
CPU time 0.91 seconds
Started Aug 23 03:22:20 AM UTC 24
Finished Aug 23 03:22:22 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881214823 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.881214823
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.508361448
Short name T822
Test name
Test status
Simulation time 2276227010 ps
CPU time 8.5 seconds
Started Aug 23 03:22:20 AM UTC 24
Finished Aug 23 03:22:29 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508361448 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.508361448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4145256860
Short name T810
Test name
Test status
Simulation time 650642834 ps
CPU time 1.28 seconds
Started Aug 23 03:22:19 AM UTC 24
Finished Aug 23 03:22:21 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145256860 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4145256860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2311648845
Short name T347
Test name
Test status
Simulation time 4444805110 ps
CPU time 10.24 seconds
Started Aug 23 03:22:19 AM UTC 24
Finished Aug 23 03:22:30 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311648845 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.2311648845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1800490853
Short name T818
Test name
Test status
Simulation time 576198939 ps
CPU time 1.11 seconds
Started Aug 23 03:22:24 AM UTC 24
Finished Aug 23 03:22:26 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1800490853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_cs
r_mem_rw_with_rand_reset.1800490853
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2282740090
Short name T815
Test name
Test status
Simulation time 567701145 ps
CPU time 0.96 seconds
Started Aug 23 03:22:23 AM UTC 24
Finished Aug 23 03:22:26 AM UTC 24
Peak memory 209648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282740090 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2282740090
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.1087236907
Short name T816
Test name
Test status
Simulation time 302997410 ps
CPU time 1.09 seconds
Started Aug 23 03:22:23 AM UTC 24
Finished Aug 23 03:22:26 AM UTC 24
Peak memory 209720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087236907 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1087236907
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3178938852
Short name T824
Test name
Test status
Simulation time 5379770219 ps
CPU time 4.91 seconds
Started Aug 23 03:22:23 AM UTC 24
Finished Aug 23 03:22:30 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178938852 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.3178938852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.496372979
Short name T72
Test name
Test status
Simulation time 1011686733 ps
CPU time 2.52 seconds
Started Aug 23 03:22:21 AM UTC 24
Finished Aug 23 03:22:25 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496372979 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.496372979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2856846916
Short name T348
Test name
Test status
Simulation time 4160395945 ps
CPU time 8.4 seconds
Started Aug 23 03:22:22 AM UTC 24
Finished Aug 23 03:22:32 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856846916 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.2856846916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1087492552
Short name T820
Test name
Test status
Simulation time 450281373 ps
CPU time 1.28 seconds
Started Aug 23 03:22:26 AM UTC 24
Finished Aug 23 03:22:29 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1087492552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_cs
r_mem_rw_with_rand_reset.1087492552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4245314455
Short name T115
Test name
Test status
Simulation time 329218259 ps
CPU time 1.01 seconds
Started Aug 23 03:22:25 AM UTC 24
Finished Aug 23 03:22:27 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245314455 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4245314455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1655072106
Short name T817
Test name
Test status
Simulation time 428077822 ps
CPU time 0.81 seconds
Started Aug 23 03:22:24 AM UTC 24
Finished Aug 23 03:22:26 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655072106 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1655072106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2501487131
Short name T833
Test name
Test status
Simulation time 4594906418 ps
CPU time 9.25 seconds
Started Aug 23 03:22:25 AM UTC 24
Finished Aug 23 03:22:36 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501487131 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.2501487131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1409391094
Short name T819
Test name
Test status
Simulation time 579544750 ps
CPU time 1.69 seconds
Started Aug 23 03:22:24 AM UTC 24
Finished Aug 23 03:22:27 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409391094 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1409391094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1367754245
Short name T349
Test name
Test status
Simulation time 8000825457 ps
CPU time 18.73 seconds
Started Aug 23 03:22:24 AM UTC 24
Finished Aug 23 03:22:44 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367754245 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.1367754245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3230027006
Short name T826
Test name
Test status
Simulation time 520779585 ps
CPU time 1.87 seconds
Started Aug 23 03:22:28 AM UTC 24
Finished Aug 23 03:22:31 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3230027006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs
r_mem_rw_with_rand_reset.3230027006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2658712856
Short name T823
Test name
Test status
Simulation time 335948873 ps
CPU time 1.01 seconds
Started Aug 23 03:22:27 AM UTC 24
Finished Aug 23 03:22:30 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658712856 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2658712856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.1076970948
Short name T821
Test name
Test status
Simulation time 487504662 ps
CPU time 0.69 seconds
Started Aug 23 03:22:27 AM UTC 24
Finished Aug 23 03:22:29 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076970948 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1076970948
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.250168193
Short name T827
Test name
Test status
Simulation time 5152316767 ps
CPU time 3.33 seconds
Started Aug 23 03:22:28 AM UTC 24
Finished Aug 23 03:22:33 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250168193 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.250168193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1707856521
Short name T825
Test name
Test status
Simulation time 508610695 ps
CPU time 1.49 seconds
Started Aug 23 03:22:27 AM UTC 24
Finished Aug 23 03:22:30 AM UTC 24
Peak memory 209896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707856521 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1707856521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.678864710
Short name T351
Test name
Test status
Simulation time 8076615220 ps
CPU time 19.44 seconds
Started Aug 23 03:22:27 AM UTC 24
Finished Aug 23 03:22:48 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678864710 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.678864710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1973341840
Short name T830
Test name
Test status
Simulation time 595871117 ps
CPU time 1.17 seconds
Started Aug 23 03:22:31 AM UTC 24
Finished Aug 23 03:22:33 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1973341840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs
r_mem_rw_with_rand_reset.1973341840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1666489207
Short name T120
Test name
Test status
Simulation time 439535670 ps
CPU time 1.56 seconds
Started Aug 23 03:22:31 AM UTC 24
Finished Aug 23 03:22:34 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666489207 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1666489207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2236545930
Short name T829
Test name
Test status
Simulation time 291700273 ps
CPU time 1.19 seconds
Started Aug 23 03:22:31 AM UTC 24
Finished Aug 23 03:22:33 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236545930 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2236545930
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.961476294
Short name T838
Test name
Test status
Simulation time 4585834787 ps
CPU time 5.11 seconds
Started Aug 23 03:22:31 AM UTC 24
Finished Aug 23 03:22:37 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961476294 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.961476294
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2635671581
Short name T828
Test name
Test status
Simulation time 495151781 ps
CPU time 2.32 seconds
Started Aug 23 03:22:30 AM UTC 24
Finished Aug 23 03:22:33 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635671581 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2635671581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3436935673
Short name T839
Test name
Test status
Simulation time 8697862058 ps
CPU time 6.43 seconds
Started Aug 23 03:22:30 AM UTC 24
Finished Aug 23 03:22:37 AM UTC 24
Peak memory 211656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436935673 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.3436935673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.599158625
Short name T34
Test name
Test status
Simulation time 325317163643 ps
CPU time 187.14 seconds
Started Aug 23 04:14:42 AM UTC 24
Finished Aug 23 04:17:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599158625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.599158625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.2473968521
Short name T201
Test name
Test status
Simulation time 321771682237 ps
CPU time 366.49 seconds
Started Aug 23 04:14:37 AM UTC 24
Finished Aug 23 04:20:47 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473968521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2473968521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1033427651
Short name T178
Test name
Test status
Simulation time 487496572866 ps
CPU time 1035.97 seconds
Started Aug 23 04:14:41 AM UTC 24
Finished Aug 23 04:32:07 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033427651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.1033427651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.458900002
Short name T12
Test name
Test status
Simulation time 205027099326 ps
CPU time 113.99 seconds
Started Aug 23 04:14:49 AM UTC 24
Finished Aug 23 04:16:45 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458900002 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.458900002
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.2989088608
Short name T11
Test name
Test status
Simulation time 38939303800 ps
CPU time 89.61 seconds
Started Aug 23 04:15:02 AM UTC 24
Finished Aug 23 04:16:34 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989088608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2989088608
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.708164193
Short name T2
Test name
Test status
Simulation time 5585211655 ps
CPU time 1.43 seconds
Started Aug 23 04:14:59 AM UTC 24
Finished Aug 23 04:15:02 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708164193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.708164193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1652410353
Short name T31
Test name
Test status
Simulation time 218771149075 ps
CPU time 250.93 seconds
Started Aug 23 04:15:05 AM UTC 24
Finished Aug 23 04:19:20 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652410353 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.1652410353
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.478682757
Short name T19
Test name
Test status
Simulation time 295889897 ps
CPU time 1.11 seconds
Started Aug 23 04:16:02 AM UTC 24
Finished Aug 23 04:16:04 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478682757 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.478682757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3426577546
Short name T14
Test name
Test status
Simulation time 162447946121 ps
CPU time 87.4 seconds
Started Aug 23 04:15:38 AM UTC 24
Finished Aug 23 04:17:07 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426577546 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.3426577546
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.4206901615
Short name T221
Test name
Test status
Simulation time 179657988187 ps
CPU time 364.32 seconds
Started Aug 23 04:15:38 AM UTC 24
Finished Aug 23 04:21:47 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206901615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4206901615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3354804586
Short name T15
Test name
Test status
Simulation time 168201877727 ps
CPU time 109.4 seconds
Started Aug 23 04:15:21 AM UTC 24
Finished Aug 23 04:17:12 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354804586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3354804586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.881573465
Short name T259
Test name
Test status
Simulation time 489289690971 ps
CPU time 288.92 seconds
Started Aug 23 04:15:22 AM UTC 24
Finished Aug 23 04:20:14 AM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881573465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.881573465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.3835324523
Short name T220
Test name
Test status
Simulation time 330689242753 ps
CPU time 649.02 seconds
Started Aug 23 04:15:17 AM UTC 24
Finished Aug 23 04:26:13 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835324523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3835324523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.3392763633
Short name T361
Test name
Test status
Simulation time 329015574884 ps
CPU time 358.22 seconds
Started Aug 23 04:15:19 AM UTC 24
Finished Aug 23 04:21:21 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392763633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.3392763633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3885632853
Short name T16
Test name
Test status
Simulation time 607948482128 ps
CPU time 122.5 seconds
Started Aug 23 04:15:27 AM UTC 24
Finished Aug 23 04:17:31 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885632853 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.3885632853
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.192993494
Short name T49
Test name
Test status
Simulation time 108309185254 ps
CPU time 549.37 seconds
Started Aug 23 04:15:49 AM UTC 24
Finished Aug 23 04:25:04 AM UTC 24
Peak memory 212764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192993494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.192993494
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.1182724517
Short name T48
Test name
Test status
Simulation time 33610929226 ps
CPU time 68.48 seconds
Started Aug 23 04:15:45 AM UTC 24
Finished Aug 23 04:16:55 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182724517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1182724517
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.1898246196
Short name T6
Test name
Test status
Simulation time 2736583423 ps
CPU time 6.11 seconds
Started Aug 23 04:15:42 AM UTC 24
Finished Aug 23 04:15:49 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898246196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1898246196
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2270342744
Short name T20
Test name
Test status
Simulation time 7923867371 ps
CPU time 9.8 seconds
Started Aug 23 04:16:01 AM UTC 24
Finished Aug 23 04:16:12 AM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270342744 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2270342744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.3917357763
Short name T4
Test name
Test status
Simulation time 5845757218 ps
CPU time 3.96 seconds
Started Aug 23 04:15:15 AM UTC 24
Finished Aug 23 04:15:21 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917357763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3917357763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4198014258
Short name T8
Test name
Test status
Simulation time 4015078848 ps
CPU time 5.3 seconds
Started Aug 23 04:15:54 AM UTC 24
Finished Aug 23 04:16:01 AM UTC 24
Peak memory 211600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4198014258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.adc_ctrl_stress_all_with_rand_reset.4198014258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.3569434599
Short name T184
Test name
Test status
Simulation time 480453282 ps
CPU time 1.75 seconds
Started Aug 23 04:33:07 AM UTC 24
Finished Aug 23 04:33:10 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569434599 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3569434599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.607230131
Short name T230
Test name
Test status
Simulation time 164156680891 ps
CPU time 119.42 seconds
Started Aug 23 04:32:04 AM UTC 24
Finished Aug 23 04:34:05 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607230131 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.607230131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.1664547729
Short name T232
Test name
Test status
Simulation time 165868876657 ps
CPU time 96.78 seconds
Started Aug 23 04:32:08 AM UTC 24
Finished Aug 23 04:33:46 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664547729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1664547729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1193342058
Short name T388
Test name
Test status
Simulation time 169531679946 ps
CPU time 100.27 seconds
Started Aug 23 04:31:52 AM UTC 24
Finished Aug 23 04:33:34 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193342058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.1193342058
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.3327506330
Short name T172
Test name
Test status
Simulation time 320178011845 ps
CPU time 57.31 seconds
Started Aug 23 04:31:04 AM UTC 24
Finished Aug 23 04:32:03 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327506330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3327506330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.1341544003
Short name T186
Test name
Test status
Simulation time 161447476422 ps
CPU time 34.58 seconds
Started Aug 23 04:31:20 AM UTC 24
Finished Aug 23 04:31:57 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341544003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.1341544003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.152673549
Short name T460
Test name
Test status
Simulation time 629543059645 ps
CPU time 1452.59 seconds
Started Aug 23 04:32:00 AM UTC 24
Finished Aug 23 04:56:26 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152673549 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.152673549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.592918868
Short name T209
Test name
Test status
Simulation time 138870439353 ps
CPU time 692.57 seconds
Started Aug 23 04:32:40 AM UTC 24
Finished Aug 23 04:44:19 AM UTC 24
Peak memory 212828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592918868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.592918868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.3992562475
Short name T389
Test name
Test status
Simulation time 40370240822 ps
CPU time 82.94 seconds
Started Aug 23 04:32:38 AM UTC 24
Finished Aug 23 04:34:02 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992562475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3992562475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.1856881404
Short name T180
Test name
Test status
Simulation time 5240216036 ps
CPU time 12.58 seconds
Started Aug 23 04:32:24 AM UTC 24
Finished Aug 23 04:32:37 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856881404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1856881404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.3807817605
Short name T385
Test name
Test status
Simulation time 5660484331 ps
CPU time 12.7 seconds
Started Aug 23 04:30:49 AM UTC 24
Finished Aug 23 04:31:03 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807817605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3807817605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2964399514
Short name T392
Test name
Test status
Simulation time 233660720463 ps
CPU time 89.94 seconds
Started Aug 23 04:33:01 AM UTC 24
Finished Aug 23 04:34:33 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964399514 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.2964399514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2293408440
Short name T183
Test name
Test status
Simulation time 19295088396 ps
CPU time 11.24 seconds
Started Aug 23 04:32:54 AM UTC 24
Finished Aug 23 04:33:06 AM UTC 24
Peak memory 221764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2293408440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.adc_ctrl_stress_all_with_rand_reset.2293408440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.3904838769
Short name T394
Test name
Test status
Simulation time 404547938 ps
CPU time 0.67 seconds
Started Aug 23 04:34:45 AM UTC 24
Finished Aug 23 04:34:47 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904838769 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3904838769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.1312729826
Short name T233
Test name
Test status
Simulation time 161387583391 ps
CPU time 185.1 seconds
Started Aug 23 04:34:04 AM UTC 24
Finished Aug 23 04:37:11 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312729826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1312729826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.2830578516
Short name T281
Test name
Test status
Simulation time 160485658769 ps
CPU time 196.32 seconds
Started Aug 23 04:33:34 AM UTC 24
Finished Aug 23 04:36:54 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830578516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2830578516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4208004636
Short name T397
Test name
Test status
Simulation time 319827634930 ps
CPU time 77.01 seconds
Started Aug 23 04:33:46 AM UTC 24
Finished Aug 23 04:35:05 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208004636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.4208004636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3310154649
Short name T196
Test name
Test status
Simulation time 330079645160 ps
CPU time 264.31 seconds
Started Aug 23 04:33:17 AM UTC 24
Finished Aug 23 04:37:45 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310154649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3310154649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.3705518254
Short name T439
Test name
Test status
Simulation time 490905461961 ps
CPU time 992.81 seconds
Started Aug 23 04:33:26 AM UTC 24
Finished Aug 23 04:50:09 AM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705518254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.3705518254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2727201540
Short name T251
Test name
Test status
Simulation time 168394568453 ps
CPU time 90.42 seconds
Started Aug 23 04:33:47 AM UTC 24
Finished Aug 23 04:35:20 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727201540 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.2727201540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1410458717
Short name T393
Test name
Test status
Simulation time 406489151937 ps
CPU time 54.64 seconds
Started Aug 23 04:33:48 AM UTC 24
Finished Aug 23 04:34:45 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410458717 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.1410458717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.4255527742
Short name T208
Test name
Test status
Simulation time 71920770361 ps
CPU time 242.91 seconds
Started Aug 23 04:34:34 AM UTC 24
Finished Aug 23 04:38:40 AM UTC 24
Peak memory 212080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255527742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4255527742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.2591775073
Short name T391
Test name
Test status
Simulation time 28709471004 ps
CPU time 14.78 seconds
Started Aug 23 04:34:17 AM UTC 24
Finished Aug 23 04:34:32 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591775073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2591775073
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.1918669191
Short name T390
Test name
Test status
Simulation time 4040686358 ps
CPU time 9.47 seconds
Started Aug 23 04:34:06 AM UTC 24
Finished Aug 23 04:34:16 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918669191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1918669191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.3279600955
Short name T387
Test name
Test status
Simulation time 5998823511 ps
CPU time 14.3 seconds
Started Aug 23 04:33:10 AM UTC 24
Finished Aug 23 04:33:26 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279600955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3279600955
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.3430356237
Short name T153
Test name
Test status
Simulation time 429768527341 ps
CPU time 880.28 seconds
Started Aug 23 04:34:42 AM UTC 24
Finished Aug 23 04:49:31 AM UTC 24
Peak memory 212472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430356237 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.3430356237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.539857125
Short name T274
Test name
Test status
Simulation time 4363575413 ps
CPU time 11.65 seconds
Started Aug 23 04:34:34 AM UTC 24
Finished Aug 23 04:34:47 AM UTC 24
Peak memory 221752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=539857125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
11.adc_ctrl_stress_all_with_rand_reset.539857125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.1304133237
Short name T400
Test name
Test status
Simulation time 329349096 ps
CPU time 0.9 seconds
Started Aug 23 04:37:45 AM UTC 24
Finished Aug 23 04:37:47 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304133237 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1304133237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3044304103
Short name T145
Test name
Test status
Simulation time 350112955853 ps
CPU time 675.8 seconds
Started Aug 23 04:36:44 AM UTC 24
Finished Aug 23 04:48:07 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044304103 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.3044304103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.3893779193
Short name T167
Test name
Test status
Simulation time 498339331177 ps
CPU time 270.27 seconds
Started Aug 23 04:36:55 AM UTC 24
Finished Aug 23 04:41:28 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893779193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3893779193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1860826277
Short name T412
Test name
Test status
Simulation time 168626849175 ps
CPU time 375.74 seconds
Started Aug 23 04:35:06 AM UTC 24
Finished Aug 23 04:41:26 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860826277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.1860826277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.1801700478
Short name T446
Test name
Test status
Simulation time 492835008238 ps
CPU time 1019.47 seconds
Started Aug 23 04:34:47 AM UTC 24
Finished Aug 23 04:51:56 AM UTC 24
Peak memory 212820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801700478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1801700478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.3289539677
Short name T407
Test name
Test status
Simulation time 167569531381 ps
CPU time 318.68 seconds
Started Aug 23 04:34:52 AM UTC 24
Finished Aug 23 04:40:15 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289539677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.3289539677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2289141533
Short name T249
Test name
Test status
Simulation time 359905546127 ps
CPU time 118.96 seconds
Started Aug 23 04:35:14 AM UTC 24
Finished Aug 23 04:37:15 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289141533 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.2289141533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3515281649
Short name T401
Test name
Test status
Simulation time 600171684346 ps
CPU time 153.32 seconds
Started Aug 23 04:35:20 AM UTC 24
Finished Aug 23 04:37:56 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515281649 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.3515281649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2263324582
Short name T53
Test name
Test status
Simulation time 84602515578 ps
CPU time 427.37 seconds
Started Aug 23 04:37:18 AM UTC 24
Finished Aug 23 04:44:29 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263324582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2263324582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.3194813429
Short name T403
Test name
Test status
Simulation time 42794743765 ps
CPU time 45.81 seconds
Started Aug 23 04:37:16 AM UTC 24
Finished Aug 23 04:38:03 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194813429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3194813429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.2513238593
Short name T399
Test name
Test status
Simulation time 5280365427 ps
CPU time 11.23 seconds
Started Aug 23 04:37:12 AM UTC 24
Finished Aug 23 04:37:24 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513238593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2513238593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.402627979
Short name T395
Test name
Test status
Simulation time 6020532585 ps
CPU time 3.15 seconds
Started Aug 23 04:34:47 AM UTC 24
Finished Aug 23 04:34:51 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402627979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.402627979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.1445031215
Short name T236
Test name
Test status
Simulation time 369271866206 ps
CPU time 217.42 seconds
Started Aug 23 04:37:31 AM UTC 24
Finished Aug 23 04:41:11 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445031215 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.1445031215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1047131898
Short name T22
Test name
Test status
Simulation time 792620956 ps
CPU time 3.84 seconds
Started Aug 23 04:37:25 AM UTC 24
Finished Aug 23 04:37:30 AM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1047131898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.adc_ctrl_stress_all_with_rand_reset.1047131898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.521292995
Short name T408
Test name
Test status
Simulation time 382325754 ps
CPU time 1.29 seconds
Started Aug 23 04:40:19 AM UTC 24
Finished Aug 23 04:40:22 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521292995 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.521292995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1743187737
Short name T298
Test name
Test status
Simulation time 173924307651 ps
CPU time 95.46 seconds
Started Aug 23 04:38:41 AM UTC 24
Finished Aug 23 04:40:18 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743187737 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.1743187737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1160636458
Short name T192
Test name
Test status
Simulation time 329802024645 ps
CPU time 348.36 seconds
Started Aug 23 04:39:07 AM UTC 24
Finished Aug 23 04:44:59 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160636458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1160636458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3687931303
Short name T305
Test name
Test status
Simulation time 489946740916 ps
CPU time 1058.89 seconds
Started Aug 23 04:37:57 AM UTC 24
Finished Aug 23 04:55:46 AM UTC 24
Peak memory 212572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687931303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3687931303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.4156695764
Short name T438
Test name
Test status
Simulation time 326862453759 ps
CPU time 720.26 seconds
Started Aug 23 04:37:59 AM UTC 24
Finished Aug 23 04:50:07 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156695764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.4156695764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.2272184233
Short name T342
Test name
Test status
Simulation time 493270818026 ps
CPU time 1082.2 seconds
Started Aug 23 04:37:51 AM UTC 24
Finished Aug 23 04:56:04 AM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272184233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2272184233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.3715732576
Short name T404
Test name
Test status
Simulation time 160523292058 ps
CPU time 90.29 seconds
Started Aug 23 04:37:53 AM UTC 24
Finished Aug 23 04:39:25 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715732576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.3715732576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.156381396
Short name T423
Test name
Test status
Simulation time 201828949845 ps
CPU time 411.74 seconds
Started Aug 23 04:38:03 AM UTC 24
Finished Aug 23 04:45:00 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156381396 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.156381396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.1030850394
Short name T352
Test name
Test status
Simulation time 130122246978 ps
CPU time 422.46 seconds
Started Aug 23 04:39:57 AM UTC 24
Finished Aug 23 04:47:03 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030850394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1030850394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3690154824
Short name T406
Test name
Test status
Simulation time 34734668314 ps
CPU time 17.73 seconds
Started Aug 23 04:39:37 AM UTC 24
Finished Aug 23 04:39:56 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690154824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3690154824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3888338098
Short name T405
Test name
Test status
Simulation time 4587255800 ps
CPU time 9.34 seconds
Started Aug 23 04:39:26 AM UTC 24
Finished Aug 23 04:39:36 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888338098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3888338098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.4165945650
Short name T402
Test name
Test status
Simulation time 5840502351 ps
CPU time 11.83 seconds
Started Aug 23 04:37:48 AM UTC 24
Finished Aug 23 04:38:01 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165945650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.4165945650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.601008323
Short name T54
Test name
Test status
Simulation time 218827407233 ps
CPU time 1032.39 seconds
Started Aug 23 04:40:16 AM UTC 24
Finished Aug 23 04:57:37 AM UTC 24
Peak memory 212764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601008323 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.601008323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3279064251
Short name T409
Test name
Test status
Simulation time 2691489487 ps
CPU time 14.37 seconds
Started Aug 23 04:40:09 AM UTC 24
Finished Aug 23 04:40:24 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3279064251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.adc_ctrl_stress_all_with_rand_reset.3279064251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.295825474
Short name T416
Test name
Test status
Simulation time 366055626 ps
CPU time 1.2 seconds
Started Aug 23 04:43:01 AM UTC 24
Finished Aug 23 04:43:03 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295825474 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.295825474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.2068802705
Short name T242
Test name
Test status
Simulation time 166897972554 ps
CPU time 35.09 seconds
Started Aug 23 04:41:29 AM UTC 24
Finished Aug 23 04:42:05 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068802705 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.2068802705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.4043918544
Short name T144
Test name
Test status
Simulation time 163172630913 ps
CPU time 324.4 seconds
Started Aug 23 04:42:06 AM UTC 24
Finished Aug 23 04:47:34 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043918544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4043918544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.442874445
Short name T320
Test name
Test status
Simulation time 160685634668 ps
CPU time 323.84 seconds
Started Aug 23 04:40:37 AM UTC 24
Finished Aug 23 04:46:05 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442874445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.442874445
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3932598062
Short name T414
Test name
Test status
Simulation time 166310094605 ps
CPU time 91.39 seconds
Started Aug 23 04:41:12 AM UTC 24
Finished Aug 23 04:42:45 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932598062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.3932598062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.279927411
Short name T417
Test name
Test status
Simulation time 164755544384 ps
CPU time 164.11 seconds
Started Aug 23 04:40:25 AM UTC 24
Finished Aug 23 04:43:12 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279927411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.279927411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.4115046701
Short name T420
Test name
Test status
Simulation time 497066333181 ps
CPU time 255.69 seconds
Started Aug 23 04:40:27 AM UTC 24
Finished Aug 23 04:44:46 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115046701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.4115046701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2798301723
Short name T90
Test name
Test status
Simulation time 351626230548 ps
CPU time 680 seconds
Started Aug 23 04:41:18 AM UTC 24
Finished Aug 23 04:52:45 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798301723 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.2798301723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1519196114
Short name T431
Test name
Test status
Simulation time 615033392131 ps
CPU time 337.73 seconds
Started Aug 23 04:41:28 AM UTC 24
Finished Aug 23 04:47:09 AM UTC 24
Peak memory 211788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519196114 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.1519196114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2814244852
Short name T441
Test name
Test status
Simulation time 90117313532 ps
CPU time 444.56 seconds
Started Aug 23 04:42:46 AM UTC 24
Finished Aug 23 04:50:15 AM UTC 24
Peak memory 212084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814244852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2814244852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.2576084307
Short name T415
Test name
Test status
Simulation time 30411317480 ps
CPU time 17.94 seconds
Started Aug 23 04:42:33 AM UTC 24
Finished Aug 23 04:42:52 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576084307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2576084307
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.928312665
Short name T413
Test name
Test status
Simulation time 4106368122 ps
CPU time 2.73 seconds
Started Aug 23 04:42:28 AM UTC 24
Finished Aug 23 04:42:32 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928312665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.928312665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.2672214535
Short name T410
Test name
Test status
Simulation time 6048558119 ps
CPU time 2.54 seconds
Started Aug 23 04:40:22 AM UTC 24
Finished Aug 23 04:40:26 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672214535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2672214535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2568285578
Short name T204
Test name
Test status
Simulation time 10976453125 ps
CPU time 6.58 seconds
Started Aug 23 04:42:53 AM UTC 24
Finished Aug 23 04:43:01 AM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2568285578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.adc_ctrl_stress_all_with_rand_reset.2568285578
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.386088287
Short name T425
Test name
Test status
Simulation time 423526722 ps
CPU time 0.74 seconds
Started Aug 23 04:45:08 AM UTC 24
Finished Aug 23 04:45:10 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386088287 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.386088287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.54270486
Short name T146
Test name
Test status
Simulation time 157371071050 ps
CPU time 336.15 seconds
Started Aug 23 04:44:30 AM UTC 24
Finished Aug 23 04:50:11 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54270486 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.54270486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.498068976
Short name T307
Test name
Test status
Simulation time 365337225171 ps
CPU time 402.63 seconds
Started Aug 23 04:44:47 AM UTC 24
Finished Aug 23 04:51:34 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498068976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.498068976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2816088692
Short name T428
Test name
Test status
Simulation time 325692020095 ps
CPU time 104.07 seconds
Started Aug 23 04:44:00 AM UTC 24
Finished Aug 23 04:45:46 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816088692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.2816088692
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.700529329
Short name T286
Test name
Test status
Simulation time 326152041608 ps
CPU time 643.7 seconds
Started Aug 23 04:43:13 AM UTC 24
Finished Aug 23 04:54:03 AM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700529329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.700529329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.3486420366
Short name T429
Test name
Test status
Simulation time 161196368590 ps
CPU time 208.8 seconds
Started Aug 23 04:43:15 AM UTC 24
Finished Aug 23 04:46:47 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486420366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.3486420366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.796396811
Short name T422
Test name
Test status
Simulation time 208129994809 ps
CPU time 25.56 seconds
Started Aug 23 04:44:30 AM UTC 24
Finished Aug 23 04:44:57 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796396811 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.796396811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.321299740
Short name T94
Test name
Test status
Simulation time 125804067773 ps
CPU time 531.93 seconds
Started Aug 23 04:44:58 AM UTC 24
Finished Aug 23 04:53:54 AM UTC 24
Peak memory 212776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321299740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.321299740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.407283377
Short name T426
Test name
Test status
Simulation time 30095666538 ps
CPU time 17.37 seconds
Started Aug 23 04:44:52 AM UTC 24
Finished Aug 23 04:45:10 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407283377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.407283377
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.3049926730
Short name T421
Test name
Test status
Simulation time 4518786067 ps
CPU time 1.73 seconds
Started Aug 23 04:44:49 AM UTC 24
Finished Aug 23 04:44:51 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049926730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3049926730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2652388622
Short name T418
Test name
Test status
Simulation time 5857857601 ps
CPU time 11.74 seconds
Started Aug 23 04:43:04 AM UTC 24
Finished Aug 23 04:43:17 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652388622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2652388622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.4110537932
Short name T465
Test name
Test status
Simulation time 327860989566 ps
CPU time 739.56 seconds
Started Aug 23 04:45:01 AM UTC 24
Finished Aug 23 04:57:28 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110537932 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.4110537932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4248635550
Short name T256
Test name
Test status
Simulation time 7378614125 ps
CPU time 16.35 seconds
Started Aug 23 04:45:00 AM UTC 24
Finished Aug 23 04:45:17 AM UTC 24
Peak memory 222224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4248635550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.adc_ctrl_stress_all_with_rand_reset.4248635550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1567137080
Short name T432
Test name
Test status
Simulation time 469179260 ps
CPU time 0.92 seconds
Started Aug 23 04:47:16 AM UTC 24
Finished Aug 23 04:47:18 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567137080 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1567137080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.872713054
Short name T241
Test name
Test status
Simulation time 361869749268 ps
CPU time 749.67 seconds
Started Aug 23 04:46:47 AM UTC 24
Finished Aug 23 04:59:25 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872713054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.872713054
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3163908998
Short name T314
Test name
Test status
Simulation time 165157666116 ps
CPU time 30.61 seconds
Started Aug 23 04:45:26 AM UTC 24
Finished Aug 23 04:45:58 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163908998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3163908998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.746808105
Short name T434
Test name
Test status
Simulation time 156500786367 ps
CPU time 152.76 seconds
Started Aug 23 04:45:34 AM UTC 24
Finished Aug 23 04:48:09 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746808105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.746808105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1510762029
Short name T464
Test name
Test status
Simulation time 327730113649 ps
CPU time 702.47 seconds
Started Aug 23 04:45:11 AM UTC 24
Finished Aug 23 04:57:02 AM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510762029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1510762029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.942586742
Short name T436
Test name
Test status
Simulation time 491781375607 ps
CPU time 248.82 seconds
Started Aug 23 04:45:18 AM UTC 24
Finished Aug 23 04:49:30 AM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942586742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.942586742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.2582982841
Short name T318
Test name
Test status
Simulation time 373085186986 ps
CPU time 768.85 seconds
Started Aug 23 04:45:47 AM UTC 24
Finished Aug 23 04:58:44 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582982841 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.2582982841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3868446825
Short name T514
Test name
Test status
Simulation time 591832132452 ps
CPU time 1288.96 seconds
Started Aug 23 04:45:59 AM UTC 24
Finished Aug 23 05:07:41 AM UTC 24
Peak memory 212732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868446825 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.3868446825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.453955195
Short name T447
Test name
Test status
Simulation time 119538392532 ps
CPU time 413.65 seconds
Started Aug 23 04:47:00 AM UTC 24
Finished Aug 23 04:53:57 AM UTC 24
Peak memory 212028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453955195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.453955195
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.1139771642
Short name T435
Test name
Test status
Simulation time 38106614284 ps
CPU time 87.09 seconds
Started Aug 23 04:46:58 AM UTC 24
Finished Aug 23 04:48:26 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139771642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1139771642
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.1357162973
Short name T430
Test name
Test status
Simulation time 4213742709 ps
CPU time 2.87 seconds
Started Aug 23 04:46:54 AM UTC 24
Finished Aug 23 04:46:58 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357162973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1357162973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.3034932448
Short name T427
Test name
Test status
Simulation time 5879563905 ps
CPU time 13.57 seconds
Started Aug 23 04:45:11 AM UTC 24
Finished Aug 23 04:45:26 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034932448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3034932448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.543199801
Short name T23
Test name
Test status
Simulation time 3882944744 ps
CPU time 10.05 seconds
Started Aug 23 04:47:04 AM UTC 24
Finished Aug 23 04:47:15 AM UTC 24
Peak memory 221700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=543199801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
16.adc_ctrl_stress_all_with_rand_reset.543199801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.1677150260
Short name T440
Test name
Test status
Simulation time 352914146 ps
CPU time 1.22 seconds
Started Aug 23 04:50:10 AM UTC 24
Finished Aug 23 04:50:12 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677150260 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1677150260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.1053879036
Short name T283
Test name
Test status
Simulation time 162030269460 ps
CPU time 89.02 seconds
Started Aug 23 04:49:30 AM UTC 24
Finished Aug 23 04:51:01 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053879036 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.1053879036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.623631506
Short name T88
Test name
Test status
Simulation time 329490255013 ps
CPU time 172.29 seconds
Started Aug 23 04:49:31 AM UTC 24
Finished Aug 23 04:52:26 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623631506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.623631506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.2002773540
Short name T321
Test name
Test status
Simulation time 162151105372 ps
CPU time 184.72 seconds
Started Aug 23 04:47:35 AM UTC 24
Finished Aug 23 04:50:42 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002773540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2002773540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1184734002
Short name T478
Test name
Test status
Simulation time 336584315350 ps
CPU time 667.17 seconds
Started Aug 23 04:48:08 AM UTC 24
Finished Aug 23 04:59:22 AM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184734002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.1184734002
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.133991344
Short name T198
Test name
Test status
Simulation time 498245875609 ps
CPU time 281.05 seconds
Started Aug 23 04:47:19 AM UTC 24
Finished Aug 23 04:52:03 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133991344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.133991344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1312879978
Short name T457
Test name
Test status
Simulation time 494765903518 ps
CPU time 533.25 seconds
Started Aug 23 04:47:23 AM UTC 24
Finished Aug 23 04:56:21 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312879978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.1312879978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3211698944
Short name T219
Test name
Test status
Simulation time 564171792395 ps
CPU time 111.21 seconds
Started Aug 23 04:48:10 AM UTC 24
Finished Aug 23 04:50:03 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211698944 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.3211698944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4004334547
Short name T477
Test name
Test status
Simulation time 609241698135 ps
CPU time 640.8 seconds
Started Aug 23 04:48:27 AM UTC 24
Finished Aug 23 04:59:15 AM UTC 24
Peak memory 212540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004334547 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.4004334547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.2450793944
Short name T455
Test name
Test status
Simulation time 103553886442 ps
CPU time 339.41 seconds
Started Aug 23 04:50:04 AM UTC 24
Finished Aug 23 04:55:46 AM UTC 24
Peak memory 211836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450793944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2450793944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1308391700
Short name T445
Test name
Test status
Simulation time 45528659238 ps
CPU time 102.04 seconds
Started Aug 23 04:50:02 AM UTC 24
Finished Aug 23 04:51:46 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308391700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1308391700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3359248657
Short name T437
Test name
Test status
Simulation time 4563469411 ps
CPU time 10.15 seconds
Started Aug 23 04:49:55 AM UTC 24
Finished Aug 23 04:50:07 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359248657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3359248657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.1701901740
Short name T433
Test name
Test status
Simulation time 5861745735 ps
CPU time 4.03 seconds
Started Aug 23 04:47:17 AM UTC 24
Finished Aug 23 04:47:22 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701901740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1701901740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.4103637870
Short name T443
Test name
Test status
Simulation time 11840344555 ps
CPU time 14.52 seconds
Started Aug 23 04:50:08 AM UTC 24
Finished Aug 23 04:50:23 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103637870 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.4103637870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.977994017
Short name T24
Test name
Test status
Simulation time 3970108164 ps
CPU time 4.23 seconds
Started Aug 23 04:50:08 AM UTC 24
Finished Aug 23 04:50:13 AM UTC 24
Peak memory 221676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=977994017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
17.adc_ctrl_stress_all_with_rand_reset.977994017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3789012241
Short name T86
Test name
Test status
Simulation time 279997297 ps
CPU time 1.11 seconds
Started Aug 23 04:52:07 AM UTC 24
Finished Aug 23 04:52:09 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789012241 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3789012241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.1560749665
Short name T91
Test name
Test status
Simulation time 161301200803 ps
CPU time 85.91 seconds
Started Aug 23 04:51:31 AM UTC 24
Finished Aug 23 04:52:59 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560749665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1560749665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2582412465
Short name T453
Test name
Test status
Simulation time 158264700420 ps
CPU time 318.13 seconds
Started Aug 23 04:50:21 AM UTC 24
Finished Aug 23 04:55:43 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582412465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.2582412465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.3386384060
Short name T456
Test name
Test status
Simulation time 327810422266 ps
CPU time 356.92 seconds
Started Aug 23 04:50:13 AM UTC 24
Finished Aug 23 04:56:14 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386384060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3386384060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.76605895
Short name T484
Test name
Test status
Simulation time 491653589248 ps
CPU time 618.96 seconds
Started Aug 23 04:50:14 AM UTC 24
Finished Aug 23 05:00:39 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76605895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.76605895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1760121737
Short name T452
Test name
Test status
Simulation time 207302475661 ps
CPU time 240.9 seconds
Started Aug 23 04:50:43 AM UTC 24
Finished Aug 23 04:54:47 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760121737 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.1760121737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.126557126
Short name T216
Test name
Test status
Simulation time 100066700067 ps
CPU time 521.93 seconds
Started Aug 23 04:51:47 AM UTC 24
Finished Aug 23 05:00:33 AM UTC 24
Peak memory 211824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126557126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.126557126
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.333643191
Short name T89
Test name
Test status
Simulation time 26877320363 ps
CPU time 61.01 seconds
Started Aug 23 04:51:40 AM UTC 24
Finished Aug 23 04:52:43 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333643191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.333643191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.718781442
Short name T444
Test name
Test status
Simulation time 4665533885 ps
CPU time 3.3 seconds
Started Aug 23 04:51:35 AM UTC 24
Finished Aug 23 04:51:40 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718781442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.718781442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2120082355
Short name T442
Test name
Test status
Simulation time 5614619600 ps
CPU time 6.95 seconds
Started Aug 23 04:50:12 AM UTC 24
Finished Aug 23 04:50:20 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120082355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2120082355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.3638452811
Short name T93
Test name
Test status
Simulation time 173606188491 ps
CPU time 96.12 seconds
Started Aug 23 04:52:04 AM UTC 24
Finished Aug 23 04:53:42 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638452811 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.3638452811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.1067104003
Short name T450
Test name
Test status
Simulation time 473488799 ps
CPU time 1.07 seconds
Started Aug 23 04:54:34 AM UTC 24
Finished Aug 23 04:54:36 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067104003 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1067104003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.215878450
Short name T280
Test name
Test status
Simulation time 534484869436 ps
CPU time 392.71 seconds
Started Aug 23 04:53:55 AM UTC 24
Finished Aug 23 05:00:32 AM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215878450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.215878450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.3654047298
Short name T302
Test name
Test status
Simulation time 173940938925 ps
CPU time 72.73 seconds
Started Aug 23 04:52:44 AM UTC 24
Finished Aug 23 04:53:58 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654047298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3654047298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.259401688
Short name T454
Test name
Test status
Simulation time 327247472732 ps
CPU time 175.85 seconds
Started Aug 23 04:52:45 AM UTC 24
Finished Aug 23 04:55:43 AM UTC 24
Peak memory 211792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259401688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.259401688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.4264644636
Short name T529
Test name
Test status
Simulation time 492730127714 ps
CPU time 1083.15 seconds
Started Aug 23 04:52:26 AM UTC 24
Finished Aug 23 05:10:41 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264644636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.4264644636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.2946046756
Short name T467
Test name
Test status
Simulation time 162485945463 ps
CPU time 338.15 seconds
Started Aug 23 04:52:27 AM UTC 24
Finished Aug 23 04:58:09 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946046756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.2946046756
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2448623938
Short name T252
Test name
Test status
Simulation time 550902864783 ps
CPU time 324.27 seconds
Started Aug 23 04:53:00 AM UTC 24
Finished Aug 23 04:58:28 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448623938 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.2448623938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.224598711
Short name T471
Test name
Test status
Simulation time 400486557184 ps
CPU time 299.78 seconds
Started Aug 23 04:53:26 AM UTC 24
Finished Aug 23 04:58:30 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224598711 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.224598711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.4033939676
Short name T476
Test name
Test status
Simulation time 75403630271 ps
CPU time 294.26 seconds
Started Aug 23 04:54:03 AM UTC 24
Finished Aug 23 04:59:00 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033939676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4033939676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.786847791
Short name T449
Test name
Test status
Simulation time 39444330610 ps
CPU time 32.31 seconds
Started Aug 23 04:53:59 AM UTC 24
Finished Aug 23 04:54:33 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786847791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.786847791
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.2116876488
Short name T448
Test name
Test status
Simulation time 4015583303 ps
CPU time 2.85 seconds
Started Aug 23 04:53:58 AM UTC 24
Finished Aug 23 04:54:02 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116876488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2116876488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.4195706926
Short name T87
Test name
Test status
Simulation time 5680451088 ps
CPU time 14.27 seconds
Started Aug 23 04:52:10 AM UTC 24
Finished Aug 23 04:52:25 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195706926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4195706926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1355511445
Short name T26
Test name
Test status
Simulation time 1165023799 ps
CPU time 6.32 seconds
Started Aug 23 04:54:05 AM UTC 24
Finished Aug 23 04:54:12 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1355511445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.adc_ctrl_stress_all_with_rand_reset.1355511445
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.1554775068
Short name T68
Test name
Test status
Simulation time 462076512 ps
CPU time 0.81 seconds
Started Aug 23 04:17:13 AM UTC 24
Finished Aug 23 04:17:15 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554775068 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1554775068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2609036962
Short name T82
Test name
Test status
Simulation time 163286208119 ps
CPU time 178.59 seconds
Started Aug 23 04:16:12 AM UTC 24
Finished Aug 23 04:19:13 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609036962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2609036962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3876673453
Short name T83
Test name
Test status
Simulation time 167074880316 ps
CPU time 180.83 seconds
Started Aug 23 04:16:13 AM UTC 24
Finished Aug 23 04:19:16 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876673453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.3876673453
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.698997148
Short name T17
Test name
Test status
Simulation time 166227230811 ps
CPU time 91.31 seconds
Started Aug 23 04:16:04 AM UTC 24
Finished Aug 23 04:17:37 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698997148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.698997148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3208775323
Short name T363
Test name
Test status
Simulation time 166131417359 ps
CPU time 362.64 seconds
Started Aug 23 04:16:12 AM UTC 24
Finished Aug 23 04:22:18 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208775323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.3208775323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2967034854
Short name T222
Test name
Test status
Simulation time 342388588608 ps
CPU time 681.48 seconds
Started Aug 23 04:16:24 AM UTC 24
Finished Aug 23 04:27:53 AM UTC 24
Peak memory 212572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967034854 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.2967034854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3726057246
Short name T131
Test name
Test status
Simulation time 608802371188 ps
CPU time 299.01 seconds
Started Aug 23 04:16:24 AM UTC 24
Finished Aug 23 04:21:27 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726057246 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.3726057246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.1986097650
Short name T47
Test name
Test status
Simulation time 77470544628 ps
CPU time 416.08 seconds
Started Aug 23 04:16:56 AM UTC 24
Finished Aug 23 04:23:56 AM UTC 24
Peak memory 211836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986097650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1986097650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.483111153
Short name T149
Test name
Test status
Simulation time 38341649261 ps
CPU time 85.02 seconds
Started Aug 23 04:16:51 AM UTC 24
Finished Aug 23 04:18:17 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483111153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.483111153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1919735157
Short name T30
Test name
Test status
Simulation time 5057280409 ps
CPU time 3.5 seconds
Started Aug 23 04:16:46 AM UTC 24
Finished Aug 23 04:16:50 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919735157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1919735157
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1297095781
Short name T67
Test name
Test status
Simulation time 8204950363 ps
CPU time 17.79 seconds
Started Aug 23 04:17:08 AM UTC 24
Finished Aug 23 04:17:27 AM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297095781 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1297095781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.4088259483
Short name T9
Test name
Test status
Simulation time 5603279498 ps
CPU time 6.87 seconds
Started Aug 23 04:16:03 AM UTC 24
Finished Aug 23 04:16:11 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088259483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4088259483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.1678062977
Short name T205
Test name
Test status
Simulation time 283255574747 ps
CPU time 805.68 seconds
Started Aug 23 04:17:02 AM UTC 24
Finished Aug 23 04:30:35 AM UTC 24
Peak memory 223088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678062977 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.1678062977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1614507651
Short name T33
Test name
Test status
Simulation time 1590142388 ps
CPU time 4.05 seconds
Started Aug 23 04:16:56 AM UTC 24
Finished Aug 23 04:17:01 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1614507651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.adc_ctrl_stress_all_with_rand_reset.1614507651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.4219148358
Short name T462
Test name
Test status
Simulation time 347508510 ps
CPU time 0.7 seconds
Started Aug 23 04:56:36 AM UTC 24
Finished Aug 23 04:56:37 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219148358 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.4219148358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.1890609358
Short name T538
Test name
Test status
Simulation time 498009766290 ps
CPU time 1083.84 seconds
Started Aug 23 04:55:43 AM UTC 24
Finished Aug 23 05:13:57 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890609358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1890609358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2622015939
Short name T485
Test name
Test status
Simulation time 159259690834 ps
CPU time 308.77 seconds
Started Aug 23 04:55:43 AM UTC 24
Finished Aug 23 05:00:56 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622015939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.2622015939
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.2646914286
Short name T339
Test name
Test status
Simulation time 496070943372 ps
CPU time 525.41 seconds
Started Aug 23 04:54:41 AM UTC 24
Finished Aug 23 05:03:33 AM UTC 24
Peak memory 212568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646914286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2646914286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.2794159510
Short name T458
Test name
Test status
Simulation time 166677044890 ps
CPU time 93.39 seconds
Started Aug 23 04:54:48 AM UTC 24
Finished Aug 23 04:56:23 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794159510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.2794159510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.1090927928
Short name T326
Test name
Test status
Simulation time 360811437702 ps
CPU time 229.19 seconds
Started Aug 23 04:55:44 AM UTC 24
Finished Aug 23 04:59:36 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090927928 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.1090927928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.721955765
Short name T472
Test name
Test status
Simulation time 386145726254 ps
CPU time 164.08 seconds
Started Aug 23 04:55:47 AM UTC 24
Finished Aug 23 04:58:34 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721955765 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.721955765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.510234106
Short name T499
Test name
Test status
Simulation time 94864939605 ps
CPU time 471.13 seconds
Started Aug 23 04:56:23 AM UTC 24
Finished Aug 23 05:04:19 AM UTC 24
Peak memory 212084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510234106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.510234106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.1006177133
Short name T466
Test name
Test status
Simulation time 37822703364 ps
CPU time 76.08 seconds
Started Aug 23 04:56:22 AM UTC 24
Finished Aug 23 04:57:40 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006177133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1006177133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.769937080
Short name T459
Test name
Test status
Simulation time 4808278480 ps
CPU time 9.98 seconds
Started Aug 23 04:56:14 AM UTC 24
Finished Aug 23 04:56:25 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769937080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.769937080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.1717982357
Short name T451
Test name
Test status
Simulation time 5985701003 ps
CPU time 1.93 seconds
Started Aug 23 04:54:37 AM UTC 24
Finished Aug 23 04:54:40 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717982357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1717982357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.3688479631
Short name T353
Test name
Test status
Simulation time 278569029466 ps
CPU time 453.7 seconds
Started Aug 23 04:56:26 AM UTC 24
Finished Aug 23 05:04:05 AM UTC 24
Peak memory 222000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688479631 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.3688479631
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2309080108
Short name T461
Test name
Test status
Simulation time 5050280818 ps
CPU time 6.52 seconds
Started Aug 23 04:56:26 AM UTC 24
Finished Aug 23 04:56:34 AM UTC 24
Peak memory 221752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2309080108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.adc_ctrl_stress_all_with_rand_reset.2309080108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.2077327230
Short name T473
Test name
Test status
Simulation time 379374475 ps
CPU time 0.88 seconds
Started Aug 23 04:58:35 AM UTC 24
Finished Aug 23 04:58:37 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077327230 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2077327230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.1245873561
Short name T229
Test name
Test status
Simulation time 413093792370 ps
CPU time 65.57 seconds
Started Aug 23 04:57:41 AM UTC 24
Finished Aug 23 04:58:48 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245873561 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.1245873561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.4286312769
Short name T155
Test name
Test status
Simulation time 345253254244 ps
CPU time 766.33 seconds
Started Aug 23 04:58:10 AM UTC 24
Finished Aug 23 05:11:04 AM UTC 24
Peak memory 212592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286312769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4286312769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.2995136781
Short name T154
Test name
Test status
Simulation time 499159481348 ps
CPU time 132.99 seconds
Started Aug 23 04:57:03 AM UTC 24
Finished Aug 23 04:59:18 AM UTC 24
Peak memory 211568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995136781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2995136781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.249765383
Short name T496
Test name
Test status
Simulation time 167445170550 ps
CPU time 386.53 seconds
Started Aug 23 04:57:26 AM UTC 24
Finished Aug 23 05:03:57 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249765383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.249765383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.644660053
Short name T468
Test name
Test status
Simulation time 162167224828 ps
CPU time 81.17 seconds
Started Aug 23 04:56:49 AM UTC 24
Finished Aug 23 04:58:12 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644660053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.644660053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.724350717
Short name T505
Test name
Test status
Simulation time 492036771836 ps
CPU time 497.43 seconds
Started Aug 23 04:56:57 AM UTC 24
Finished Aug 23 05:05:20 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724350717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.724350717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.998773912
Short name T329
Test name
Test status
Simulation time 362965779409 ps
CPU time 736.39 seconds
Started Aug 23 04:57:29 AM UTC 24
Finished Aug 23 05:09:53 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998773912 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.998773912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.780522953
Short name T486
Test name
Test status
Simulation time 404754006432 ps
CPU time 197.05 seconds
Started Aug 23 04:57:37 AM UTC 24
Finished Aug 23 05:00:57 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780522953 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.780522953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.2146977193
Short name T523
Test name
Test status
Simulation time 121992649323 ps
CPU time 651.84 seconds
Started Aug 23 04:58:28 AM UTC 24
Finished Aug 23 05:09:27 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146977193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2146977193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.2925088636
Short name T470
Test name
Test status
Simulation time 22634072187 ps
CPU time 8.95 seconds
Started Aug 23 04:58:19 AM UTC 24
Finished Aug 23 04:58:29 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925088636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2925088636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.3602960368
Short name T469
Test name
Test status
Simulation time 3274448875 ps
CPU time 4.26 seconds
Started Aug 23 04:58:12 AM UTC 24
Finished Aug 23 04:58:18 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602960368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3602960368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.2708483437
Short name T463
Test name
Test status
Simulation time 5727091055 ps
CPU time 7.71 seconds
Started Aug 23 04:56:39 AM UTC 24
Finished Aug 23 04:56:48 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708483437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2708483437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.2773420380
Short name T502
Test name
Test status
Simulation time 112403107559 ps
CPU time 384.06 seconds
Started Aug 23 04:58:31 AM UTC 24
Finished Aug 23 05:04:59 AM UTC 24
Peak memory 212072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773420380 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.2773420380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2260500037
Short name T27
Test name
Test status
Simulation time 22428704363 ps
CPU time 26.23 seconds
Started Aug 23 04:58:30 AM UTC 24
Finished Aug 23 04:58:58 AM UTC 24
Peak memory 222004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2260500037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.adc_ctrl_stress_all_with_rand_reset.2260500037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.4259769549
Short name T481
Test name
Test status
Simulation time 475322637 ps
CPU time 0.76 seconds
Started Aug 23 04:59:50 AM UTC 24
Finished Aug 23 04:59:53 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259769549 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4259769549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.1124252225
Short name T245
Test name
Test status
Simulation time 331616483379 ps
CPU time 154.42 seconds
Started Aug 23 04:59:15 AM UTC 24
Finished Aug 23 05:01:52 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124252225 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.1124252225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.2170519481
Short name T500
Test name
Test status
Simulation time 163803979258 ps
CPU time 333.12 seconds
Started Aug 23 04:58:49 AM UTC 24
Finished Aug 23 05:04:26 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170519481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2170519481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2493257853
Short name T489
Test name
Test status
Simulation time 323782065934 ps
CPU time 160.68 seconds
Started Aug 23 04:58:59 AM UTC 24
Finished Aug 23 05:01:42 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493257853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.2493257853
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.1687449024
Short name T187
Test name
Test status
Simulation time 491751777014 ps
CPU time 274.83 seconds
Started Aug 23 04:58:45 AM UTC 24
Finished Aug 23 05:03:23 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687449024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1687449024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.1911438664
Short name T483
Test name
Test status
Simulation time 161139842538 ps
CPU time 85.28 seconds
Started Aug 23 04:58:47 AM UTC 24
Finished Aug 23 05:00:14 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911438664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.1911438664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.3104731498
Short name T270
Test name
Test status
Simulation time 169475276750 ps
CPU time 95.46 seconds
Started Aug 23 04:59:00 AM UTC 24
Finished Aug 23 05:00:37 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104731498 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.3104731498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3157558447
Short name T535
Test name
Test status
Simulation time 417997914061 ps
CPU time 836.94 seconds
Started Aug 23 04:59:04 AM UTC 24
Finished Aug 23 05:13:09 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157558447 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.3157558447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.951700046
Short name T517
Test name
Test status
Simulation time 114164267766 ps
CPU time 554.96 seconds
Started Aug 23 04:59:30 AM UTC 24
Finished Aug 23 05:08:51 AM UTC 24
Peak memory 211776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951700046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.951700046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.6482795
Short name T480
Test name
Test status
Simulation time 37550066943 ps
CPU time 17.85 seconds
Started Aug 23 04:59:25 AM UTC 24
Finished Aug 23 04:59:44 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6482795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_S
EQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.6482795
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.2825156297
Short name T479
Test name
Test status
Simulation time 3277833189 ps
CPU time 4.93 seconds
Started Aug 23 04:59:23 AM UTC 24
Finished Aug 23 04:59:29 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825156297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2825156297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.4226842960
Short name T474
Test name
Test status
Simulation time 5958896483 ps
CPU time 7.24 seconds
Started Aug 23 04:58:38 AM UTC 24
Finished Aug 23 04:58:46 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226842960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4226842960
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.2935367917
Short name T482
Test name
Test status
Simulation time 9829471655 ps
CPU time 11.87 seconds
Started Aug 23 04:59:45 AM UTC 24
Finished Aug 23 04:59:58 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935367917 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.2935367917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.487410000
Short name T289
Test name
Test status
Simulation time 117670025306 ps
CPU time 10.99 seconds
Started Aug 23 04:59:37 AM UTC 24
Finished Aug 23 04:59:49 AM UTC 24
Peak memory 221620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=487410000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
22.adc_ctrl_stress_all_with_rand_reset.487410000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.2140741593
Short name T490
Test name
Test status
Simulation time 353014228 ps
CPU time 0.88 seconds
Started Aug 23 05:01:43 AM UTC 24
Finished Aug 23 05:01:46 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140741593 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2140741593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.418188372
Short name T315
Test name
Test status
Simulation time 323679469030 ps
CPU time 394.86 seconds
Started Aug 23 05:00:56 AM UTC 24
Finished Aug 23 05:07:35 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418188372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.418188372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.3266576242
Short name T267
Test name
Test status
Simulation time 324500187307 ps
CPU time 177.14 seconds
Started Aug 23 05:00:15 AM UTC 24
Finished Aug 23 05:03:15 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266576242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3266576242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2805203111
Short name T562
Test name
Test status
Simulation time 495620588855 ps
CPU time 1067.88 seconds
Started Aug 23 05:00:33 AM UTC 24
Finished Aug 23 05:18:30 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805203111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.2805203111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.2010612660
Short name T97
Test name
Test status
Simulation time 326176170873 ps
CPU time 681.62 seconds
Started Aug 23 04:59:59 AM UTC 24
Finished Aug 23 05:11:27 AM UTC 24
Peak memory 212568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010612660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2010612660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.3658846482
Short name T488
Test name
Test status
Simulation time 168892375809 ps
CPU time 93.1 seconds
Started Aug 23 05:00:00 AM UTC 24
Finished Aug 23 05:01:35 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658846482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.3658846482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3857355159
Short name T581
Test name
Test status
Simulation time 611055598689 ps
CPU time 1318.39 seconds
Started Aug 23 05:00:38 AM UTC 24
Finished Aug 23 05:22:49 AM UTC 24
Peak memory 212540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857355159 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.3857355159
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.913413066
Short name T524
Test name
Test status
Simulation time 98298863013 ps
CPU time 506.34 seconds
Started Aug 23 05:01:09 AM UTC 24
Finished Aug 23 05:09:40 AM UTC 24
Peak memory 211836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913413066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.913413066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.919557304
Short name T493
Test name
Test status
Simulation time 39833417231 ps
CPU time 82.03 seconds
Started Aug 23 05:01:02 AM UTC 24
Finished Aug 23 05:02:26 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919557304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.919557304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.2983061390
Short name T487
Test name
Test status
Simulation time 4092916709 ps
CPU time 2.29 seconds
Started Aug 23 05:00:58 AM UTC 24
Finished Aug 23 05:01:01 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983061390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2983061390
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.3426565083
Short name T475
Test name
Test status
Simulation time 5687507655 ps
CPU time 2.9 seconds
Started Aug 23 04:59:54 AM UTC 24
Finished Aug 23 04:59:58 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426565083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3426565083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.316284855
Short name T491
Test name
Test status
Simulation time 5879032308 ps
CPU time 13.76 seconds
Started Aug 23 05:01:42 AM UTC 24
Finished Aug 23 05:01:58 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316284855 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.316284855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1388099677
Short name T28
Test name
Test status
Simulation time 2442082523 ps
CPU time 6.42 seconds
Started Aug 23 05:01:35 AM UTC 24
Finished Aug 23 05:01:43 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1388099677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.adc_ctrl_stress_all_with_rand_reset.1388099677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.2179219050
Short name T497
Test name
Test status
Simulation time 493394933 ps
CPU time 0.84 seconds
Started Aug 23 05:04:11 AM UTC 24
Finished Aug 23 05:04:13 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179219050 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2179219050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.1156662211
Short name T311
Test name
Test status
Simulation time 159566016063 ps
CPU time 91.01 seconds
Started Aug 23 05:01:59 AM UTC 24
Finished Aug 23 05:03:32 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156662211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1156662211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.839723562
Short name T494
Test name
Test status
Simulation time 168869878573 ps
CPU time 48.02 seconds
Started Aug 23 05:02:04 AM UTC 24
Finished Aug 23 05:02:53 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839723562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.839723562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.822822266
Short name T561
Test name
Test status
Simulation time 493378542116 ps
CPU time 983.81 seconds
Started Aug 23 05:01:53 AM UTC 24
Finished Aug 23 05:18:26 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822822266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.822822266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3252186069
Short name T512
Test name
Test status
Simulation time 413639755085 ps
CPU time 249.41 seconds
Started Aug 23 05:02:54 AM UTC 24
Finished Aug 23 05:07:06 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252186069 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.3252186069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.1213690972
Short name T522
Test name
Test status
Simulation time 64566017547 ps
CPU time 339.05 seconds
Started Aug 23 05:03:43 AM UTC 24
Finished Aug 23 05:09:26 AM UTC 24
Peak memory 211968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213690972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1213690972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.62807667
Short name T501
Test name
Test status
Simulation time 28972665092 ps
CPU time 62.88 seconds
Started Aug 23 05:03:33 AM UTC 24
Finished Aug 23 05:04:38 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62807667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.62807667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.653007397
Short name T495
Test name
Test status
Simulation time 3707399265 ps
CPU time 8.4 seconds
Started Aug 23 05:03:32 AM UTC 24
Finished Aug 23 05:03:42 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653007397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.653007397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.4069727308
Short name T492
Test name
Test status
Simulation time 5918345204 ps
CPU time 14.87 seconds
Started Aug 23 05:01:46 AM UTC 24
Finished Aug 23 05:02:03 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069727308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.4069727308
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.1488285753
Short name T504
Test name
Test status
Simulation time 174453603987 ps
CPU time 71.06 seconds
Started Aug 23 05:04:05 AM UTC 24
Finished Aug 23 05:05:18 AM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488285753 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.1488285753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3405141451
Short name T29
Test name
Test status
Simulation time 36286592412 ps
CPU time 12.38 seconds
Started Aug 23 05:03:57 AM UTC 24
Finished Aug 23 05:04:11 AM UTC 24
Peak memory 221964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3405141451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.adc_ctrl_stress_all_with_rand_reset.3405141451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.3418001340
Short name T509
Test name
Test status
Simulation time 373716604 ps
CPU time 0.59 seconds
Started Aug 23 05:06:13 AM UTC 24
Finished Aug 23 05:06:15 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418001340 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3418001340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.3206289178
Short name T341
Test name
Test status
Simulation time 322142340734 ps
CPU time 162.05 seconds
Started Aug 23 05:05:19 AM UTC 24
Finished Aug 23 05:08:03 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206289178 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.3206289178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.3653134252
Short name T199
Test name
Test status
Simulation time 487587088490 ps
CPU time 261.77 seconds
Started Aug 23 05:04:27 AM UTC 24
Finished Aug 23 05:08:52 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653134252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3653134252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1272124822
Short name T508
Test name
Test status
Simulation time 164127541646 ps
CPU time 92.54 seconds
Started Aug 23 05:04:39 AM UTC 24
Finished Aug 23 05:06:13 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272124822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.1272124822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.3985613726
Short name T254
Test name
Test status
Simulation time 501190994946 ps
CPU time 1179 seconds
Started Aug 23 05:04:20 AM UTC 24
Finished Aug 23 05:24:11 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985613726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3985613726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.913595403
Short name T503
Test name
Test status
Simulation time 326753562898 ps
CPU time 47.38 seconds
Started Aug 23 05:04:20 AM UTC 24
Finished Aug 23 05:05:08 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913595403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.913595403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.4105898667
Short name T513
Test name
Test status
Simulation time 190771943083 ps
CPU time 158.25 seconds
Started Aug 23 05:05:00 AM UTC 24
Finished Aug 23 05:07:40 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105898667 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.4105898667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.416997904
Short name T525
Test name
Test status
Simulation time 590830097564 ps
CPU time 299.08 seconds
Started Aug 23 05:05:09 AM UTC 24
Finished Aug 23 05:10:12 AM UTC 24
Peak memory 211652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416997904 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.416997904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.1517427876
Short name T102
Test name
Test status
Simulation time 69891074553 ps
CPU time 383.61 seconds
Started Aug 23 05:05:43 AM UTC 24
Finished Aug 23 05:12:11 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517427876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1517427876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.492276486
Short name T507
Test name
Test status
Simulation time 43875159078 ps
CPU time 5.27 seconds
Started Aug 23 05:05:42 AM UTC 24
Finished Aug 23 05:05:48 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492276486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.492276486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.4119211185
Short name T506
Test name
Test status
Simulation time 3085003731 ps
CPU time 2.29 seconds
Started Aug 23 05:05:39 AM UTC 24
Finished Aug 23 05:05:43 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119211185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4119211185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.4275062619
Short name T498
Test name
Test status
Simulation time 5755961546 ps
CPU time 4.32 seconds
Started Aug 23 05:04:13 AM UTC 24
Finished Aug 23 05:04:19 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275062619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.4275062619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.3346999514
Short name T567
Test name
Test status
Simulation time 340620599492 ps
CPU time 773.68 seconds
Started Aug 23 05:06:13 AM UTC 24
Finished Aug 23 05:19:15 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346999514 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.3346999514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.4077524668
Short name T511
Test name
Test status
Simulation time 63232388290 ps
CPU time 53.05 seconds
Started Aug 23 05:05:49 AM UTC 24
Finished Aug 23 05:06:43 AM UTC 24
Peak memory 222028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4077524668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.adc_ctrl_stress_all_with_rand_reset.4077524668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.4081538978
Short name T519
Test name
Test status
Simulation time 450198076 ps
CPU time 0.93 seconds
Started Aug 23 05:09:04 AM UTC 24
Finished Aug 23 05:09:06 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081538978 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4081538978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.3994246004
Short name T293
Test name
Test status
Simulation time 328793053476 ps
CPU time 305.99 seconds
Started Aug 23 05:07:42 AM UTC 24
Finished Aug 23 05:12:51 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994246004 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.3994246004
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.1306192504
Short name T98
Test name
Test status
Simulation time 172613849088 ps
CPU time 202.69 seconds
Started Aug 23 05:08:04 AM UTC 24
Finished Aug 23 05:11:29 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306192504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1306192504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.2897201773
Short name T325
Test name
Test status
Simulation time 167502012524 ps
CPU time 88.84 seconds
Started Aug 23 05:07:08 AM UTC 24
Finished Aug 23 05:08:38 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897201773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2897201773
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2075170941
Short name T101
Test name
Test status
Simulation time 160274321243 ps
CPU time 289.82 seconds
Started Aug 23 05:07:12 AM UTC 24
Finished Aug 23 05:12:05 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075170941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.2075170941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.4097594621
Short name T526
Test name
Test status
Simulation time 344444260387 ps
CPU time 224.74 seconds
Started Aug 23 05:06:31 AM UTC 24
Finished Aug 23 05:10:19 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097594621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4097594621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.2484758373
Short name T515
Test name
Test status
Simulation time 161491859849 ps
CPU time 79.42 seconds
Started Aug 23 05:06:45 AM UTC 24
Finished Aug 23 05:08:06 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484758373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.2484758373
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.1683784537
Short name T580
Test name
Test status
Simulation time 390398300626 ps
CPU time 840.45 seconds
Started Aug 23 05:07:36 AM UTC 24
Finished Aug 23 05:21:45 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683784537 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.1683784537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.4125664414
Short name T530
Test name
Test status
Simulation time 210164707270 ps
CPU time 207.17 seconds
Started Aug 23 05:07:41 AM UTC 24
Finished Aug 23 05:11:11 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125664414 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.4125664414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.819879684
Short name T217
Test name
Test status
Simulation time 104896488013 ps
CPU time 318.85 seconds
Started Aug 23 05:08:39 AM UTC 24
Finished Aug 23 05:14:01 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819879684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.819879684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.2012850850
Short name T521
Test name
Test status
Simulation time 35589169056 ps
CPU time 73.53 seconds
Started Aug 23 05:08:09 AM UTC 24
Finished Aug 23 05:09:24 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012850850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2012850850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.1623331818
Short name T516
Test name
Test status
Simulation time 4600528095 ps
CPU time 1.71 seconds
Started Aug 23 05:08:06 AM UTC 24
Finished Aug 23 05:08:09 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623331818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1623331818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.988160602
Short name T510
Test name
Test status
Simulation time 6125289096 ps
CPU time 14.46 seconds
Started Aug 23 05:06:15 AM UTC 24
Finished Aug 23 05:06:31 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988160602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.988160602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.3711438876
Short name T356
Test name
Test status
Simulation time 117081322966 ps
CPU time 439.69 seconds
Started Aug 23 05:08:52 AM UTC 24
Finished Aug 23 05:16:17 AM UTC 24
Peak memory 222076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711438876 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.3711438876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1484070097
Short name T518
Test name
Test status
Simulation time 4717682100 ps
CPU time 11.25 seconds
Started Aug 23 05:08:51 AM UTC 24
Finished Aug 23 05:09:04 AM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1484070097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.adc_ctrl_stress_all_with_rand_reset.1484070097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.3394826996
Short name T531
Test name
Test status
Simulation time 500548697 ps
CPU time 1.09 seconds
Started Aug 23 05:11:12 AM UTC 24
Finished Aug 23 05:11:14 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394826996 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3394826996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.3685971110
Short name T96
Test name
Test status
Simulation time 503424774495 ps
CPU time 72.88 seconds
Started Aug 23 05:10:12 AM UTC 24
Finished Aug 23 05:11:26 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685971110 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.3685971110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.4177937066
Short name T558
Test name
Test status
Simulation time 213031161553 ps
CPU time 438.97 seconds
Started Aug 23 05:10:20 AM UTC 24
Finished Aug 23 05:17:44 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177937066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4177937066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.3354205628
Short name T547
Test name
Test status
Simulation time 333335069374 ps
CPU time 354.22 seconds
Started Aug 23 05:09:26 AM UTC 24
Finished Aug 23 05:15:25 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354205628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3354205628
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1832844886
Short name T100
Test name
Test status
Simulation time 331258757426 ps
CPU time 134.54 seconds
Started Aug 23 05:09:28 AM UTC 24
Finished Aug 23 05:11:44 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832844886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.1832844886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.954379241
Short name T543
Test name
Test status
Simulation time 325735401181 ps
CPU time 348.47 seconds
Started Aug 23 05:09:12 AM UTC 24
Finished Aug 23 05:15:05 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954379241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.954379241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.1244531260
Short name T527
Test name
Test status
Simulation time 165023030653 ps
CPU time 54.93 seconds
Started Aug 23 05:09:24 AM UTC 24
Finished Aug 23 05:10:21 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244531260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.1244531260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.9131060
Short name T174
Test name
Test status
Simulation time 549937687252 ps
CPU time 88.94 seconds
Started Aug 23 05:09:41 AM UTC 24
Finished Aug 23 05:11:11 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9131060 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.9131060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1300083695
Short name T588
Test name
Test status
Simulation time 431524852765 ps
CPU time 874.67 seconds
Started Aug 23 05:09:54 AM UTC 24
Finished Aug 23 05:24:37 AM UTC 24
Peak memory 212464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300083695 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.1300083695
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.3131489149
Short name T214
Test name
Test status
Simulation time 69816645794 ps
CPU time 275.65 seconds
Started Aug 23 05:10:42 AM UTC 24
Finished Aug 23 05:15:22 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131489149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3131489149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.2134007657
Short name T99
Test name
Test status
Simulation time 34210961328 ps
CPU time 71.34 seconds
Started Aug 23 05:10:27 AM UTC 24
Finished Aug 23 05:11:40 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134007657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2134007657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.1047417944
Short name T528
Test name
Test status
Simulation time 3936915205 ps
CPU time 2.71 seconds
Started Aug 23 05:10:22 AM UTC 24
Finished Aug 23 05:10:26 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047417944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1047417944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.4126831145
Short name T520
Test name
Test status
Simulation time 5873526680 ps
CPU time 2.87 seconds
Started Aug 23 05:09:07 AM UTC 24
Finished Aug 23 05:09:12 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126831145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4126831145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.23910630
Short name T559
Test name
Test status
Simulation time 80586616179 ps
CPU time 411.27 seconds
Started Aug 23 05:11:11 AM UTC 24
Finished Aug 23 05:18:07 AM UTC 24
Peak memory 221828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23910630 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.23910630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2381434503
Short name T85
Test name
Test status
Simulation time 163613222357 ps
CPU time 19.7 seconds
Started Aug 23 05:11:05 AM UTC 24
Finished Aug 23 05:11:26 AM UTC 24
Peak memory 221624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2381434503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.adc_ctrl_stress_all_with_rand_reset.2381434503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.1513397464
Short name T534
Test name
Test status
Simulation time 428769588 ps
CPU time 1 seconds
Started Aug 23 05:12:52 AM UTC 24
Finished Aug 23 05:12:54 AM UTC 24
Peak memory 209512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513397464 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1513397464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.1050161634
Short name T261
Test name
Test status
Simulation time 485036183994 ps
CPU time 379.2 seconds
Started Aug 23 05:11:45 AM UTC 24
Finished Aug 23 05:18:08 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050161634 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.1050161634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.2995019443
Short name T537
Test name
Test status
Simulation time 166413184090 ps
CPU time 96.1 seconds
Started Aug 23 05:12:06 AM UTC 24
Finished Aug 23 05:13:44 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995019443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2995019443
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.3123151412
Short name T548
Test name
Test status
Simulation time 159118327348 ps
CPU time 237.6 seconds
Started Aug 23 05:11:27 AM UTC 24
Finished Aug 23 05:15:27 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123151412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3123151412
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1781487706
Short name T578
Test name
Test status
Simulation time 496765973820 ps
CPU time 568.38 seconds
Started Aug 23 05:11:28 AM UTC 24
Finished Aug 23 05:21:02 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781487706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.1781487706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.2214117821
Short name T612
Test name
Test status
Simulation time 496600766594 ps
CPU time 1079.75 seconds
Started Aug 23 05:11:21 AM UTC 24
Finished Aug 23 05:29:31 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214117821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2214117821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.1506933069
Short name T103
Test name
Test status
Simulation time 342927167603 ps
CPU time 48.09 seconds
Started Aug 23 05:11:27 AM UTC 24
Finished Aug 23 05:12:16 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506933069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.1506933069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1221036716
Short name T568
Test name
Test status
Simulation time 198658241136 ps
CPU time 453.8 seconds
Started Aug 23 05:11:41 AM UTC 24
Finished Aug 23 05:19:19 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221036716 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.1221036716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.2758215364
Short name T557
Test name
Test status
Simulation time 78070615403 ps
CPU time 307.3 seconds
Started Aug 23 05:12:18 AM UTC 24
Finished Aug 23 05:17:29 AM UTC 24
Peak memory 211892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758215364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2758215364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.2984071318
Short name T533
Test name
Test status
Simulation time 41700875850 ps
CPU time 22.69 seconds
Started Aug 23 05:12:17 AM UTC 24
Finished Aug 23 05:12:41 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984071318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2984071318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.4004488699
Short name T104
Test name
Test status
Simulation time 3735701220 ps
CPU time 4.6 seconds
Started Aug 23 05:12:12 AM UTC 24
Finished Aug 23 05:12:18 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004488699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4004488699
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.1638743058
Short name T532
Test name
Test status
Simulation time 5759158688 ps
CPU time 3.91 seconds
Started Aug 23 05:11:15 AM UTC 24
Finished Aug 23 05:11:20 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638743058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1638743058
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.209777956
Short name T310
Test name
Test status
Simulation time 17378422718 ps
CPU time 11.87 seconds
Started Aug 23 05:12:42 AM UTC 24
Finished Aug 23 05:12:56 AM UTC 24
Peak memory 221948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=209777956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
28.adc_ctrl_stress_all_with_rand_reset.209777956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.199710301
Short name T545
Test name
Test status
Simulation time 301437105 ps
CPU time 0.7 seconds
Started Aug 23 05:15:07 AM UTC 24
Finished Aug 23 05:15:09 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199710301 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.199710301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.2977322412
Short name T539
Test name
Test status
Simulation time 165529556504 ps
CPU time 11.09 seconds
Started Aug 23 05:14:02 AM UTC 24
Finished Aug 23 05:14:14 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977322412 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.2977322412
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.1966066526
Short name T312
Test name
Test status
Simulation time 521659060407 ps
CPU time 568.82 seconds
Started Aug 23 05:14:15 AM UTC 24
Finished Aug 23 05:23:50 AM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966066526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1966066526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.3821005040
Short name T541
Test name
Test status
Simulation time 167312618257 ps
CPU time 101.45 seconds
Started Aug 23 05:13:12 AM UTC 24
Finished Aug 23 05:14:55 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821005040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3821005040
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2171572340
Short name T551
Test name
Test status
Simulation time 161330143863 ps
CPU time 177.69 seconds
Started Aug 23 05:13:21 AM UTC 24
Finished Aug 23 05:16:21 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171572340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.2171572340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.3840592227
Short name T157
Test name
Test status
Simulation time 331340832433 ps
CPU time 97.25 seconds
Started Aug 23 05:12:56 AM UTC 24
Finished Aug 23 05:14:35 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840592227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3840592227
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.2946538264
Short name T550
Test name
Test status
Simulation time 487969366502 ps
CPU time 166.65 seconds
Started Aug 23 05:13:09 AM UTC 24
Finished Aug 23 05:15:58 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946538264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.2946538264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.2167243492
Short name T549
Test name
Test status
Simulation time 545337587937 ps
CPU time 115.22 seconds
Started Aug 23 05:13:45 AM UTC 24
Finished Aug 23 05:15:42 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167243492 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.2167243492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2956937857
Short name T644
Test name
Test status
Simulation time 593729692362 ps
CPU time 1264.47 seconds
Started Aug 23 05:13:58 AM UTC 24
Finished Aug 23 05:35:13 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956937857 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.2956937857
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.3536393935
Short name T575
Test name
Test status
Simulation time 114382961513 ps
CPU time 350.23 seconds
Started Aug 23 05:14:55 AM UTC 24
Finished Aug 23 05:20:49 AM UTC 24
Peak memory 212028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536393935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3536393935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.1711722462
Short name T542
Test name
Test status
Simulation time 29534841372 ps
CPU time 15.71 seconds
Started Aug 23 05:14:43 AM UTC 24
Finished Aug 23 05:15:00 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711722462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1711722462
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.3219734498
Short name T540
Test name
Test status
Simulation time 4843842830 ps
CPU time 5.56 seconds
Started Aug 23 05:14:36 AM UTC 24
Finished Aug 23 05:14:43 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219734498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3219734498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.23425716
Short name T536
Test name
Test status
Simulation time 6209427255 ps
CPU time 14.17 seconds
Started Aug 23 05:12:55 AM UTC 24
Finished Aug 23 05:13:11 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23425716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.23425716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.2529862892
Short name T343
Test name
Test status
Simulation time 355184037330 ps
CPU time 67.04 seconds
Started Aug 23 05:15:05 AM UTC 24
Finished Aug 23 05:16:14 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529862892 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.2529862892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2202545964
Short name T544
Test name
Test status
Simulation time 20606469629 ps
CPU time 5.79 seconds
Started Aug 23 05:15:00 AM UTC 24
Finished Aug 23 05:15:07 AM UTC 24
Peak memory 221820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2202545964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.adc_ctrl_stress_all_with_rand_reset.2202545964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2405664704
Short name T79
Test name
Test status
Simulation time 481799195 ps
CPU time 1.56 seconds
Started Aug 23 04:18:42 AM UTC 24
Finished Aug 23 04:18:45 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405664704 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2405664704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.179496905
Short name T137
Test name
Test status
Simulation time 165633665122 ps
CPU time 338.94 seconds
Started Aug 23 04:17:42 AM UTC 24
Finished Aug 23 04:23:24 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179496905 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.179496905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1544939036
Short name T129
Test name
Test status
Simulation time 184176184317 ps
CPU time 398.73 seconds
Started Aug 23 04:17:47 AM UTC 24
Finished Aug 23 04:24:30 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544939036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1544939036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3024282153
Short name T136
Test name
Test status
Simulation time 331878982687 ps
CPU time 340.83 seconds
Started Aug 23 04:17:30 AM UTC 24
Finished Aug 23 04:23:14 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024282153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3024282153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3163230483
Short name T150
Test name
Test status
Simulation time 491271597944 ps
CPU time 192.02 seconds
Started Aug 23 04:17:33 AM UTC 24
Finished Aug 23 04:20:47 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163230483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.3163230483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.2660793292
Short name T200
Test name
Test status
Simulation time 163718672290 ps
CPU time 169.61 seconds
Started Aug 23 04:17:20 AM UTC 24
Finished Aug 23 04:20:12 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660793292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2660793292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.289345394
Short name T152
Test name
Test status
Simulation time 325570186187 ps
CPU time 133.17 seconds
Started Aug 23 04:17:27 AM UTC 24
Finished Aug 23 04:19:42 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289345394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.289345394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.3700998844
Short name T42
Test name
Test status
Simulation time 362474218006 ps
CPU time 64.52 seconds
Started Aug 23 04:17:35 AM UTC 24
Finished Aug 23 04:18:41 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700998844 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.3700998844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.572442528
Short name T367
Test name
Test status
Simulation time 585749401860 ps
CPU time 379.93 seconds
Started Aug 23 04:17:38 AM UTC 24
Finished Aug 23 04:24:02 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572442528 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.572442528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.1730853198
Short name T81
Test name
Test status
Simulation time 31613399853 ps
CPU time 68.48 seconds
Started Aug 23 04:17:58 AM UTC 24
Finished Aug 23 04:19:08 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730853198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1730853198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2745798515
Short name T106
Test name
Test status
Simulation time 2875106571 ps
CPU time 3.99 seconds
Started Aug 23 04:17:52 AM UTC 24
Finished Aug 23 04:17:57 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745798515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2745798515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.2048154416
Short name T77
Test name
Test status
Simulation time 8295051317 ps
CPU time 8.92 seconds
Started Aug 23 04:18:40 AM UTC 24
Finished Aug 23 04:18:50 AM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048154416 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2048154416
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.347642060
Short name T105
Test name
Test status
Simulation time 5639243856 ps
CPU time 2.44 seconds
Started Aug 23 04:17:16 AM UTC 24
Finished Aug 23 04:17:19 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347642060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.347642060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.1260995094
Short name T555
Test name
Test status
Simulation time 498250451 ps
CPU time 1.59 seconds
Started Aug 23 05:17:06 AM UTC 24
Finished Aug 23 05:17:09 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260995094 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1260995094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.837436666
Short name T158
Test name
Test status
Simulation time 178106490005 ps
CPU time 198.3 seconds
Started Aug 23 05:15:59 AM UTC 24
Finished Aug 23 05:19:20 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837436666 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.837436666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.566223033
Short name T262
Test name
Test status
Simulation time 514843921640 ps
CPU time 99.85 seconds
Started Aug 23 05:16:15 AM UTC 24
Finished Aug 23 05:17:57 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566223033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.566223033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.1377045865
Short name T333
Test name
Test status
Simulation time 327291323975 ps
CPU time 689.49 seconds
Started Aug 23 05:15:26 AM UTC 24
Finished Aug 23 05:27:02 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377045865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1377045865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4186021493
Short name T599
Test name
Test status
Simulation time 323199415919 ps
CPU time 694.89 seconds
Started Aug 23 05:15:28 AM UTC 24
Finished Aug 23 05:27:10 AM UTC 24
Peak memory 212540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186021493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.4186021493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.713576650
Short name T601
Test name
Test status
Simulation time 326626734066 ps
CPU time 718.71 seconds
Started Aug 23 05:15:13 AM UTC 24
Finished Aug 23 05:27:19 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713576650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.713576650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.1512887020
Short name T572
Test name
Test status
Simulation time 159141037293 ps
CPU time 300.85 seconds
Started Aug 23 05:15:23 AM UTC 24
Finished Aug 23 05:20:27 AM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512887020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.1512887020
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.78172605
Short name T659
Test name
Test status
Simulation time 615925038742 ps
CPU time 1297.95 seconds
Started Aug 23 05:15:43 AM UTC 24
Finished Aug 23 05:37:33 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78172605 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.78172605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.836017268
Short name T609
Test name
Test status
Simulation time 384165238074 ps
CPU time 793.74 seconds
Started Aug 23 05:15:55 AM UTC 24
Finished Aug 23 05:29:16 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836017268 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.836017268
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.4180494713
Short name T206
Test name
Test status
Simulation time 114076652673 ps
CPU time 506.5 seconds
Started Aug 23 05:16:27 AM UTC 24
Finished Aug 23 05:24:59 AM UTC 24
Peak memory 212028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180494713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.4180494713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.3368353598
Short name T554
Test name
Test status
Simulation time 40122065114 ps
CPU time 45.03 seconds
Started Aug 23 05:16:22 AM UTC 24
Finished Aug 23 05:17:09 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368353598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3368353598
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.3681566404
Short name T552
Test name
Test status
Simulation time 3760088557 ps
CPU time 8.64 seconds
Started Aug 23 05:16:17 AM UTC 24
Finished Aug 23 05:16:27 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681566404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3681566404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.2166538888
Short name T546
Test name
Test status
Simulation time 6149913062 ps
CPU time 1.38 seconds
Started Aug 23 05:15:10 AM UTC 24
Finished Aug 23 05:15:13 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166538888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2166538888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.2366093285
Short name T354
Test name
Test status
Simulation time 597635860430 ps
CPU time 546.67 seconds
Started Aug 23 05:17:06 AM UTC 24
Finished Aug 23 05:26:18 AM UTC 24
Peak memory 223836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366093285 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.2366093285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2331365968
Short name T553
Test name
Test status
Simulation time 10732153480 ps
CPU time 6.68 seconds
Started Aug 23 05:16:58 AM UTC 24
Finished Aug 23 05:17:06 AM UTC 24
Peak memory 221632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2331365968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.adc_ctrl_stress_all_with_rand_reset.2331365968
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.3467605641
Short name T565
Test name
Test status
Simulation time 371788474 ps
CPU time 0.95 seconds
Started Aug 23 05:18:46 AM UTC 24
Finished Aug 23 05:18:48 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467605641 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3467605641
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.712490798
Short name T290
Test name
Test status
Simulation time 200961379263 ps
CPU time 39.72 seconds
Started Aug 23 05:18:08 AM UTC 24
Finished Aug 23 05:18:49 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712490798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.712490798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.120157099
Short name T300
Test name
Test status
Simulation time 494869184162 ps
CPU time 216.73 seconds
Started Aug 23 05:17:30 AM UTC 24
Finished Aug 23 05:21:09 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120157099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.120157099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.280453829
Short name T583
Test name
Test status
Simulation time 324235724601 ps
CPU time 344.8 seconds
Started Aug 23 05:17:42 AM UTC 24
Finished Aug 23 05:23:31 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280453829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.280453829
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.2340793924
Short name T637
Test name
Test status
Simulation time 485873155746 ps
CPU time 997.4 seconds
Started Aug 23 05:17:17 AM UTC 24
Finished Aug 23 05:34:05 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340793924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.2340793924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.2385725054
Short name T268
Test name
Test status
Simulation time 181069248834 ps
CPU time 409.54 seconds
Started Aug 23 05:17:45 AM UTC 24
Finished Aug 23 05:24:39 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385725054 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.2385725054
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2977606991
Short name T665
Test name
Test status
Simulation time 612796458109 ps
CPU time 1215.09 seconds
Started Aug 23 05:17:49 AM UTC 24
Finished Aug 23 05:38:15 AM UTC 24
Peak memory 212600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977606991 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.2977606991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.824957131
Short name T602
Test name
Test status
Simulation time 145821425269 ps
CPU time 589.35 seconds
Started Aug 23 05:18:26 AM UTC 24
Finished Aug 23 05:28:21 AM UTC 24
Peak memory 211968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824957131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.824957131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.3858673011
Short name T563
Test name
Test status
Simulation time 25859404588 ps
CPU time 14.46 seconds
Started Aug 23 05:18:15 AM UTC 24
Finished Aug 23 05:18:30 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858673011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3858673011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.3773026670
Short name T560
Test name
Test status
Simulation time 3421881250 ps
CPU time 4.16 seconds
Started Aug 23 05:18:09 AM UTC 24
Finished Aug 23 05:18:14 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773026670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3773026670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.462161560
Short name T556
Test name
Test status
Simulation time 5564300636 ps
CPU time 6.48 seconds
Started Aug 23 05:17:09 AM UTC 24
Finished Aug 23 05:17:17 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462161560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.462161560
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.3290228991
Short name T571
Test name
Test status
Simulation time 170793507993 ps
CPU time 99.93 seconds
Started Aug 23 05:18:31 AM UTC 24
Finished Aug 23 05:20:13 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290228991 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.3290228991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2285510446
Short name T564
Test name
Test status
Simulation time 2630097067 ps
CPU time 13.49 seconds
Started Aug 23 05:18:31 AM UTC 24
Finished Aug 23 05:18:46 AM UTC 24
Peak memory 221680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2285510446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.adc_ctrl_stress_all_with_rand_reset.2285510446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.827553336
Short name T577
Test name
Test status
Simulation time 296868564 ps
CPU time 0.82 seconds
Started Aug 23 05:20:54 AM UTC 24
Finished Aug 23 05:20:56 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827553336 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.827553336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.2025191083
Short name T263
Test name
Test status
Simulation time 194697877277 ps
CPU time 212.34 seconds
Started Aug 23 05:19:56 AM UTC 24
Finished Aug 23 05:23:31 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025191083 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.2025191083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.1108620886
Short name T631
Test name
Test status
Simulation time 342179980441 ps
CPU time 717.39 seconds
Started Aug 23 05:19:56 AM UTC 24
Finished Aug 23 05:32:00 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108620886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1108620886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1952261740
Short name T582
Test name
Test status
Simulation time 165334675976 ps
CPU time 216.42 seconds
Started Aug 23 05:19:21 AM UTC 24
Finished Aug 23 05:23:00 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952261740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.1952261740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.2630018499
Short name T570
Test name
Test status
Simulation time 325988482849 ps
CPU time 64.11 seconds
Started Aug 23 05:18:49 AM UTC 24
Finished Aug 23 05:19:55 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630018499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2630018499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.3031917503
Short name T569
Test name
Test status
Simulation time 162844564553 ps
CPU time 40.5 seconds
Started Aug 23 05:18:58 AM UTC 24
Finished Aug 23 05:19:40 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031917503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.3031917503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.907324953
Short name T593
Test name
Test status
Simulation time 355435488203 ps
CPU time 381.79 seconds
Started Aug 23 05:19:21 AM UTC 24
Finished Aug 23 05:25:47 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907324953 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.907324953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1012435938
Short name T604
Test name
Test status
Simulation time 606489995258 ps
CPU time 528.85 seconds
Started Aug 23 05:19:41 AM UTC 24
Finished Aug 23 05:28:35 AM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012435938 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.1012435938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.459988114
Short name T355
Test name
Test status
Simulation time 91610442684 ps
CPU time 470.46 seconds
Started Aug 23 05:20:28 AM UTC 24
Finished Aug 23 05:28:23 AM UTC 24
Peak memory 212084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459988114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.459988114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.3233444752
Short name T574
Test name
Test status
Simulation time 32200880678 ps
CPU time 9.7 seconds
Started Aug 23 05:20:28 AM UTC 24
Finished Aug 23 05:20:39 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233444752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3233444752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.1011235657
Short name T573
Test name
Test status
Simulation time 5114051880 ps
CPU time 12.15 seconds
Started Aug 23 05:20:14 AM UTC 24
Finished Aug 23 05:20:27 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011235657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1011235657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.87329494
Short name T566
Test name
Test status
Simulation time 5948455106 ps
CPU time 7.24 seconds
Started Aug 23 05:18:49 AM UTC 24
Finished Aug 23 05:18:58 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87329494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.87329494
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4108936665
Short name T576
Test name
Test status
Simulation time 13913700492 ps
CPU time 13.18 seconds
Started Aug 23 05:20:39 AM UTC 24
Finished Aug 23 05:20:53 AM UTC 24
Peak memory 222084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4108936665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.adc_ctrl_stress_all_with_rand_reset.4108936665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.1619318597
Short name T589
Test name
Test status
Simulation time 546509143 ps
CPU time 0.81 seconds
Started Aug 23 05:24:36 AM UTC 24
Finished Aug 23 05:24:37 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619318597 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1619318597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.3035159405
Short name T269
Test name
Test status
Simulation time 191235343130 ps
CPU time 192.59 seconds
Started Aug 23 05:23:31 AM UTC 24
Finished Aug 23 05:26:47 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035159405 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.3035159405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.353786522
Short name T592
Test name
Test status
Simulation time 163993474139 ps
CPU time 87.36 seconds
Started Aug 23 05:23:31 AM UTC 24
Finished Aug 23 05:25:01 AM UTC 24
Peak memory 211248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353786522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.353786522
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1831250544
Short name T614
Test name
Test status
Simulation time 485433293333 ps
CPU time 482.29 seconds
Started Aug 23 05:21:46 AM UTC 24
Finished Aug 23 05:29:53 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831250544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.1831250544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.146240765
Short name T591
Test name
Test status
Simulation time 492352173788 ps
CPU time 228.81 seconds
Started Aug 23 05:21:02 AM UTC 24
Finished Aug 23 05:24:54 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146240765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.146240765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.2541501856
Short name T587
Test name
Test status
Simulation time 341343050199 ps
CPU time 205.6 seconds
Started Aug 23 05:21:06 AM UTC 24
Finished Aug 23 05:24:35 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541501856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.2541501856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.1703843192
Short name T613
Test name
Test status
Simulation time 178152243903 ps
CPU time 401.91 seconds
Started Aug 23 05:22:50 AM UTC 24
Finished Aug 23 05:29:37 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703843192 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.1703843192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1855355192
Short name T620
Test name
Test status
Simulation time 201285305950 ps
CPU time 435.51 seconds
Started Aug 23 05:23:00 AM UTC 24
Finished Aug 23 05:30:20 AM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855355192 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.1855355192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.82462035
Short name T607
Test name
Test status
Simulation time 71813075757 ps
CPU time 286.51 seconds
Started Aug 23 05:24:11 AM UTC 24
Finished Aug 23 05:29:01 AM UTC 24
Peak memory 211816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82462035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.82462035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.2530247893
Short name T585
Test name
Test status
Simulation time 38147268778 ps
CPU time 18.46 seconds
Started Aug 23 05:23:55 AM UTC 24
Finished Aug 23 05:24:15 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530247893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2530247893
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.137603248
Short name T584
Test name
Test status
Simulation time 5238506699 ps
CPU time 3.62 seconds
Started Aug 23 05:23:50 AM UTC 24
Finished Aug 23 05:23:55 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137603248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.137603248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.1581496307
Short name T579
Test name
Test status
Simulation time 6029122364 ps
CPU time 8.83 seconds
Started Aug 23 05:20:56 AM UTC 24
Finished Aug 23 05:21:06 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581496307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1581496307
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.1944817287
Short name T595
Test name
Test status
Simulation time 335251695568 ps
CPU time 136.02 seconds
Started Aug 23 05:24:29 AM UTC 24
Finished Aug 23 05:26:47 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944817287 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.1944817287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1525515525
Short name T586
Test name
Test status
Simulation time 25361596715 ps
CPU time 11.51 seconds
Started Aug 23 05:24:15 AM UTC 24
Finished Aug 23 05:24:28 AM UTC 24
Peak memory 221936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1525515525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.adc_ctrl_stress_all_with_rand_reset.1525515525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.2306689518
Short name T596
Test name
Test status
Simulation time 535148628 ps
CPU time 0.87 seconds
Started Aug 23 05:26:55 AM UTC 24
Finished Aug 23 05:26:57 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306689518 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2306689518
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.3003556156
Short name T188
Test name
Test status
Simulation time 527385263095 ps
CPU time 109.97 seconds
Started Aug 23 05:25:47 AM UTC 24
Finished Aug 23 05:27:39 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003556156 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.3003556156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.2581179268
Short name T628
Test name
Test status
Simulation time 167615939855 ps
CPU time 385.79 seconds
Started Aug 23 05:24:46 AM UTC 24
Finished Aug 23 05:31:16 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581179268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2581179268
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3688824083
Short name T627
Test name
Test status
Simulation time 162416979356 ps
CPU time 350.83 seconds
Started Aug 23 05:24:55 AM UTC 24
Finished Aug 23 05:30:50 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688824083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.3688824083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.2606689950
Short name T677
Test name
Test status
Simulation time 488027568173 ps
CPU time 906.72 seconds
Started Aug 23 05:24:40 AM UTC 24
Finished Aug 23 05:39:55 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606689950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.2606689950
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.31251341
Short name T679
Test name
Test status
Simulation time 433783466832 ps
CPU time 894.64 seconds
Started Aug 23 05:24:59 AM UTC 24
Finished Aug 23 05:40:02 AM UTC 24
Peak memory 212820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31251341 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.31251341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2289728045
Short name T671
Test name
Test status
Simulation time 389827258803 ps
CPU time 815.42 seconds
Started Aug 23 05:25:01 AM UTC 24
Finished Aug 23 05:38:44 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289728045 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.2289728045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.3123330775
Short name T645
Test name
Test status
Simulation time 112646041406 ps
CPU time 517.87 seconds
Started Aug 23 05:26:31 AM UTC 24
Finished Aug 23 05:35:14 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123330775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3123330775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.3044759658
Short name T597
Test name
Test status
Simulation time 31577016814 ps
CPU time 31.66 seconds
Started Aug 23 05:26:25 AM UTC 24
Finished Aug 23 05:26:58 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044759658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3044759658
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.3018509579
Short name T594
Test name
Test status
Simulation time 4206687167 ps
CPU time 9.01 seconds
Started Aug 23 05:26:19 AM UTC 24
Finished Aug 23 05:26:29 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018509579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3018509579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.4292958209
Short name T590
Test name
Test status
Simulation time 5776561005 ps
CPU time 6.84 seconds
Started Aug 23 05:24:38 AM UTC 24
Finished Aug 23 05:24:46 AM UTC 24
Peak memory 210888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292958209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4292958209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.667937950
Short name T610
Test name
Test status
Simulation time 77389690508 ps
CPU time 147.49 seconds
Started Aug 23 05:26:48 AM UTC 24
Finished Aug 23 05:29:17 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667937950 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.667937950
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2090911714
Short name T598
Test name
Test status
Simulation time 9142351175 ps
CPU time 14.36 seconds
Started Aug 23 05:26:48 AM UTC 24
Finished Aug 23 05:27:03 AM UTC 24
Peak memory 221952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2090911714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.adc_ctrl_stress_all_with_rand_reset.2090911714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.4215629740
Short name T606
Test name
Test status
Simulation time 367304677 ps
CPU time 1.24 seconds
Started Aug 23 05:28:51 AM UTC 24
Finished Aug 23 05:28:53 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215629740 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.4215629740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.3513207689
Short name T624
Test name
Test status
Simulation time 162402314572 ps
CPU time 174.09 seconds
Started Aug 23 05:27:40 AM UTC 24
Finished Aug 23 05:30:37 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513207689 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.3513207689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.3059076693
Short name T616
Test name
Test status
Simulation time 328610655177 ps
CPU time 187.6 seconds
Started Aug 23 05:27:04 AM UTC 24
Finished Aug 23 05:30:14 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059076693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3059076693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1839597700
Short name T615
Test name
Test status
Simulation time 164476350914 ps
CPU time 174.21 seconds
Started Aug 23 05:27:11 AM UTC 24
Finished Aug 23 05:30:08 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839597700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.1839597700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.2158572918
Short name T669
Test name
Test status
Simulation time 330931882258 ps
CPU time 696.05 seconds
Started Aug 23 05:26:59 AM UTC 24
Finished Aug 23 05:38:43 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158572918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2158572918
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.1434051755
Short name T617
Test name
Test status
Simulation time 167281204472 ps
CPU time 190.07 seconds
Started Aug 23 05:27:03 AM UTC 24
Finished Aug 23 05:30:16 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434051755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.1434051755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.2442591023
Short name T630
Test name
Test status
Simulation time 530648220653 ps
CPU time 259.19 seconds
Started Aug 23 05:27:13 AM UTC 24
Finished Aug 23 05:31:36 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442591023 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.2442591023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3400501049
Short name T626
Test name
Test status
Simulation time 595438488844 ps
CPU time 197.94 seconds
Started Aug 23 05:27:19 AM UTC 24
Finished Aug 23 05:30:40 AM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400501049 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.3400501049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.50232599
Short name T651
Test name
Test status
Simulation time 136758056337 ps
CPU time 453.11 seconds
Started Aug 23 05:28:36 AM UTC 24
Finished Aug 23 05:36:13 AM UTC 24
Peak memory 212832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50232599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.50232599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.1918652107
Short name T605
Test name
Test status
Simulation time 41556432293 ps
CPU time 25.05 seconds
Started Aug 23 05:28:23 AM UTC 24
Finished Aug 23 05:28:50 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918652107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1918652107
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.607993191
Short name T603
Test name
Test status
Simulation time 5141924949 ps
CPU time 12.17 seconds
Started Aug 23 05:28:21 AM UTC 24
Finished Aug 23 05:28:35 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607993191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.607993191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.3509918873
Short name T600
Test name
Test status
Simulation time 5670542121 ps
CPU time 13.19 seconds
Started Aug 23 05:26:58 AM UTC 24
Finished Aug 23 05:27:12 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509918873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3509918873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.2272492125
Short name T639
Test name
Test status
Simulation time 511414997854 ps
CPU time 333.17 seconds
Started Aug 23 05:28:43 AM UTC 24
Finished Aug 23 05:34:20 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272492125 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.2272492125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2618237296
Short name T611
Test name
Test status
Simulation time 93872884237 ps
CPU time 46.82 seconds
Started Aug 23 05:28:36 AM UTC 24
Finished Aug 23 05:29:24 AM UTC 24
Peak memory 222164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2618237296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.adc_ctrl_stress_all_with_rand_reset.2618237296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.2804526829
Short name T621
Test name
Test status
Simulation time 431764181 ps
CPU time 0.73 seconds
Started Aug 23 05:30:21 AM UTC 24
Finished Aug 23 05:30:22 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804526829 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2804526829
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.724885283
Short name T692
Test name
Test status
Simulation time 514936029050 ps
CPU time 732.2 seconds
Started Aug 23 05:29:37 AM UTC 24
Finished Aug 23 05:41:57 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724885283 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.724885283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.2172845127
Short name T335
Test name
Test status
Simulation time 332110535299 ps
CPU time 193.15 seconds
Started Aug 23 05:29:17 AM UTC 24
Finished Aug 23 05:32:33 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172845127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2172845127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2660475673
Short name T636
Test name
Test status
Simulation time 322828862146 ps
CPU time 198.31 seconds
Started Aug 23 05:29:18 AM UTC 24
Finished Aug 23 05:32:39 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660475673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.2660475673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.3382018924
Short name T711
Test name
Test status
Simulation time 491814209255 ps
CPU time 1013.72 seconds
Started Aug 23 05:29:02 AM UTC 24
Finished Aug 23 05:46:06 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382018924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3382018924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.2145778673
Short name T618
Test name
Test status
Simulation time 160847903845 ps
CPU time 65.14 seconds
Started Aug 23 05:29:10 AM UTC 24
Finished Aug 23 05:30:17 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145778673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.2145778673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.2126461486
Short name T250
Test name
Test status
Simulation time 347040126937 ps
CPU time 188.79 seconds
Started Aug 23 05:29:24 AM UTC 24
Finished Aug 23 05:32:36 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126461486 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.2126461486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.86256640
Short name T657
Test name
Test status
Simulation time 403483396763 ps
CPU time 463.27 seconds
Started Aug 23 05:29:32 AM UTC 24
Finished Aug 23 05:37:20 AM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86256640 -assert nopostpro
c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.86256640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.4180979873
Short name T622
Test name
Test status
Simulation time 45069204207 ps
CPU time 6.03 seconds
Started Aug 23 05:30:15 AM UTC 24
Finished Aug 23 05:30:22 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180979873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.4180979873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.104693618
Short name T619
Test name
Test status
Simulation time 3416286222 ps
CPU time 7.82 seconds
Started Aug 23 05:30:08 AM UTC 24
Finished Aug 23 05:30:17 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104693618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.104693618
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.1622677904
Short name T608
Test name
Test status
Simulation time 5877186412 ps
CPU time 14.13 seconds
Started Aug 23 05:28:54 AM UTC 24
Finished Aug 23 05:29:09 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622677904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1622677904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.3193361485
Short name T650
Test name
Test status
Simulation time 169528696146 ps
CPU time 344.69 seconds
Started Aug 23 05:30:18 AM UTC 24
Finished Aug 23 05:36:06 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193361485 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.3193361485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2752141301
Short name T625
Test name
Test status
Simulation time 8647177792 ps
CPU time 5.59 seconds
Started Aug 23 05:30:18 AM UTC 24
Finished Aug 23 05:30:24 AM UTC 24
Peak memory 211884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2752141301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.adc_ctrl_stress_all_with_rand_reset.2752141301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.3957330793
Short name T634
Test name
Test status
Simulation time 365485280 ps
CPU time 0.73 seconds
Started Aug 23 05:32:27 AM UTC 24
Finished Aug 23 05:32:29 AM UTC 24
Peak memory 207948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957330793 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3957330793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.3395487667
Short name T648
Test name
Test status
Simulation time 525136671338 ps
CPU time 298.62 seconds
Started Aug 23 05:30:51 AM UTC 24
Finished Aug 23 05:35:53 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395487667 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.3395487667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1466587942
Short name T652
Test name
Test status
Simulation time 168444492106 ps
CPU time 332.9 seconds
Started Aug 23 05:30:37 AM UTC 24
Finished Aug 23 05:36:14 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466587942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.1466587942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.1218246051
Short name T722
Test name
Test status
Simulation time 490875013240 ps
CPU time 1048.28 seconds
Started Aug 23 05:30:23 AM UTC 24
Finished Aug 23 05:48:01 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218246051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1218246051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.2151544186
Short name T723
Test name
Test status
Simulation time 487254846043 ps
CPU time 1081.08 seconds
Started Aug 23 05:30:23 AM UTC 24
Finished Aug 23 05:48:35 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151544186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.2151544186
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.330084216
Short name T632
Test name
Test status
Simulation time 200444294317 ps
CPU time 96.45 seconds
Started Aug 23 05:30:41 AM UTC 24
Finished Aug 23 05:32:20 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330084216 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.330084216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.1345268812
Short name T658
Test name
Test status
Simulation time 62306039079 ps
CPU time 346.09 seconds
Started Aug 23 05:31:36 AM UTC 24
Finished Aug 23 05:37:26 AM UTC 24
Peak memory 211776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345268812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1345268812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.347725997
Short name T633
Test name
Test status
Simulation time 25870039887 ps
CPU time 53.98 seconds
Started Aug 23 05:31:30 AM UTC 24
Finished Aug 23 05:32:26 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347725997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.347725997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.2531311242
Short name T629
Test name
Test status
Simulation time 5184353873 ps
CPU time 7.49 seconds
Started Aug 23 05:31:21 AM UTC 24
Finished Aug 23 05:31:30 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531311242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2531311242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.190964342
Short name T623
Test name
Test status
Simulation time 5714963923 ps
CPU time 13.51 seconds
Started Aug 23 05:30:22 AM UTC 24
Finished Aug 23 05:30:36 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190964342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.190964342
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.3079630950
Short name T332
Test name
Test status
Simulation time 537827132196 ps
CPU time 123.15 seconds
Started Aug 23 05:32:21 AM UTC 24
Finished Aug 23 05:34:26 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079630950 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.3079630950
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1145772271
Short name T328
Test name
Test status
Simulation time 167181766496 ps
CPU time 23.1 seconds
Started Aug 23 05:32:01 AM UTC 24
Finished Aug 23 05:32:26 AM UTC 24
Peak memory 212092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1145772271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.adc_ctrl_stress_all_with_rand_reset.1145772271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.4195877341
Short name T642
Test name
Test status
Simulation time 609009333 ps
CPU time 0.6 seconds
Started Aug 23 05:34:45 AM UTC 24
Finished Aug 23 05:34:46 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195877341 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4195877341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.1293430109
Short name T189
Test name
Test status
Simulation time 507885184352 ps
CPU time 224.29 seconds
Started Aug 23 05:33:28 AM UTC 24
Finished Aug 23 05:37:16 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293430109 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.1293430109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.767735136
Short name T738
Test name
Test status
Simulation time 510805347767 ps
CPU time 989.93 seconds
Started Aug 23 05:34:05 AM UTC 24
Finished Aug 23 05:50:45 AM UTC 24
Peak memory 212684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767735136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.767735136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.2890710859
Short name T649
Test name
Test status
Simulation time 333196115437 ps
CPU time 201.78 seconds
Started Aug 23 05:32:35 AM UTC 24
Finished Aug 23 05:35:59 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890710859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2890710859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2250530925
Short name T647
Test name
Test status
Simulation time 172732563376 ps
CPU time 189.68 seconds
Started Aug 23 05:32:36 AM UTC 24
Finished Aug 23 05:35:48 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250530925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.2250530925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.4013426477
Short name T287
Test name
Test status
Simulation time 491649386968 ps
CPU time 1101.5 seconds
Started Aug 23 05:32:30 AM UTC 24
Finished Aug 23 05:51:02 AM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013426477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4013426477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.3069710315
Short name T646
Test name
Test status
Simulation time 327285577589 ps
CPU time 180.91 seconds
Started Aug 23 05:32:34 AM UTC 24
Finished Aug 23 05:35:37 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069710315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.3069710315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.654276786
Short name T638
Test name
Test status
Simulation time 182396989458 ps
CPU time 97.22 seconds
Started Aug 23 05:32:40 AM UTC 24
Finished Aug 23 05:34:19 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654276786 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.654276786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.631592451
Short name T681
Test name
Test status
Simulation time 208230580092 ps
CPU time 431.98 seconds
Started Aug 23 05:33:22 AM UTC 24
Finished Aug 23 05:40:39 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631592451 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.631592451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.995323269
Short name T688
Test name
Test status
Simulation time 114891628072 ps
CPU time 412.79 seconds
Started Aug 23 05:34:23 AM UTC 24
Finished Aug 23 05:41:21 AM UTC 24
Peak memory 211968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995323269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.995323269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.3667582539
Short name T641
Test name
Test status
Simulation time 39206882420 ps
CPU time 21.02 seconds
Started Aug 23 05:34:21 AM UTC 24
Finished Aug 23 05:34:44 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667582539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3667582539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.826387030
Short name T640
Test name
Test status
Simulation time 4427443860 ps
CPU time 2.42 seconds
Started Aug 23 05:34:19 AM UTC 24
Finished Aug 23 05:34:23 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826387030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.826387030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.957854176
Short name T635
Test name
Test status
Simulation time 6028238595 ps
CPU time 5.98 seconds
Started Aug 23 05:32:27 AM UTC 24
Finished Aug 23 05:32:34 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957854176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.957854176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.2676155641
Short name T724
Test name
Test status
Simulation time 268692442789 ps
CPU time 833.63 seconds
Started Aug 23 05:34:39 AM UTC 24
Finished Aug 23 05:48:40 AM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676155641 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.2676155641
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2514390700
Short name T317
Test name
Test status
Simulation time 12559621954 ps
CPU time 9.86 seconds
Started Aug 23 05:34:26 AM UTC 24
Finished Aug 23 05:34:38 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2514390700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.adc_ctrl_stress_all_with_rand_reset.2514390700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.3765792886
Short name T656
Test name
Test status
Simulation time 423972080 ps
CPU time 0.91 seconds
Started Aug 23 05:37:17 AM UTC 24
Finished Aug 23 05:37:19 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765792886 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3765792886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.2060224825
Short name T664
Test name
Test status
Simulation time 384318200589 ps
CPU time 129.86 seconds
Started Aug 23 05:36:00 AM UTC 24
Finished Aug 23 05:38:12 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060224825 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.2060224825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.2807328642
Short name T661
Test name
Test status
Simulation time 159192360648 ps
CPU time 90.68 seconds
Started Aug 23 05:36:07 AM UTC 24
Finished Aug 23 05:37:40 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807328642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2807328642
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.1397332062
Short name T675
Test name
Test status
Simulation time 163676945578 ps
CPU time 227.64 seconds
Started Aug 23 05:35:15 AM UTC 24
Finished Aug 23 05:39:05 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397332062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1397332062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2466677878
Short name T755
Test name
Test status
Simulation time 487969401912 ps
CPU time 1079.26 seconds
Started Aug 23 05:35:38 AM UTC 24
Finished Aug 23 05:53:48 AM UTC 24
Peak memory 212540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466677878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.2466677878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.2060148674
Short name T662
Test name
Test status
Simulation time 164470746096 ps
CPU time 167.09 seconds
Started Aug 23 05:34:54 AM UTC 24
Finished Aug 23 05:37:43 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060148674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2060148674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.1707874796
Short name T654
Test name
Test status
Simulation time 488993827765 ps
CPU time 81.73 seconds
Started Aug 23 05:35:14 AM UTC 24
Finished Aug 23 05:36:37 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707874796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.1707874796
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.1974997669
Short name T694
Test name
Test status
Simulation time 177955832058 ps
CPU time 374.54 seconds
Started Aug 23 05:35:49 AM UTC 24
Finished Aug 23 05:42:08 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974997669 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.1974997669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2617645258
Short name T678
Test name
Test status
Simulation time 396460860667 ps
CPU time 239.24 seconds
Started Aug 23 05:35:54 AM UTC 24
Finished Aug 23 05:39:56 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617645258 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.2617645258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.952348862
Short name T663
Test name
Test status
Simulation time 45919777023 ps
CPU time 99.99 seconds
Started Aug 23 05:36:14 AM UTC 24
Finished Aug 23 05:37:56 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952348862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.952348862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.4133451529
Short name T653
Test name
Test status
Simulation time 4968965869 ps
CPU time 3.24 seconds
Started Aug 23 05:36:14 AM UTC 24
Finished Aug 23 05:36:19 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133451529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4133451529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.2318879816
Short name T643
Test name
Test status
Simulation time 5786213625 ps
CPU time 5.57 seconds
Started Aug 23 05:34:47 AM UTC 24
Finished Aug 23 05:34:53 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318879816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2318879816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.201189594
Short name T655
Test name
Test status
Simulation time 2331492098 ps
CPU time 8.39 seconds
Started Aug 23 05:36:38 AM UTC 24
Finished Aug 23 05:36:47 AM UTC 24
Peak memory 222272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=201189594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
39.adc_ctrl_stress_all_with_rand_reset.201189594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1339545724
Short name T359
Test name
Test status
Simulation time 540701207 ps
CPU time 0.63 seconds
Started Aug 23 04:20:48 AM UTC 24
Finished Aug 23 04:20:49 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339545724 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1339545724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.984179818
Short name T132
Test name
Test status
Simulation time 341734773911 ps
CPU time 127.96 seconds
Started Aug 23 04:19:43 AM UTC 24
Finished Aug 23 04:21:53 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984179818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.984179818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.1503043053
Short name T135
Test name
Test status
Simulation time 161722804419 ps
CPU time 189.14 seconds
Started Aug 23 04:19:09 AM UTC 24
Finished Aug 23 04:22:21 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503043053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1503043053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.529958140
Short name T202
Test name
Test status
Simulation time 165078777086 ps
CPU time 95.88 seconds
Started Aug 23 04:19:13 AM UTC 24
Finished Aug 23 04:20:51 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529958140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.529958140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.1765443719
Short name T257
Test name
Test status
Simulation time 324665696302 ps
CPU time 579.39 seconds
Started Aug 23 04:18:51 AM UTC 24
Finished Aug 23 04:28:37 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765443719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1765443719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.2679895138
Short name T368
Test name
Test status
Simulation time 489572504397 ps
CPU time 313.69 seconds
Started Aug 23 04:19:03 AM UTC 24
Finished Aug 23 04:24:21 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679895138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.2679895138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3531286539
Short name T134
Test name
Test status
Simulation time 193849755668 ps
CPU time 407.47 seconds
Started Aug 23 04:19:17 AM UTC 24
Finished Aug 23 04:26:09 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531286539 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.3531286539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1751118476
Short name T171
Test name
Test status
Simulation time 196094108040 ps
CPU time 22.96 seconds
Started Aug 23 04:19:20 AM UTC 24
Finished Aug 23 04:19:45 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751118476 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.1751118476
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1787422110
Short name T45
Test name
Test status
Simulation time 102328817023 ps
CPU time 528.39 seconds
Started Aug 23 04:20:13 AM UTC 24
Finished Aug 23 04:29:06 AM UTC 24
Peak memory 212832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787422110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1787422110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2778517371
Short name T358
Test name
Test status
Simulation time 28041480229 ps
CPU time 54.62 seconds
Started Aug 23 04:19:50 AM UTC 24
Finished Aug 23 04:20:46 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778517371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2778517371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.2087781592
Short name T357
Test name
Test status
Simulation time 3658531507 ps
CPU time 2.34 seconds
Started Aug 23 04:19:45 AM UTC 24
Finished Aug 23 04:19:49 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087781592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2087781592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.1883390910
Short name T78
Test name
Test status
Simulation time 4089793213 ps
CPU time 9.11 seconds
Started Aug 23 04:20:48 AM UTC 24
Finished Aug 23 04:20:58 AM UTC 24
Peak memory 243484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883390910 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1883390910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.1027131417
Short name T80
Test name
Test status
Simulation time 5868083957 ps
CPU time 14.32 seconds
Started Aug 23 04:18:46 AM UTC 24
Finished Aug 23 04:19:02 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027131417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1027131417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.926050863
Short name T36
Test name
Test status
Simulation time 13878175271 ps
CPU time 42.91 seconds
Started Aug 23 04:20:15 AM UTC 24
Finished Aug 23 04:20:59 AM UTC 24
Peak memory 222212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=926050863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
4.adc_ctrl_stress_all_with_rand_reset.926050863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.2437347442
Short name T672
Test name
Test status
Simulation time 331307437 ps
CPU time 1.22 seconds
Started Aug 23 05:38:45 AM UTC 24
Finished Aug 23 05:38:47 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437347442 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2437347442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.1223310297
Short name T667
Test name
Test status
Simulation time 165439129784 ps
CPU time 31.57 seconds
Started Aug 23 05:37:57 AM UTC 24
Finished Aug 23 05:38:30 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223310297 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.1223310297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.3113246719
Short name T725
Test name
Test status
Simulation time 325550859242 ps
CPU time 662.51 seconds
Started Aug 23 05:37:34 AM UTC 24
Finished Aug 23 05:48:43 AM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113246719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3113246719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1070839988
Short name T682
Test name
Test status
Simulation time 330575291563 ps
CPU time 182.12 seconds
Started Aug 23 05:37:36 AM UTC 24
Finished Aug 23 05:40:41 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070839988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.1070839988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.3744770453
Short name T683
Test name
Test status
Simulation time 494046215558 ps
CPU time 201.56 seconds
Started Aug 23 05:37:21 AM UTC 24
Finished Aug 23 05:40:45 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744770453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3744770453
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.515150675
Short name T736
Test name
Test status
Simulation time 333288200698 ps
CPU time 763.35 seconds
Started Aug 23 05:37:27 AM UTC 24
Finished Aug 23 05:50:19 AM UTC 24
Peak memory 212676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515150675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.515150675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.2057006129
Short name T344
Test name
Test status
Simulation time 530175183996 ps
CPU time 1082.5 seconds
Started Aug 23 05:37:41 AM UTC 24
Finished Aug 23 05:55:54 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057006129 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.2057006129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3046192863
Short name T708
Test name
Test status
Simulation time 602109750633 ps
CPU time 483.12 seconds
Started Aug 23 05:37:44 AM UTC 24
Finished Aug 23 05:45:53 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046192863 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.3046192863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.3872913631
Short name T706
Test name
Test status
Simulation time 80189352472 ps
CPU time 418.38 seconds
Started Aug 23 05:38:31 AM UTC 24
Finished Aug 23 05:45:33 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872913631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3872913631
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.3787335504
Short name T668
Test name
Test status
Simulation time 24971710731 ps
CPU time 14.09 seconds
Started Aug 23 05:38:20 AM UTC 24
Finished Aug 23 05:38:36 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787335504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3787335504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.3808657988
Short name T666
Test name
Test status
Simulation time 3151224835 ps
CPU time 3.79 seconds
Started Aug 23 05:38:15 AM UTC 24
Finished Aug 23 05:38:20 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808657988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3808657988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.2534435724
Short name T660
Test name
Test status
Simulation time 5981980015 ps
CPU time 13.74 seconds
Started Aug 23 05:37:20 AM UTC 24
Finished Aug 23 05:37:35 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534435724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2534435724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.304318389
Short name T673
Test name
Test status
Simulation time 6564867071 ps
CPU time 4.05 seconds
Started Aug 23 05:38:44 AM UTC 24
Finished Aug 23 05:38:49 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304318389 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.304318389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.379826075
Short name T670
Test name
Test status
Simulation time 2224695727 ps
CPU time 6.36 seconds
Started Aug 23 05:38:37 AM UTC 24
Finished Aug 23 05:38:44 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=379826075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
40.adc_ctrl_stress_all_with_rand_reset.379826075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.49962795
Short name T685
Test name
Test status
Simulation time 450959883 ps
CPU time 1.6 seconds
Started Aug 23 05:40:46 AM UTC 24
Finished Aug 23 05:40:48 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49962795 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.49962795
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.3040723449
Short name T697
Test name
Test status
Simulation time 243184740458 ps
CPU time 139.77 seconds
Started Aug 23 05:39:57 AM UTC 24
Finished Aug 23 05:42:19 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040723449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3040723449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.485475555
Short name T170
Test name
Test status
Simulation time 325938388994 ps
CPU time 185.9 seconds
Started Aug 23 05:38:59 AM UTC 24
Finished Aug 23 05:42:07 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485475555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.485475555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3960414205
Short name T741
Test name
Test status
Simulation time 326243697702 ps
CPU time 707.28 seconds
Started Aug 23 05:39:06 AM UTC 24
Finished Aug 23 05:51:01 AM UTC 24
Peak memory 212676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960414205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.3960414205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.1558056098
Short name T691
Test name
Test status
Simulation time 327610334614 ps
CPU time 176.33 seconds
Started Aug 23 05:38:48 AM UTC 24
Finished Aug 23 05:41:47 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558056098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1558056098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.631244050
Short name T676
Test name
Test status
Simulation time 164069142415 ps
CPU time 53.51 seconds
Started Aug 23 05:38:50 AM UTC 24
Finished Aug 23 05:39:45 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631244050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.631244050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.2396706346
Short name T175
Test name
Test status
Simulation time 543579758649 ps
CPU time 322.59 seconds
Started Aug 23 05:39:38 AM UTC 24
Finished Aug 23 05:45:05 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396706346 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.2396706346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1490586662
Short name T689
Test name
Test status
Simulation time 200132378951 ps
CPU time 96.58 seconds
Started Aug 23 05:39:45 AM UTC 24
Finished Aug 23 05:41:24 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490586662 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.1490586662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.1033081789
Short name T737
Test name
Test status
Simulation time 128142921728 ps
CPU time 615.06 seconds
Started Aug 23 05:40:06 AM UTC 24
Finished Aug 23 05:50:26 AM UTC 24
Peak memory 212888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033081789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1033081789
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.1662572716
Short name T687
Test name
Test status
Simulation time 30378864160 ps
CPU time 61.7 seconds
Started Aug 23 05:40:02 AM UTC 24
Finished Aug 23 05:41:06 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662572716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1662572716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.2356836114
Short name T680
Test name
Test status
Simulation time 3139742772 ps
CPU time 2.27 seconds
Started Aug 23 05:40:01 AM UTC 24
Finished Aug 23 05:40:05 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356836114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2356836114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.3481603633
Short name T674
Test name
Test status
Simulation time 5714605438 ps
CPU time 12.14 seconds
Started Aug 23 05:38:45 AM UTC 24
Finished Aug 23 05:38:58 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481603633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3481603633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.1366848982
Short name T690
Test name
Test status
Simulation time 168574610920 ps
CPU time 46.56 seconds
Started Aug 23 05:40:42 AM UTC 24
Finished Aug 23 05:41:30 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366848982 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.1366848982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1918168293
Short name T684
Test name
Test status
Simulation time 6717020512 ps
CPU time 5.72 seconds
Started Aug 23 05:40:40 AM UTC 24
Finished Aug 23 05:40:46 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1918168293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.adc_ctrl_stress_all_with_rand_reset.1918168293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.1037601996
Short name T698
Test name
Test status
Simulation time 407645163 ps
CPU time 0.97 seconds
Started Aug 23 05:42:20 AM UTC 24
Finished Aug 23 05:42:22 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037601996 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1037601996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.839706183
Short name T323
Test name
Test status
Simulation time 523707456605 ps
CPU time 273.7 seconds
Started Aug 23 05:41:47 AM UTC 24
Finished Aug 23 05:46:24 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839706183 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.839706183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.4194541415
Short name T735
Test name
Test status
Simulation time 416768483615 ps
CPU time 471.16 seconds
Started Aug 23 05:41:57 AM UTC 24
Finished Aug 23 05:49:54 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194541415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.4194541415
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.3220506785
Short name T194
Test name
Test status
Simulation time 487323661987 ps
CPU time 284.15 seconds
Started Aug 23 05:41:06 AM UTC 24
Finished Aug 23 05:45:54 AM UTC 24
Peak memory 211668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220506785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3220506785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2739199731
Short name T701
Test name
Test status
Simulation time 164508256982 ps
CPU time 87.63 seconds
Started Aug 23 05:41:21 AM UTC 24
Finished Aug 23 05:42:51 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739199731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.2739199731
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.4268575143
Short name T704
Test name
Test status
Simulation time 487157383303 ps
CPU time 200.29 seconds
Started Aug 23 05:40:49 AM UTC 24
Finished Aug 23 05:44:12 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268575143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4268575143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.3263624290
Short name T703
Test name
Test status
Simulation time 325187974226 ps
CPU time 176.82 seconds
Started Aug 23 05:41:02 AM UTC 24
Finished Aug 23 05:44:01 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263624290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.3263624290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.884365379
Short name T265
Test name
Test status
Simulation time 568663090780 ps
CPU time 309.66 seconds
Started Aug 23 05:41:24 AM UTC 24
Finished Aug 23 05:46:38 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884365379 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.884365379
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2771096040
Short name T793
Test name
Test status
Simulation time 597000992065 ps
CPU time 1398.87 seconds
Started Aug 23 05:41:30 AM UTC 24
Finished Aug 23 06:05:02 AM UTC 24
Peak memory 212540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771096040 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.2771096040
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.1824004717
Short name T748
Test name
Test status
Simulation time 115478350947 ps
CPU time 601.23 seconds
Started Aug 23 05:42:09 AM UTC 24
Finished Aug 23 05:52:16 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824004717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1824004717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.3020740047
Short name T700
Test name
Test status
Simulation time 41877063253 ps
CPU time 25.47 seconds
Started Aug 23 05:42:09 AM UTC 24
Finished Aug 23 05:42:35 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020740047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3020740047
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.3182283109
Short name T695
Test name
Test status
Simulation time 3200424388 ps
CPU time 7.11 seconds
Started Aug 23 05:42:04 AM UTC 24
Finished Aug 23 05:42:12 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182283109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3182283109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.3278267032
Short name T686
Test name
Test status
Simulation time 5588908473 ps
CPU time 13.15 seconds
Started Aug 23 05:40:47 AM UTC 24
Finished Aug 23 05:41:01 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278267032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3278267032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.1996426357
Short name T702
Test name
Test status
Simulation time 31200875777 ps
CPU time 65.22 seconds
Started Aug 23 05:42:18 AM UTC 24
Finished Aug 23 05:43:25 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996426357 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.1996426357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2303385999
Short name T696
Test name
Test status
Simulation time 5224842162 ps
CPU time 3.71 seconds
Started Aug 23 05:42:13 AM UTC 24
Finished Aug 23 05:42:18 AM UTC 24
Peak memory 221896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2303385999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.adc_ctrl_stress_all_with_rand_reset.2303385999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.2448604330
Short name T709
Test name
Test status
Simulation time 535852504 ps
CPU time 1.03 seconds
Started Aug 23 05:45:53 AM UTC 24
Finished Aug 23 05:45:55 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448604330 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2448604330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.1472931949
Short name T727
Test name
Test status
Simulation time 168733259001 ps
CPU time 232.99 seconds
Started Aug 23 05:45:01 AM UTC 24
Finished Aug 23 05:48:57 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472931949 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.1472931949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.4204523350
Short name T714
Test name
Test status
Simulation time 335935630961 ps
CPU time 197.99 seconds
Started Aug 23 05:42:51 AM UTC 24
Finished Aug 23 05:46:12 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204523350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.4204523350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.884096417
Short name T715
Test name
Test status
Simulation time 165902134776 ps
CPU time 186.62 seconds
Started Aug 23 05:43:25 AM UTC 24
Finished Aug 23 05:46:35 AM UTC 24
Peak memory 211592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884096417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.884096417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.537686739
Short name T319
Test name
Test status
Simulation time 162052301372 ps
CPU time 312.36 seconds
Started Aug 23 05:42:32 AM UTC 24
Finished Aug 23 05:47:48 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537686739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.537686739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.2804307186
Short name T712
Test name
Test status
Simulation time 325936678910 ps
CPU time 207.27 seconds
Started Aug 23 05:42:36 AM UTC 24
Finished Aug 23 05:46:06 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804307186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.2804307186
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.3274385582
Short name T740
Test name
Test status
Simulation time 383426164137 ps
CPU time 408.52 seconds
Started Aug 23 05:44:02 AM UTC 24
Finished Aug 23 05:50:55 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274385582 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.3274385582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1474091624
Short name T798
Test name
Test status
Simulation time 598594506669 ps
CPU time 1380.1 seconds
Started Aug 23 05:44:12 AM UTC 24
Finished Aug 23 06:07:26 AM UTC 24
Peak memory 212512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474091624 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.1474091624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.279346431
Short name T750
Test name
Test status
Simulation time 111575273151 ps
CPU time 444.33 seconds
Started Aug 23 05:45:34 AM UTC 24
Finished Aug 23 05:53:03 AM UTC 24
Peak memory 211780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279346431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.279346431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.60568225
Short name T713
Test name
Test status
Simulation time 36329830116 ps
CPU time 45.3 seconds
Started Aug 23 05:45:20 AM UTC 24
Finished Aug 23 05:46:07 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60568225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.60568225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.1867112184
Short name T705
Test name
Test status
Simulation time 4139585137 ps
CPU time 5.67 seconds
Started Aug 23 05:45:13 AM UTC 24
Finished Aug 23 05:45:20 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867112184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1867112184
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.2132708138
Short name T699
Test name
Test status
Simulation time 6019869759 ps
CPU time 7.71 seconds
Started Aug 23 05:42:23 AM UTC 24
Finished Aug 23 05:42:32 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132708138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2132708138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.2749052194
Short name T306
Test name
Test status
Simulation time 178321754665 ps
CPU time 77.75 seconds
Started Aug 23 05:45:43 AM UTC 24
Finished Aug 23 05:47:03 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749052194 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.2749052194
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1060313731
Short name T707
Test name
Test status
Simulation time 7506925062 ps
CPU time 5.59 seconds
Started Aug 23 05:45:36 AM UTC 24
Finished Aug 23 05:45:43 AM UTC 24
Peak memory 211632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1060313731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.adc_ctrl_stress_all_with_rand_reset.1060313731
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.2917767031
Short name T719
Test name
Test status
Simulation time 468802628 ps
CPU time 0.81 seconds
Started Aug 23 05:47:21 AM UTC 24
Finished Aug 23 05:47:23 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917767031 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2917767031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.2684821953
Short name T743
Test name
Test status
Simulation time 505379102731 ps
CPU time 277.82 seconds
Started Aug 23 05:46:25 AM UTC 24
Finished Aug 23 05:51:06 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684821953 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.2684821953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.2346885381
Short name T721
Test name
Test status
Simulation time 353733538209 ps
CPU time 62 seconds
Started Aug 23 05:46:36 AM UTC 24
Finished Aug 23 05:47:40 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346885381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2346885381
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.3452670941
Short name T776
Test name
Test status
Simulation time 329532640281 ps
CPU time 680.88 seconds
Started Aug 23 05:46:07 AM UTC 24
Finished Aug 23 05:57:34 AM UTC 24
Peak memory 212436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452670941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3452670941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1327061786
Short name T716
Test name
Test status
Simulation time 167024675194 ps
CPU time 27.15 seconds
Started Aug 23 05:46:07 AM UTC 24
Finished Aug 23 05:46:35 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327061786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.1327061786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.1591383339
Short name T790
Test name
Test status
Simulation time 498418293452 ps
CPU time 1051.11 seconds
Started Aug 23 05:45:56 AM UTC 24
Finished Aug 23 06:03:38 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591383339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1591383339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.527773789
Short name T774
Test name
Test status
Simulation time 326077813681 ps
CPU time 658.36 seconds
Started Aug 23 05:45:59 AM UTC 24
Finished Aug 23 05:57:05 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527773789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.527773789
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3098477421
Short name T784
Test name
Test status
Simulation time 400668399182 ps
CPU time 845.86 seconds
Started Aug 23 05:46:13 AM UTC 24
Finished Aug 23 06:00:27 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098477421 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.3098477421
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.391086393
Short name T751
Test name
Test status
Simulation time 110812306384 ps
CPU time 391.56 seconds
Started Aug 23 05:46:41 AM UTC 24
Finished Aug 23 05:53:17 AM UTC 24
Peak memory 211968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391086393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.391086393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.1229643314
Short name T718
Test name
Test status
Simulation time 38785895245 ps
CPU time 21.7 seconds
Started Aug 23 05:46:39 AM UTC 24
Finished Aug 23 05:47:02 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229643314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1229643314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.4228657827
Short name T717
Test name
Test status
Simulation time 4909866494 ps
CPU time 3.24 seconds
Started Aug 23 05:46:36 AM UTC 24
Finished Aug 23 05:46:40 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228657827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.4228657827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.3370949050
Short name T710
Test name
Test status
Simulation time 5862449879 ps
CPU time 3.82 seconds
Started Aug 23 05:45:54 AM UTC 24
Finished Aug 23 05:45:59 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370949050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3370949050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.39426569
Short name T64
Test name
Test status
Simulation time 7375551217 ps
CPU time 16.22 seconds
Started Aug 23 05:47:03 AM UTC 24
Finished Aug 23 05:47:20 AM UTC 24
Peak memory 221744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=39426569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
44.adc_ctrl_stress_all_with_rand_reset.39426569
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.3876485629
Short name T732
Test name
Test status
Simulation time 508178725 ps
CPU time 0.86 seconds
Started Aug 23 05:49:18 AM UTC 24
Finished Aug 23 05:49:20 AM UTC 24
Peak memory 209772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876485629 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3876485629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.749063191
Short name T729
Test name
Test status
Simulation time 170119665677 ps
CPU time 36.89 seconds
Started Aug 23 05:48:35 AM UTC 24
Finished Aug 23 05:49:13 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749063191 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.749063191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.2562571669
Short name T324
Test name
Test status
Simulation time 323212799896 ps
CPU time 193.65 seconds
Started Aug 23 05:47:49 AM UTC 24
Finished Aug 23 05:51:05 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562571669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2562571669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1293028600
Short name T757
Test name
Test status
Simulation time 486662672559 ps
CPU time 363.39 seconds
Started Aug 23 05:47:51 AM UTC 24
Finished Aug 23 05:53:58 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293028600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.1293028600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.265946528
Short name T739
Test name
Test status
Simulation time 327491176051 ps
CPU time 196.74 seconds
Started Aug 23 05:47:29 AM UTC 24
Finished Aug 23 05:50:49 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265946528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.265946528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.4054792235
Short name T728
Test name
Test status
Simulation time 166048479656 ps
CPU time 82.74 seconds
Started Aug 23 05:47:41 AM UTC 24
Finished Aug 23 05:49:05 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054792235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.4054792235
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.1080085663
Short name T338
Test name
Test status
Simulation time 415855953438 ps
CPU time 191.12 seconds
Started Aug 23 05:48:02 AM UTC 24
Finished Aug 23 05:51:15 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080085663 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.1080085663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2640641623
Short name T734
Test name
Test status
Simulation time 201963353970 ps
CPU time 55.09 seconds
Started Aug 23 05:48:35 AM UTC 24
Finished Aug 23 05:49:31 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640641623 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.2640641623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.2853294860
Short name T211
Test name
Test status
Simulation time 125771625512 ps
CPU time 411.27 seconds
Started Aug 23 05:48:57 AM UTC 24
Finished Aug 23 05:55:52 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853294860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2853294860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.2518787474
Short name T731
Test name
Test status
Simulation time 23544489008 ps
CPU time 25.93 seconds
Started Aug 23 05:48:50 AM UTC 24
Finished Aug 23 05:49:17 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518787474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2518787474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.1106455591
Short name T726
Test name
Test status
Simulation time 3346570015 ps
CPU time 4.42 seconds
Started Aug 23 05:48:44 AM UTC 24
Finished Aug 23 05:48:50 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106455591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1106455591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.4066619424
Short name T720
Test name
Test status
Simulation time 6005441026 ps
CPU time 3.97 seconds
Started Aug 23 05:47:23 AM UTC 24
Finished Aug 23 05:47:28 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066619424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4066619424
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.1306952067
Short name T772
Test name
Test status
Simulation time 202058637044 ps
CPU time 438.98 seconds
Started Aug 23 05:49:13 AM UTC 24
Finished Aug 23 05:56:37 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306952067 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.1306952067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1076945751
Short name T730
Test name
Test status
Simulation time 11205511574 ps
CPU time 10.84 seconds
Started Aug 23 05:49:05 AM UTC 24
Finished Aug 23 05:49:17 AM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1076945751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.adc_ctrl_stress_all_with_rand_reset.1076945751
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.1107884633
Short name T745
Test name
Test status
Simulation time 396212893 ps
CPU time 1.41 seconds
Started Aug 23 05:51:05 AM UTC 24
Finished Aug 23 05:51:08 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107884633 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1107884633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.2928762129
Short name T762
Test name
Test status
Simulation time 321394456960 ps
CPU time 282.3 seconds
Started Aug 23 05:50:27 AM UTC 24
Finished Aug 23 05:55:13 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928762129 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.2928762129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.949518680
Short name T754
Test name
Test status
Simulation time 316428560223 ps
CPU time 175.61 seconds
Started Aug 23 05:50:45 AM UTC 24
Finished Aug 23 05:53:43 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949518680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.949518680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.2189482032
Short name T763
Test name
Test status
Simulation time 166174869692 ps
CPU time 347.24 seconds
Started Aug 23 05:49:33 AM UTC 24
Finished Aug 23 05:55:24 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189482032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2189482032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1311564500
Short name T765
Test name
Test status
Simulation time 164968194133 ps
CPU time 341.96 seconds
Started Aug 23 05:49:55 AM UTC 24
Finished Aug 23 05:55:40 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311564500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.1311564500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.3308387272
Short name T797
Test name
Test status
Simulation time 497601829542 ps
CPU time 1061.41 seconds
Started Aug 23 05:49:33 AM UTC 24
Finished Aug 23 06:07:26 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308387272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.3308387272
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.2806996216
Short name T791
Test name
Test status
Simulation time 344578558772 ps
CPU time 795.12 seconds
Started Aug 23 05:50:20 AM UTC 24
Finished Aug 23 06:03:42 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806996216 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.2806996216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3866020998
Short name T747
Test name
Test status
Simulation time 204343894469 ps
CPU time 101.72 seconds
Started Aug 23 05:50:24 AM UTC 24
Finished Aug 23 05:52:08 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866020998 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.3866020998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.2024167384
Short name T775
Test name
Test status
Simulation time 101265057002 ps
CPU time 382.34 seconds
Started Aug 23 05:51:01 AM UTC 24
Finished Aug 23 05:57:27 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024167384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2024167384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.2745228467
Short name T749
Test name
Test status
Simulation time 39328069208 ps
CPU time 82.56 seconds
Started Aug 23 05:50:56 AM UTC 24
Finished Aug 23 05:52:20 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745228467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2745228467
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.3271888643
Short name T742
Test name
Test status
Simulation time 5320317316 ps
CPU time 12.97 seconds
Started Aug 23 05:50:49 AM UTC 24
Finished Aug 23 05:51:03 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271888643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3271888643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.274020561
Short name T733
Test name
Test status
Simulation time 5928880664 ps
CPU time 11.81 seconds
Started Aug 23 05:49:18 AM UTC 24
Finished Aug 23 05:49:31 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274020561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.274020561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3176196705
Short name T744
Test name
Test status
Simulation time 2228988436 ps
CPU time 3.31 seconds
Started Aug 23 05:51:02 AM UTC 24
Finished Aug 23 05:51:07 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3176196705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.adc_ctrl_stress_all_with_rand_reset.3176196705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.2346003902
Short name T756
Test name
Test status
Simulation time 509980337 ps
CPU time 1.62 seconds
Started Aug 23 05:53:49 AM UTC 24
Finished Aug 23 05:53:52 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346003902 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2346003902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.958702142
Short name T176
Test name
Test status
Simulation time 502691499426 ps
CPU time 275.13 seconds
Started Aug 23 05:52:21 AM UTC 24
Finished Aug 23 05:57:00 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958702142 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.958702142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.646433523
Short name T781
Test name
Test status
Simulation time 162486505007 ps
CPU time 343.1 seconds
Started Aug 23 05:53:03 AM UTC 24
Finished Aug 23 05:58:50 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646433523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.646433523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.2648665545
Short name T761
Test name
Test status
Simulation time 324125291507 ps
CPU time 194.33 seconds
Started Aug 23 05:51:17 AM UTC 24
Finished Aug 23 05:54:34 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648665545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2648665545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4218127962
Short name T771
Test name
Test status
Simulation time 491922365191 ps
CPU time 302.71 seconds
Started Aug 23 05:51:24 AM UTC 24
Finished Aug 23 05:56:30 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218127962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.4218127962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.3774366848
Short name T787
Test name
Test status
Simulation time 325753492172 ps
CPU time 667.6 seconds
Started Aug 23 05:51:08 AM UTC 24
Finished Aug 23 06:02:22 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774366848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3774366848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.3374310769
Short name T753
Test name
Test status
Simulation time 500522334732 ps
CPU time 132.25 seconds
Started Aug 23 05:51:09 AM UTC 24
Finished Aug 23 05:53:23 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374310769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.3374310769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.1866684525
Short name T345
Test name
Test status
Simulation time 176981089697 ps
CPU time 92.14 seconds
Started Aug 23 05:52:08 AM UTC 24
Finished Aug 23 05:53:42 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866684525 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.1866684525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3876045334
Short name T778
Test name
Test status
Simulation time 594268342481 ps
CPU time 347.14 seconds
Started Aug 23 05:52:16 AM UTC 24
Finished Aug 23 05:58:07 AM UTC 24
Peak memory 211668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876045334 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.3876045334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.3574190156
Short name T212
Test name
Test status
Simulation time 139942968401 ps
CPU time 546.3 seconds
Started Aug 23 05:53:23 AM UTC 24
Finished Aug 23 06:02:35 AM UTC 24
Peak memory 212908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574190156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3574190156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.763526811
Short name T759
Test name
Test status
Simulation time 40328458305 ps
CPU time 41.53 seconds
Started Aug 23 05:53:20 AM UTC 24
Finished Aug 23 05:54:03 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763526811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.763526811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.87576562
Short name T752
Test name
Test status
Simulation time 4145559134 ps
CPU time 1.24 seconds
Started Aug 23 05:53:17 AM UTC 24
Finished Aug 23 05:53:20 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87576562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.87576562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.946794052
Short name T746
Test name
Test status
Simulation time 6061706009 ps
CPU time 15.65 seconds
Started Aug 23 05:51:07 AM UTC 24
Finished Aug 23 05:51:23 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946794052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.946794052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.579365179
Short name T795
Test name
Test status
Simulation time 336567666918 ps
CPU time 729.64 seconds
Started Aug 23 05:53:44 AM UTC 24
Finished Aug 23 06:06:01 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579365179 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.579365179
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1218124329
Short name T758
Test name
Test status
Simulation time 81038701319 ps
CPU time 18.01 seconds
Started Aug 23 05:53:43 AM UTC 24
Finished Aug 23 05:54:02 AM UTC 24
Peak memory 211632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1218124329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.adc_ctrl_stress_all_with_rand_reset.1218124329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.723110393
Short name T768
Test name
Test status
Simulation time 417242090 ps
CPU time 0.66 seconds
Started Aug 23 05:56:03 AM UTC 24
Finished Aug 23 05:56:04 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723110393 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.723110393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.1581097308
Short name T273
Test name
Test status
Simulation time 325889951205 ps
CPU time 668.95 seconds
Started Aug 23 05:54:04 AM UTC 24
Finished Aug 23 06:05:20 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581097308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1581097308
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4123186936
Short name T783
Test name
Test status
Simulation time 332278082982 ps
CPU time 320.25 seconds
Started Aug 23 05:54:10 AM UTC 24
Finished Aug 23 05:59:34 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123186936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.4123186936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.454270203
Short name T773
Test name
Test status
Simulation time 163042103507 ps
CPU time 183.04 seconds
Started Aug 23 05:53:59 AM UTC 24
Finished Aug 23 05:57:04 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454270203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.454270203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.1374209600
Short name T764
Test name
Test status
Simulation time 495169362544 ps
CPU time 95.51 seconds
Started Aug 23 05:54:03 AM UTC 24
Finished Aug 23 05:55:40 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374209600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.1374209600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.1224257624
Short name T796
Test name
Test status
Simulation time 355485849027 ps
CPU time 701.36 seconds
Started Aug 23 05:54:34 AM UTC 24
Finished Aug 23 06:06:23 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224257624 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.1224257624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4073842011
Short name T782
Test name
Test status
Simulation time 201613698599 ps
CPU time 259.57 seconds
Started Aug 23 05:55:03 AM UTC 24
Finished Aug 23 05:59:26 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073842011 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.4073842011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.1431736637
Short name T794
Test name
Test status
Simulation time 132221208117 ps
CPU time 549.85 seconds
Started Aug 23 05:55:53 AM UTC 24
Finished Aug 23 06:05:09 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431736637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1431736637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.3380656513
Short name T767
Test name
Test status
Simulation time 36008939060 ps
CPU time 19.25 seconds
Started Aug 23 05:55:41 AM UTC 24
Finished Aug 23 05:56:02 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380656513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3380656513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.2103411565
Short name T766
Test name
Test status
Simulation time 5278622630 ps
CPU time 12.27 seconds
Started Aug 23 05:55:41 AM UTC 24
Finished Aug 23 05:55:55 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103411565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2103411565
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.3645257233
Short name T760
Test name
Test status
Simulation time 5947128467 ps
CPU time 14.68 seconds
Started Aug 23 05:53:53 AM UTC 24
Finished Aug 23 05:54:09 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645257233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3645257233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.412074414
Short name T789
Test name
Test status
Simulation time 208481059450 ps
CPU time 450.14 seconds
Started Aug 23 05:55:56 AM UTC 24
Finished Aug 23 06:03:31 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412074414 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.412074414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2121488730
Short name T769
Test name
Test status
Simulation time 44816452349 ps
CPU time 14.39 seconds
Started Aug 23 05:55:55 AM UTC 24
Finished Aug 23 05:56:10 AM UTC 24
Peak memory 221960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2121488730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.adc_ctrl_stress_all_with_rand_reset.2121488730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.2971014188
Short name T780
Test name
Test status
Simulation time 413132512 ps
CPU time 0.72 seconds
Started Aug 23 05:58:13 AM UTC 24
Finished Aug 23 05:58:15 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971014188 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2971014188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.4139729080
Short name T316
Test name
Test status
Simulation time 349424027909 ps
CPU time 144.7 seconds
Started Aug 23 05:57:05 AM UTC 24
Finished Aug 23 05:59:32 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139729080 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.4139729080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.2481600079
Short name T792
Test name
Test status
Simulation time 185315807500 ps
CPU time 400.32 seconds
Started Aug 23 05:57:28 AM UTC 24
Finished Aug 23 06:04:14 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481600079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2481600079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2767160931
Short name T799
Test name
Test status
Simulation time 330519003691 ps
CPU time 688.73 seconds
Started Aug 23 05:56:38 AM UTC 24
Finished Aug 23 06:08:14 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767160931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.2767160931
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.1891966301
Short name T340
Test name
Test status
Simulation time 178442653640 ps
CPU time 116.51 seconds
Started Aug 23 05:56:11 AM UTC 24
Finished Aug 23 05:58:09 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891966301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1891966301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.57200753
Short name T786
Test name
Test status
Simulation time 166221319079 ps
CPU time 328.31 seconds
Started Aug 23 05:56:22 AM UTC 24
Finished Aug 23 06:01:54 AM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57200753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.57200753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.3036847103
Short name T801
Test name
Test status
Simulation time 539955729692 ps
CPU time 1067 seconds
Started Aug 23 05:57:01 AM UTC 24
Finished Aug 23 06:14:58 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036847103 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.3036847103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3406759111
Short name T800
Test name
Test status
Simulation time 414650489247 ps
CPU time 994.2 seconds
Started Aug 23 05:57:05 AM UTC 24
Finished Aug 23 06:13:49 AM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406759111 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.3406759111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.1959734537
Short name T788
Test name
Test status
Simulation time 92543575699 ps
CPU time 303.45 seconds
Started Aug 23 05:58:09 AM UTC 24
Finished Aug 23 06:03:15 AM UTC 24
Peak memory 211968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959734537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1959734537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.3069967586
Short name T779
Test name
Test status
Simulation time 46234061000 ps
CPU time 25.47 seconds
Started Aug 23 05:57:46 AM UTC 24
Finished Aug 23 05:58:12 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069967586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3069967586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.1670260738
Short name T777
Test name
Test status
Simulation time 3990325639 ps
CPU time 9.26 seconds
Started Aug 23 05:57:34 AM UTC 24
Finished Aug 23 05:57:45 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670260738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1670260738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.2840191167
Short name T770
Test name
Test status
Simulation time 5935437292 ps
CPU time 15.09 seconds
Started Aug 23 05:56:05 AM UTC 24
Finished Aug 23 05:56:21 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840191167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2840191167
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1814617566
Short name T785
Test name
Test status
Simulation time 368501190203 ps
CPU time 160.25 seconds
Started Aug 23 05:58:10 AM UTC 24
Finished Aug 23 06:00:52 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814617566 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.1814617566
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.583648530
Short name T203
Test name
Test status
Simulation time 5107164311 ps
CPU time 15.6 seconds
Started Aug 23 05:58:10 AM UTC 24
Finished Aug 23 05:58:26 AM UTC 24
Peak memory 221952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=583648530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
49.adc_ctrl_stress_all_with_rand_reset.583648530
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.316794545
Short name T364
Test name
Test status
Simulation time 462966554 ps
CPU time 0.99 seconds
Started Aug 23 04:23:15 AM UTC 24
Finished Aug 23 04:23:17 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316794545 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.316794545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.1405871337
Short name T151
Test name
Test status
Simulation time 162089426438 ps
CPU time 352.03 seconds
Started Aug 23 04:21:54 AM UTC 24
Finished Aug 23 04:27:51 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405871337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1405871337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.3834229426
Short name T160
Test name
Test status
Simulation time 161999846577 ps
CPU time 333.78 seconds
Started Aug 23 04:21:00 AM UTC 24
Finished Aug 23 04:26:38 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834229426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3834229426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3964646015
Short name T195
Test name
Test status
Simulation time 330362692674 ps
CPU time 159.89 seconds
Started Aug 23 04:21:02 AM UTC 24
Finished Aug 23 04:23:44 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964646015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.3964646015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2418624588
Short name T141
Test name
Test status
Simulation time 340275242629 ps
CPU time 202.66 seconds
Started Aug 23 04:20:52 AM UTC 24
Finished Aug 23 04:24:17 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418624588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2418624588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.2232833610
Short name T161
Test name
Test status
Simulation time 161893021907 ps
CPU time 335.46 seconds
Started Aug 23 04:20:59 AM UTC 24
Finished Aug 23 04:26:38 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232833610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.2232833610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.414587276
Short name T371
Test name
Test status
Simulation time 400246923550 ps
CPU time 213.5 seconds
Started Aug 23 04:21:27 AM UTC 24
Finished Aug 23 04:25:04 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414587276 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.414587276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.1507067644
Short name T46
Test name
Test status
Simulation time 71029883179 ps
CPU time 411.69 seconds
Started Aug 23 04:22:20 AM UTC 24
Finished Aug 23 04:29:16 AM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507067644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1507067644
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.2262208419
Short name T366
Test name
Test status
Simulation time 31942905513 ps
CPU time 66.97 seconds
Started Aug 23 04:22:15 AM UTC 24
Finished Aug 23 04:23:23 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262208419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2262208419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.3582232982
Short name T362
Test name
Test status
Simulation time 5082616392 ps
CPU time 3.28 seconds
Started Aug 23 04:22:09 AM UTC 24
Finished Aug 23 04:22:14 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582232982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3582232982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.4147987067
Short name T360
Test name
Test status
Simulation time 6193293680 ps
CPU time 10.56 seconds
Started Aug 23 04:20:50 AM UTC 24
Finished Aug 23 04:21:02 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147987067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4147987067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.552924279
Short name T231
Test name
Test status
Simulation time 321311785596 ps
CPU time 561.82 seconds
Started Aug 23 04:22:31 AM UTC 24
Finished Aug 23 04:31:59 AM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552924279 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.552924279
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3020158784
Short name T370
Test name
Test status
Simulation time 340942777 ps
CPU time 1.18 seconds
Started Aug 23 04:25:01 AM UTC 24
Finished Aug 23 04:25:03 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020158784 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3020158784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3299742572
Short name T248
Test name
Test status
Simulation time 527541976737 ps
CPU time 1125.4 seconds
Started Aug 23 04:24:18 AM UTC 24
Finished Aug 23 04:43:15 AM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299742572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3299742572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.765938104
Short name T190
Test name
Test status
Simulation time 159889903372 ps
CPU time 90.66 seconds
Started Aug 23 04:23:25 AM UTC 24
Finished Aug 23 04:24:57 AM UTC 24
Peak memory 211788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765938104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.765938104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.4002575024
Short name T379
Test name
Test status
Simulation time 491532729840 ps
CPU time 335.69 seconds
Started Aug 23 04:23:24 AM UTC 24
Finished Aug 23 04:29:04 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002575024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.4002575024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.182760893
Short name T143
Test name
Test status
Simulation time 524001612673 ps
CPU time 1042.41 seconds
Started Aug 23 04:23:45 AM UTC 24
Finished Aug 23 04:41:17 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182760893 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.182760893
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.467776938
Short name T375
Test name
Test status
Simulation time 392266730647 ps
CPU time 241.32 seconds
Started Aug 23 04:23:57 AM UTC 24
Finished Aug 23 04:28:02 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467776938 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.467776938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.1188426725
Short name T182
Test name
Test status
Simulation time 96728322283 ps
CPU time 496.59 seconds
Started Aug 23 04:24:31 AM UTC 24
Finished Aug 23 04:32:53 AM UTC 24
Peak memory 212848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188426725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1188426725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.3377458638
Short name T372
Test name
Test status
Simulation time 30497127033 ps
CPU time 32.8 seconds
Started Aug 23 04:24:31 AM UTC 24
Finished Aug 23 04:25:06 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377458638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3377458638
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.3373162533
Short name T369
Test name
Test status
Simulation time 2997395283 ps
CPU time 7.78 seconds
Started Aug 23 04:24:21 AM UTC 24
Finished Aug 23 04:24:30 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373162533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3373162533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.1282405399
Short name T365
Test name
Test status
Simulation time 6046881198 ps
CPU time 4.01 seconds
Started Aug 23 04:23:18 AM UTC 24
Finished Aug 23 04:23:23 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282405399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1282405399
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.376721772
Short name T207
Test name
Test status
Simulation time 242209990194 ps
CPU time 731.1 seconds
Started Aug 23 04:24:58 AM UTC 24
Finished Aug 23 04:37:17 AM UTC 24
Peak memory 212768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376721772 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.376721772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3604971945
Short name T37
Test name
Test status
Simulation time 1620474136 ps
CPU time 3.78 seconds
Started Aug 23 04:24:55 AM UTC 24
Finished Aug 23 04:25:00 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3604971945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.adc_ctrl_stress_all_with_rand_reset.3604971945
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1793512933
Short name T162
Test name
Test status
Simulation time 516202202 ps
CPU time 1.62 seconds
Started Aug 23 04:26:38 AM UTC 24
Finished Aug 23 04:26:41 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793512933 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1793512933
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1540834581
Short name T247
Test name
Test status
Simulation time 340622496764 ps
CPU time 714.6 seconds
Started Aug 23 04:25:57 AM UTC 24
Finished Aug 23 04:37:59 AM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540834581 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.1540834581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.44790344
Short name T139
Test name
Test status
Simulation time 503735836633 ps
CPU time 248.57 seconds
Started Aug 23 04:25:05 AM UTC 24
Finished Aug 23 04:29:16 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44790344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.44790344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2387538783
Short name T159
Test name
Test status
Simulation time 158984250664 ps
CPU time 88.43 seconds
Started Aug 23 04:25:07 AM UTC 24
Finished Aug 23 04:26:37 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387538783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.2387538783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.765551872
Short name T275
Test name
Test status
Simulation time 332154534384 ps
CPU time 761.26 seconds
Started Aug 23 04:25:04 AM UTC 24
Finished Aug 23 04:37:52 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765551872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.765551872
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.1712006514
Short name T380
Test name
Test status
Simulation time 484246896321 ps
CPU time 248.69 seconds
Started Aug 23 04:25:05 AM UTC 24
Finished Aug 23 04:29:17 AM UTC 24
Peak memory 211656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712006514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.1712006514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1011737809
Short name T140
Test name
Test status
Simulation time 527178397293 ps
CPU time 296.82 seconds
Started Aug 23 04:25:13 AM UTC 24
Finished Aug 23 04:30:13 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011737809 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.1011737809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.14821752
Short name T181
Test name
Test status
Simulation time 394301897189 ps
CPU time 431.28 seconds
Started Aug 23 04:25:23 AM UTC 24
Finished Aug 23 04:32:39 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14821752 -assert nopostpro
c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.14821752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2168999796
Short name T52
Test name
Test status
Simulation time 86071715670 ps
CPU time 265.58 seconds
Started Aug 23 04:26:16 AM UTC 24
Finished Aug 23 04:30:45 AM UTC 24
Peak memory 211892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168999796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2168999796
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.756685737
Short name T164
Test name
Test status
Simulation time 36147397619 ps
CPU time 78.23 seconds
Started Aug 23 04:26:13 AM UTC 24
Finished Aug 23 04:27:33 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756685737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.756685737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.1597898727
Short name T374
Test name
Test status
Simulation time 4576136026 ps
CPU time 3.37 seconds
Started Aug 23 04:26:11 AM UTC 24
Finished Aug 23 04:26:16 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597898727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1597898727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.2880078214
Short name T373
Test name
Test status
Simulation time 5749727418 ps
CPU time 7.54 seconds
Started Aug 23 04:25:04 AM UTC 24
Finished Aug 23 04:25:12 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880078214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2880078214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.287858537
Short name T130
Test name
Test status
Simulation time 160897790887 ps
CPU time 80.48 seconds
Started Aug 23 04:26:37 AM UTC 24
Finished Aug 23 04:28:00 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287858537 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.287858537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3027953401
Short name T38
Test name
Test status
Simulation time 24708015270 ps
CPU time 7.55 seconds
Started Aug 23 04:26:34 AM UTC 24
Finished Aug 23 04:26:43 AM UTC 24
Peak memory 221680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3027953401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.adc_ctrl_stress_all_with_rand_reset.3027953401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1505342314
Short name T377
Test name
Test status
Simulation time 331618088 ps
CPU time 0.73 seconds
Started Aug 23 04:28:44 AM UTC 24
Finished Aug 23 04:28:46 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505342314 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1505342314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.622765437
Short name T191
Test name
Test status
Simulation time 167674137268 ps
CPU time 39.73 seconds
Started Aug 23 04:28:00 AM UTC 24
Finished Aug 23 04:28:41 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622765437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.622765437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.528623214
Short name T235
Test name
Test status
Simulation time 329974545268 ps
CPU time 723.89 seconds
Started Aug 23 04:26:55 AM UTC 24
Finished Aug 23 04:39:06 AM UTC 24
Peak memory 212572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528623214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.528623214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3279485222
Short name T383
Test name
Test status
Simulation time 165092588259 ps
CPU time 176.51 seconds
Started Aug 23 04:27:34 AM UTC 24
Finished Aug 23 04:30:34 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279485222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.3279485222
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.1467922202
Short name T276
Test name
Test status
Simulation time 499205912060 ps
CPU time 1075.42 seconds
Started Aug 23 04:26:42 AM UTC 24
Finished Aug 23 04:44:48 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467922202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1467922202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.4039970299
Short name T419
Test name
Test status
Simulation time 493051888497 ps
CPU time 1056.68 seconds
Started Aug 23 04:26:44 AM UTC 24
Finished Aug 23 04:44:30 AM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039970299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.4039970299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.1291519836
Short name T197
Test name
Test status
Simulation time 373405861552 ps
CPU time 733.27 seconds
Started Aug 23 04:27:47 AM UTC 24
Finished Aug 23 04:40:08 AM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291519836 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.1291519836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1239468217
Short name T396
Test name
Test status
Simulation time 193887549360 ps
CPU time 419.84 seconds
Started Aug 23 04:27:51 AM UTC 24
Finished Aug 23 04:34:56 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239468217 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.1239468217
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.1419622659
Short name T51
Test name
Test status
Simulation time 109047737187 ps
CPU time 291.96 seconds
Started Aug 23 04:28:05 AM UTC 24
Finished Aug 23 04:33:00 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419622659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1419622659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.438247827
Short name T381
Test name
Test status
Simulation time 37520410472 ps
CPU time 85.13 seconds
Started Aug 23 04:28:02 AM UTC 24
Finished Aug 23 04:29:29 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438247827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.438247827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.382567681
Short name T376
Test name
Test status
Simulation time 4562842042 ps
CPU time 2.95 seconds
Started Aug 23 04:28:00 AM UTC 24
Finished Aug 23 04:28:04 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382567681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.382567681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1004180282
Short name T163
Test name
Test status
Simulation time 5737545494 ps
CPU time 12.98 seconds
Started Aug 23 04:26:40 AM UTC 24
Finished Aug 23 04:26:54 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004180282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1004180282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.1813269149
Short name T266
Test name
Test status
Simulation time 391916720328 ps
CPU time 816.64 seconds
Started Aug 23 04:28:42 AM UTC 24
Finished Aug 23 04:42:27 AM UTC 24
Peak memory 212528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813269149 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.1813269149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.3083706916
Short name T384
Test name
Test status
Simulation time 325900373 ps
CPU time 0.71 seconds
Started Aug 23 04:30:47 AM UTC 24
Finished Aug 23 04:30:49 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083706916 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3083706916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2987494121
Short name T234
Test name
Test status
Simulation time 386884837698 ps
CPU time 439.53 seconds
Started Aug 23 04:29:18 AM UTC 24
Finished Aug 23 04:36:42 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987494121 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.2987494121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.3712670206
Short name T179
Test name
Test status
Simulation time 163212653484 ps
CPU time 170.42 seconds
Started Aug 23 04:29:30 AM UTC 24
Finished Aug 23 04:32:23 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712670206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3712670206
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.713068525
Short name T411
Test name
Test status
Simulation time 331170982382 ps
CPU time 682.28 seconds
Started Aug 23 04:29:07 AM UTC 24
Finished Aug 23 04:40:36 AM UTC 24
Peak memory 212868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713068525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.713068525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2163569618
Short name T255
Test name
Test status
Simulation time 157029203598 ps
CPU time 346.01 seconds
Started Aug 23 04:28:50 AM UTC 24
Finished Aug 23 04:34:41 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163569618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2163569618
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.4104418030
Short name T424
Test name
Test status
Simulation time 483132720162 ps
CPU time 961.88 seconds
Started Aug 23 04:28:56 AM UTC 24
Finished Aug 23 04:45:07 AM UTC 24
Peak memory 212872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104418030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.4104418030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.501347010
Short name T253
Test name
Test status
Simulation time 399093711013 ps
CPU time 809.77 seconds
Started Aug 23 04:29:17 AM UTC 24
Finished Aug 23 04:42:55 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501347010 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.501347010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1551817977
Short name T185
Test name
Test status
Simulation time 417354906896 ps
CPU time 236.47 seconds
Started Aug 23 04:29:17 AM UTC 24
Finished Aug 23 04:33:16 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551817977 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.1551817977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.463292364
Short name T398
Test name
Test status
Simulation time 71404072362 ps
CPU time 275.92 seconds
Started Aug 23 04:30:34 AM UTC 24
Finished Aug 23 04:35:13 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463292364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.463292364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.3633732454
Short name T386
Test name
Test status
Simulation time 32508407521 ps
CPU time 65.03 seconds
Started Aug 23 04:30:18 AM UTC 24
Finished Aug 23 04:31:25 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633732454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3633732454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.2965124985
Short name T382
Test name
Test status
Simulation time 3847377778 ps
CPU time 2.48 seconds
Started Aug 23 04:30:14 AM UTC 24
Finished Aug 23 04:30:18 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965124985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2965124985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.1645640074
Short name T378
Test name
Test status
Simulation time 5561360165 ps
CPU time 2.65 seconds
Started Aug 23 04:28:46 AM UTC 24
Finished Aug 23 04:28:50 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645640074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1645640074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1808597336
Short name T237
Test name
Test status
Simulation time 369421530656 ps
CPU time 192.36 seconds
Started Aug 23 04:30:46 AM UTC 24
Finished Aug 23 04:34:01 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808597336 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.1808597336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest
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