Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1138859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1119667

1

T1

2

T3

32

T19

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1991289	1			T1	1		T2	1		T19	1
values[0x0]	133189	1			T1	6		T2	1		T3	26
values[0x1]	134048	1			T1	5		T2	1		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	912346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1346180

1

T1

5

T3

38

T19

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6654	1			T3	16		T9	1		T10	10
valid_sources[0x01]	12696	1			T4	1		T6	1		T10	7
valid_sources[0x02]	10613	1			T8	2		T10	5		T122	1
valid_sources[0x03]	11695	1			T10	7		T11	2		T14	1
valid_sources[0x04]	9562	1			T19	1		T5	1		T6	3
valid_sources[0x05]	7990	1			T4	2		T9	1		T10	2
valid_sources[0x06]	6744	1			T6	1		T10	5		T14	2
valid_sources[0x07]	6710	1			T9	2		T10	3		T14	5
valid_sources[0x08]	7419	1			T4	1		T9	2		T10	15
valid_sources[0x09]	7679	1			T7	1		T8	5		T10	3
valid_sources[0x0a]	7055	1			T6	1		T12	15		T14	6
valid_sources[0x0b]	7810	1			T4	1		T7	1		T8	1
valid_sources[0x0c]	6330	1			T6	2		T10	2		T14	2
valid_sources[0x0d]	7590	1			T6	3		T8	1		T9	1
valid_sources[0x0e]	13741	1			T5	1		T9	1		T10	2
valid_sources[0x0f]	6616	1			T6	2		T9	2		T10	3
valid_sources[0x10]	6504	1			T7	1		T10	2		T16	6
valid_sources[0x11]	6670	1			T6	1		T10	7		T11	1
valid_sources[0x12]	7820	1			T10	3		T14	5		T122	1
valid_sources[0x13]	9086	1			T6	9		T8	2		T10	3
valid_sources[0x14]	10690	1			T6	5		T8	2		T10	8
valid_sources[0x15]	7184	1			T6	1		T9	2		T10	5
valid_sources[0x16]	11275	1			T4	5		T7	2		T8	1
valid_sources[0x17]	11317	1			T6	1		T8	1		T9	1
valid_sources[0x18]	7450	1			T9	1		T10	11		T13	15
valid_sources[0x19]	11248	1			T6	1		T9	1		T10	4
valid_sources[0x1a]	6959	1			T6	1		T9	1		T10	5
valid_sources[0x1b]	7635	1			T6	1		T9	2		T10	1
valid_sources[0x1c]	6794	1			T6	1		T10	3		T14	1
valid_sources[0x1d]	7457	1			T5	1		T6	5		T9	1
valid_sources[0x1e]	15147	1			T10	12		T14	2		T71	1
valid_sources[0x1f]	6358	1			T3	2		T20	1		T10	6
valid_sources[0x20]	16391	1			T21	1		T10	5		T14	8
valid_sources[0x21]	6599	1			T6	1		T10	2		T14	1
valid_sources[0x22]	6605	1			T8	3		T10	13		T11	2
valid_sources[0x23]	10897	1			T6	1		T9	1		T10	6
valid_sources[0x24]	6436	1			T6	1		T10	2		T122	3
valid_sources[0x25]	9220	1			T6	1		T10	5		T14	1
valid_sources[0x26]	6714	1			T4	2		T6	3		T10	2
valid_sources[0x27]	6328	1			T10	2		T17	5		T18	14
valid_sources[0x28]	6853	1			T6	1		T9	1		T10	9
valid_sources[0x29]	6792	1			T8	2		T10	4		T16	1
valid_sources[0x2a]	11910	1			T9	1		T10	7		T16	2
valid_sources[0x2b]	6988	1			T6	2		T10	4		T11	2
valid_sources[0x2c]	13470	1			T5	2		T10	3		T71	1
valid_sources[0x2d]	6809	1			T6	3		T8	1		T10	6
valid_sources[0x2e]	6880	1			T4	1		T6	1		T8	2
valid_sources[0x2f]	12214	1			T6	1		T9	1		T10	4
valid_sources[0x30]	7506	1			T10	7		T12	1		T22	4
valid_sources[0x31]	11200	1			T6	1		T21	1		T8	2
valid_sources[0x32]	6436	1			T10	4		T14	1		T122	1
valid_sources[0x33]	6858	1			T4	2		T6	1		T9	1
valid_sources[0x34]	7899	1			T6	1		T9	1		T10	10
valid_sources[0x35]	24140	1			T10	7		T11	8		T122	2
valid_sources[0x36]	10917	1			T7	2		T10	8		T14	3
valid_sources[0x37]	11417	1			T6	1		T7	1		T8	2
valid_sources[0x38]	6626	1			T6	2		T10	6		T11	3
valid_sources[0x39]	6538	1			T9	1		T10	9		T122	1
valid_sources[0x3a]	7870	1			T9	5		T10	4		T14	1
valid_sources[0x3b]	7220	1			T9	1		T10	7		T12	17
valid_sources[0x3c]	6958	1			T6	1		T10	6		T14	12
valid_sources[0x3d]	7081	1			T6	5		T10	1		T14	1
valid_sources[0x3e]	6514	1			T4	3		T6	1		T7	1
valid_sources[0x3f]	7153	1			T9	3		T10	1		T14	2
valid_sources[0x40]	7279	1			T9	1		T10	5		T16	2
valid_sources[0x41]	7968	1			T6	1		T10	5		T71	1
valid_sources[0x42]	11136	1			T6	3		T9	2		T10	1
valid_sources[0x43]	7704	1			T4	1		T10	3		T13	15
valid_sources[0x44]	15494	1			T10	6		T17	1		T18	4
valid_sources[0x45]	6666	1			T10	5		T66	1		T14	1
valid_sources[0x46]	7126	1			T2	2		T10	11		T13	1
valid_sources[0x47]	15428	1			T6	1		T21	1		T10	7
valid_sources[0x48]	9877	1			T6	1		T7	1		T8	1
valid_sources[0x49]	11855	1			T10	4		T13	15		T122	5
valid_sources[0x4a]	11678	1			T6	2		T9	1		T10	16
valid_sources[0x4b]	7308	1			T7	1		T9	5		T10	5
valid_sources[0x4c]	6911	1			T19	1		T6	1		T8	1
valid_sources[0x4d]	6674	1			T7	1		T8	2		T9	1
valid_sources[0x4e]	7386	1			T6	1		T8	1		T9	2
valid_sources[0x4f]	11994	1			T6	2		T10	2		T22	14
valid_sources[0x50]	6899	1			T20	1		T6	2		T8	3
valid_sources[0x51]	17660	1			T8	1		T9	1		T10	6
valid_sources[0x52]	7000	1			T6	1		T9	4		T10	5
valid_sources[0x53]	6913	1			T9	2		T10	4		T14	4
valid_sources[0x54]	10997	1			T6	2		T8	2		T10	7
valid_sources[0x55]	7888	1			T3	7		T4	2		T10	4
valid_sources[0x56]	6970	1			T6	2		T7	1		T10	8
valid_sources[0x57]	10374	1			T8	1		T10	3		T16	5
valid_sources[0x58]	7049	1			T1	6		T6	1		T10	9
valid_sources[0x59]	6588	1			T7	1		T10	3		T13	128
valid_sources[0x5a]	6781	1			T5	10		T6	1		T10	5
valid_sources[0x5b]	10710	1			T3	2		T8	1		T9	1
valid_sources[0x5c]	7688	1			T10	3		T71	1		T16	2
valid_sources[0x5d]	7522	1			T10	2		T16	4		T17	3
valid_sources[0x5e]	10822	1			T8	1		T9	2		T10	4
valid_sources[0x5f]	6614	1			T6	1		T10	8		T11	3
valid_sources[0x60]	7320	1			T10	4		T13	15		T14	1
valid_sources[0x61]	10418	1			T6	3		T8	4		T9	1
valid_sources[0x62]	6354	1			T20	3		T6	1		T8	1
valid_sources[0x63]	6840	1			T6	3		T8	2		T9	1
valid_sources[0x64]	6628	1			T10	8		T122	2		T71	1
valid_sources[0x65]	6241	1			T8	1		T9	1		T10	3
valid_sources[0x66]	6469	1			T9	1		T10	4		T13	1
valid_sources[0x67]	6554	1			T8	1		T9	1		T10	1
valid_sources[0x68]	7124	1			T6	4		T10	7		T14	3
valid_sources[0x69]	7090	1			T6	4		T9	1		T10	6
valid_sources[0x6a]	11135	1			T8	1		T9	1		T10	7
valid_sources[0x6b]	20778	1			T10	1		T14	1		T16	3
valid_sources[0x6c]	9211	1			T4	3		T10	1		T14	2
valid_sources[0x6d]	10952	1			T6	1		T10	23		T14	2
valid_sources[0x6e]	11076	1			T1	1		T6	1		T10	5
valid_sources[0x6f]	7382	1			T10	3		T14	9		T16	4
valid_sources[0x70]	10383	1			T10	5		T13	15		T14	1
valid_sources[0x71]	6614	1			T4	2		T5	3		T6	2
valid_sources[0x72]	7151	1			T10	5		T16	2		T17	7
valid_sources[0x73]	11997	1			T6	3		T14	1		T16	3
valid_sources[0x74]	9304	1			T6	1		T10	4		T14	4
valid_sources[0x75]	6612	1			T10	11		T14	2		T16	3
valid_sources[0x76]	7100	1			T6	1		T7	1		T10	5
valid_sources[0x77]	6554	1			T8	3		T63	1		T122	7
valid_sources[0x78]	6539	1			T6	1		T9	1		T10	8
valid_sources[0x79]	8591	1			T6	1		T10	14		T125	1
valid_sources[0x7a]	6180	1			T6	1		T10	3		T11	1
valid_sources[0x7b]	10806	1			T6	1		T10	4		T14	1
valid_sources[0x7c]	6894	1			T10	1		T14	7		T16	1
valid_sources[0x7d]	13158	1			T6	1		T8	1		T9	4
valid_sources[0x7e]	8950	1			T2	1		T20	3		T6	1
valid_sources[0x7f]	23310	1			T7	1		T9	2		T10	11
valid_sources[0x80]	16035	1			T6	3		T8	1		T10	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

993808

1

T1

1

T19

1

T6

78

values[0x0]

all_enables

biggest_size

72980

1

T1

1

T3

16

T19

2

values[0x1]

all_enables

biggest_size

52879

1

T3

16

T4

9

T20

1