Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26646	1			T6	9		T7	9		T13	43
auto[PWRUP]	80	1			T70	1		T38	1		T74	1
auto[ONEST_0]	58	1			T38	1		T77	1		T74	2
auto[ONEST_021]	20	1			T81	1		T82	1		T219	1
auto[ONEST_1]	74	1			T13	1		T77	1		T74	1
auto[ONEST_DONE]	7	1			T220	1		T221	1		T222	1
auto[LP_0]	98	1			T38	1		T77	1		T74	1
auto[LP_021]	22	1			T74	1		T223	1		T224	1
auto[LP_1]	100	1			T13	1		T70	1		T38	1
auto[LP_EVAL]	41	1			T6	1		T38	1		T77	1
auto[LP_SLP]	424	1			T13	2		T38	8		T77	7
auto[LP_PWRUP]	20	1			T38	1		T75	1		T220	1
auto[NP_0]	116	1			T74	3		T75	1		T220	3
auto[NP_021]	26	1			T38	1		T220	1		T81	1
auto[NP_1]	132	1			T68	1		T70	1		T77	2
auto[NP_EVAL]	27	1			T74	2		T75	1		T81	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T221

1

T225

1

T226

1

min

26188

1

T6

9

T7

9

T13

44

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26193	1			T6	9		T7	9		T13	44
pow[0x1]	8	1			T227	1		T228	1		T57	1
pow[0x2]	9	1			T74	1		T75	1		T219	1
pow[0x3]	48	1			T68	1		T74	1		T220	2
pow[0x4]	52	1			T77	1		T75	1		T76	2
pow[0x5]	119	1			T38	3		T74	2		T75	1
pow[0x6]	201	1			T70	1		T38	1		T77	3
pow[0x7]	409	1			T6	1		T38	3		T77	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

168

1

T6

1

T38

1

T74

4

min

25810

1

T6

9

T7

9

T13

41

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25810	1			T6	9		T7	9		T13	41
pow[0x3]	1	1			T229	1		-	-		-	-
pow[0x5]	1	1			T221	1		-	-		-	-
pow[0x6]	1	1			T230	1		-	-		-	-
pow[0x7]	1	1			T231	1		-	-		-	-
pow[0x8]	6	1			T225	1		T232	1		T231	1
pow[0x9]	5	1			T229	1		T232	1		T233	1
pow[0xa]	17	1			T74	1		T75	1		T220	1
pow[0xb]	21	1			T38	1		T220	1		T78	2
pow[0xc]	71	1			T74	1		T75	2		T76	1
pow[0xd]	108	1			T70	1		T38	3		T77	2
pow[0xe]	242	1			T13	1		T38	3		T77	1
pow[0xf]	465	1			T13	4		T70	1		T38	3