Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	1969	1			T2	10		T6	7		T21	20
auto[PWRUP]	127	1			T6	1		T12	1		T69	1
auto[ONEST_0]	60	1			T12	1		T16	1		T24	1
auto[ONEST_021]	18	1			T81	1		T82	1		T26	1
auto[ONEST_1]	81	1			T38	2		T74	1		T75	1
auto[ONEST_DONE]	2	1			T57	1		T386	1		-	-
auto[LP_0]	117	1			T12	1		T77	1		T74	1
auto[LP_021]	30	1			T75	3		T76	1		T387	1
auto[LP_1]	121	1			T10	1		T13	1		T69	1
auto[LP_EVAL]	45	1			T12	1		T14	1		T69	1
auto[LP_SLP]	459	1			T12	1		T13	1		T58	1
auto[LP_PWRUP]	26	1			T77	1		T74	2		T81	2
auto[NP_0]	150	1			T10	2		T12	1		T13	2
auto[NP_021]	39	1			T10	1		T12	1		T13	1
auto[NP_1]	176	1			T10	1		T14	2		T58	1
auto[NP_EVAL]	23	1			T10	1		T68	1		T70	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T245

1

T78

1

T79

1

min

1701

1

T2

10

T6

7

T21

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1711	1			T2	10		T6	7		T21	20
pow[0x1]	5	1			T10	1		T227	1		T388	1
pow[0x2]	18	1			T70	1		T38	2		T74	1
pow[0x3]	29	1			T38	1		T75	2		T76	1
pow[0x4]	57	1			T12	1		T387	1		T78	1
pow[0x5]	106	1			T38	2		T77	3		T74	3
pow[0x6]	222	1			T38	3		T77	6		T74	1
pow[0x7]	416	1			T13	1		T70	1		T73	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

170

1

T73

1

T38

4

T77

2

min

1221

1

T2

10

T6

7

T21

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1226	1			T2	10		T6	7		T21	20
pow[0x1]	10	1			T12	1		T14	2		T73	1
pow[0x2]	15	1			T10	3		T68	1		T164	1
pow[0x3]	21	1			T10	1		T13	3		T58	2
pow[0x4]	22	1			T10	1		T16	1		T70	3
pow[0x6]	2	1			T77	1		T386	1		-	-
pow[0x7]	3	1			T6	1		T221	1		T226	1
pow[0x8]	5	1			T76	1		T389	1		T344	1
pow[0x9]	5	1			T390	1		T231	1		T372	1
pow[0xa]	11	1			T74	1		T387	1		T90	1
pow[0xb]	25	1			T75	1		T220	1		T221	1
pow[0xc]	57	1			T38	1		T77	1		T74	2
pow[0xd]	126	1			T12	1		T77	1		T74	2
pow[0xe]	220	1			T70	1		T38	2		T77	5
pow[0xf]	491	1			T13	1		T38	7		T77	8