Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2618	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2580	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2550	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2680	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2633	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2740	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2573	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2666	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2762	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2661	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2662	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2618	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2585	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2549	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2551	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2624	0	0
adc_en_ctl_rd_A	2147483647	2185	0	0
adc_fsm_rst_rd_A	2147483647	2217	0	0
adc_intr_ctl_rd_A	2147483647	2598	0	0
adc_lp_sample_ctl_rd_A	2147483647	2108	0	0
adc_pd_ctl_rd_A	2147483647	2554	0	0
adc_sample_ctl_rd_A	2147483647	1884	0	0
adc_wakeup_ctl_rd_A	2147483647	2208	0	0
intr_enable_rd_A	2147483647	2256	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2618	0	0
T24	118846	5	0	0
T25	0	40	0	0
T26	0	12	0	0
T27	0	27	0	0
T28	0	10	0	0
T29	0	23	0	0
T30	0	35	0	0
T31	0	13	0	0
T32	0	15	0	0
T33	0	2	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2580	0	0
T24	118846	7	0	0
T25	0	30	0	0
T26	0	19	0	0
T27	0	20	0	0
T28	0	9	0	0
T29	0	35	0	0
T30	0	51	0	0
T31	0	14	0	0
T32	0	7	0	0
T33	0	6	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2550	0	0
T24	118846	11	0	0
T25	0	40	0	0
T26	0	10	0	0
T27	0	24	0	0
T28	0	18	0	0
T29	0	20	0	0
T30	0	36	0	0
T31	0	9	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2680	0	0
T24	118846	10	0	0
T25	0	38	0	0
T26	0	15	0	0
T27	0	16	0	0
T28	0	5	0	0
T29	0	23	0	0
T30	0	45	0	0
T31	0	6	0	0
T32	0	11	0	0
T33	0	4	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2633	0	0
T24	118846	9	0	0
T25	0	33	0	0
T26	0	16	0	0
T27	0	20	0	0
T28	0	5	0	0
T29	0	27	0	0
T30	0	48	0	0
T31	0	8	0	0
T32	0	8	0	0
T33	0	8	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2740	0	0
T25	545147	36	0	0
T26	0	10	0	0
T27	0	23	0	0
T28	0	12	0	0
T29	0	11	0	0
T30	0	30	0	0
T31	0	7	0	0
T32	0	19	0	0
T43	0	28	0	0
T44	0	113	0	0
T45	197231	0	0	0
T46	161121	0	0	0
T47	74654	0	0	0
T48	574740	0	0	0
T49	162021	0	0	0
T50	138286	0	0	0
T51	505602	0	0	0
T52	40042	0	0	0
T53	159973	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2573	0	0
T24	118846	9	0	0
T25	0	62	0	0
T26	0	24	0	0
T27	0	21	0	0
T28	0	9	0	0
T29	0	15	0	0
T30	0	30	0	0
T31	0	1	0	0
T32	0	12	0	0
T33	0	4	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2666	0	0
T24	118846	12	0	0
T25	0	30	0	0
T26	0	11	0	0
T27	0	30	0	0
T28	0	10	0	0
T29	0	20	0	0
T30	0	49	0	0
T31	0	15	0	0
T32	0	3	0	0
T33	0	4	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2762	0	0
T24	118846	8	0	0
T25	0	40	0	0
T26	0	26	0	0
T27	0	21	0	0
T28	0	7	0	0
T29	0	23	0	0
T30	0	42	0	0
T31	0	1	0	0
T33	0	4	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0
T43	0	35	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2661	0	0
T24	118846	5	0	0
T25	0	34	0	0
T26	0	19	0	0
T27	0	9	0	0
T28	0	8	0	0
T29	0	27	0	0
T30	0	39	0	0
T31	0	4	0	0
T32	0	21	0	0
T33	0	7	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2662	0	0
T24	118846	18	0	0
T25	0	53	0	0
T26	0	28	0	0
T27	0	12	0	0
T28	0	7	0	0
T29	0	24	0	0
T30	0	36	0	0
T31	0	9	0	0
T32	0	19	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0
T43	0	15	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2618	0	0
T24	118846	16	0	0
T25	0	31	0	0
T26	0	20	0	0
T27	0	10	0	0
T28	0	9	0	0
T29	0	10	0	0
T30	0	28	0	0
T31	0	10	0	0
T32	0	18	0	0
T33	0	9	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2585	0	0
T24	118846	9	0	0
T25	0	47	0	0
T26	0	11	0	0
T27	0	18	0	0
T28	0	2	0	0
T29	0	17	0	0
T30	0	40	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0
T43	0	17	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2549	0	0
T24	118846	2	0	0
T25	0	33	0	0
T26	0	13	0	0
T27	0	24	0	0
T28	0	16	0	0
T29	0	14	0	0
T30	0	36	0	0
T31	0	6	0	0
T32	0	29	0	0
T33	0	8	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2551	0	0
T24	118846	13	0	0
T25	0	37	0	0
T26	0	15	0	0
T27	0	23	0	0
T28	0	1	0	0
T29	0	23	0	0
T30	0	34	0	0
T31	0	9	0	0
T32	0	8	0	0
T33	0	1	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2624	0	0
T24	118846	16	0	0
T25	0	27	0	0
T26	0	9	0	0
T27	0	11	0	0
T28	0	1	0	0
T29	0	20	0	0
T30	0	29	0	0
T31	0	16	0	0
T33	0	3	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0
T43	0	27	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2185	0	0
T24	118846	2	0	0
T25	0	19	0	0
T26	0	15	0	0
T27	0	17	0	0
T28	0	7	0	0
T29	0	34	0	0
T30	0	28	0	0
T31	0	11	0	0
T32	0	10	0	0
T33	0	3	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2217	0	0
T24	118846	10	0	0
T25	0	36	0	0
T26	0	3	0	0
T27	0	9	0	0
T28	0	19	0	0
T29	0	31	0	0
T30	0	40	0	0
T31	0	11	0	0
T32	0	14	0	0
T33	0	3	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2598	0	0
T24	118846	5	0	0
T25	0	37	0	0
T26	0	21	0	0
T27	0	16	0	0
T28	0	11	0	0
T29	0	14	0	0
T30	0	44	0	0
T31	0	9	0	0
T32	0	15	0	0
T33	0	2	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2108	0	0
T24	118846	15	0	0
T25	0	18	0	0
T26	0	16	0	0
T27	0	8	0	0
T28	0	14	0	0
T29	0	25	0	0
T30	0	55	0	0
T31	0	12	0	0
T32	0	3	0	0
T33	0	5	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2554	0	0
T24	118846	4	0	0
T25	0	42	0	0
T26	0	20	0	0
T27	0	16	0	0
T28	0	9	0	0
T29	0	5	0	0
T30	0	47	0	0
T31	0	8	0	0
T32	0	15	0	0
T33	0	8	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1884	0	0
T24	118846	2	0	0
T25	0	29	0	0
T26	0	25	0	0
T27	0	20	0	0
T28	0	15	0	0
T29	0	28	0	0
T30	0	43	0	0
T31	0	3	0	0
T32	0	14	0	0
T33	0	4	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2208	0	0
T24	118846	12	0	0
T25	0	32	0	0
T26	0	13	0	0
T27	0	13	0	0
T28	0	14	0	0
T29	0	13	0	0
T30	0	49	0	0
T31	0	8	0	0
T32	0	6	0	0
T33	0	4	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256	0	0
T24	118846	20	0	0
T25	0	94	0	0
T26	0	25	0	0
T27	0	19	0	0
T28	0	30	0	0
T29	0	16	0	0
T34	105953	0	0	0
T35	20492	0	0	0
T36	467484	0	0	0
T37	285492	0	0	0
T38	196650	0	0	0
T39	135923	0	0	0
T40	793121	0	0	0
T41	440624	0	0	0
T42	808799	0	0	0
T54	0	10	0	0
T55	0	26	0	0
T56	0	12	0	0
T57	0	29	0	0