Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1135462	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1112560

1

T1

2

T2

2

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1972064	1			T1	1		T2	1		T3	1
values[0x0]	137470	1			T1	2		T2	5		T3	13
values[0x1]	138488	1			T1	1		T2	3		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	908340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1339682

1

T1

2

T2

2

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16276	1			T6	2		T8	1		T60	6
valid_sources[0x01]	6455	1			T12	1		T69	8		T60	1
valid_sources[0x02]	7471	1			T2	1		T60	1		T61	6
valid_sources[0x03]	6620	1			T4	1		T6	1		T12	2
valid_sources[0x04]	14667	1			T4	1		T7	1		T60	2
valid_sources[0x05]	8091	1			T4	1		T6	3		T12	3
valid_sources[0x06]	6732	1			T10	6		T12	1		T14	1
valid_sources[0x07]	6973	1			T4	1		T8	2		T60	2
valid_sources[0x08]	6701	1			T6	4		T8	1		T10	11
valid_sources[0x09]	7649	1			T6	1		T8	1		T10	4
valid_sources[0x0a]	7140	1			T4	1		T6	6		T7	8
valid_sources[0x0b]	6563	1			T4	1		T6	1		T8	2
valid_sources[0x0c]	6553	1			T2	1		T4	1		T5	5
valid_sources[0x0d]	6691	1			T14	2		T16	3		T97	1
valid_sources[0x0e]	9390	1			T12	2		T13	1		T14	3
valid_sources[0x0f]	7144	1			T6	4		T26	1		T12	2
valid_sources[0x10]	6435	1			T12	2		T14	5		T15	1
valid_sources[0x11]	14137	1			T4	2		T10	2		T13	1
valid_sources[0x12]	11088	1			T4	1		T12	1		T60	3
valid_sources[0x13]	11783	1			T6	1		T14	3		T16	5
valid_sources[0x14]	9706	1			T4	2		T6	3		T7	8
valid_sources[0x15]	7467	1			T4	2		T12	1		T14	2
valid_sources[0x16]	9330	1			T10	2		T12	2		T60	1
valid_sources[0x17]	6417	1			T4	2		T6	1		T12	3
valid_sources[0x18]	6707	1			T6	4		T12	1		T13	1
valid_sources[0x19]	9299	1			T2	1		T7	3		T8	1
valid_sources[0x1a]	6935	1			T8	1		T10	1		T11	1
valid_sources[0x1b]	7736	1			T4	1		T12	1		T60	2
valid_sources[0x1c]	10878	1			T4	1		T10	4		T25	1
valid_sources[0x1d]	10390	1			T4	2		T6	2		T8	1
valid_sources[0x1e]	6694	1			T2	1		T4	1		T6	6
valid_sources[0x1f]	11006	1			T7	2		T10	2		T61	1
valid_sources[0x20]	8983	1			T6	4		T69	7		T60	3
valid_sources[0x21]	7354	1			T4	2		T12	3		T60	4
valid_sources[0x22]	6737	1			T6	4		T12	3		T61	3
valid_sources[0x23]	7161	1			T4	1		T12	1		T60	8
valid_sources[0x24]	10710	1			T14	3		T16	8		T17	4262
valid_sources[0x25]	6499	1			T10	3		T60	1		T14	2
valid_sources[0x26]	6421	1			T4	1		T12	1		T13	1
valid_sources[0x27]	8177	1			T4	1		T6	3		T8	1
valid_sources[0x28]	6383	1			T4	2		T6	1		T12	2
valid_sources[0x29]	6335	1			T4	1		T6	1		T12	2
valid_sources[0x2a]	6745	1			T1	1		T12	4		T13	1
valid_sources[0x2b]	6856	1			T4	1		T6	8		T10	1
valid_sources[0x2c]	6927	1			T4	1		T6	3		T8	2
valid_sources[0x2d]	11237	1			T4	5		T6	7		T7	3
valid_sources[0x2e]	8449	1			T6	2		T12	3		T69	4
valid_sources[0x2f]	6324	1			T10	5		T12	2		T69	9
valid_sources[0x30]	10467	1			T4	3		T5	16		T8	1
valid_sources[0x31]	15099	1			T6	9		T8	1		T10	5
valid_sources[0x32]	6302	1			T4	2		T6	3		T12	2
valid_sources[0x33]	9382	1			T7	6		T24	3		T8	2
valid_sources[0x34]	8116	1			T6	3		T8	2		T69	9
valid_sources[0x35]	11028	1			T12	1		T13	1		T69	4
valid_sources[0x36]	6779	1			T4	2		T10	2		T12	2
valid_sources[0x37]	6704	1			T7	3		T11	1		T16	18
valid_sources[0x38]	6233	1			T10	1		T12	1		T61	5
valid_sources[0x39]	7682	1			T2	1		T5	6		T8	2
valid_sources[0x3a]	7488	1			T6	3		T8	1		T10	1
valid_sources[0x3b]	12359	1			T4	2		T7	3		T8	1
valid_sources[0x3c]	10647	1			T8	4		T11	8		T12	3
valid_sources[0x3d]	10680	1			T6	1		T12	1		T60	1
valid_sources[0x3e]	9841	1			T8	1		T12	1		T69	6
valid_sources[0x3f]	7769	1			T4	1		T6	4		T8	1
valid_sources[0x40]	7645	1			T6	2		T12	2		T14	1
valid_sources[0x41]	7002	1			T4	1		T6	1		T8	1
valid_sources[0x42]	6849	1			T4	2		T12	1		T69	4
valid_sources[0x43]	6644	1			T6	1		T8	2		T12	1
valid_sources[0x44]	11430	1			T6	8		T60	2		T14	2
valid_sources[0x45]	6515	1			T8	1		T12	2		T61	1
valid_sources[0x46]	22767	1			T4	1		T12	1		T13	1
valid_sources[0x47]	15816	1			T6	1		T12	2		T60	3
valid_sources[0x48]	7909	1			T4	1		T6	1		T8	1
valid_sources[0x49]	16041	1			T8	1		T12	1		T14	2
valid_sources[0x4a]	12068	1			T4	1		T12	1		T60	1
valid_sources[0x4b]	10860	1			T8	1		T10	1		T12	4
valid_sources[0x4c]	6600	1			T12	2		T69	1		T60	1
valid_sources[0x4d]	8803	1			T8	4		T14	1		T16	20
valid_sources[0x4e]	11855	1			T4	2		T6	3		T12	2
valid_sources[0x4f]	9632	1			T4	1		T8	4		T12	1
valid_sources[0x50]	8441	1			T4	1		T6	1		T12	1
valid_sources[0x51]	12262	1			T13	1		T14	2		T16	17
valid_sources[0x52]	6439	1			T6	3		T8	2		T12	1
valid_sources[0x53]	6825	1			T6	1		T14	2		T16	48
valid_sources[0x54]	6826	1			T2	1		T8	1		T60	5
valid_sources[0x55]	6874	1			T6	1		T25	1		T12	1
valid_sources[0x56]	7652	1			T4	1		T10	2		T13	1
valid_sources[0x57]	7284	1			T8	1		T60	2		T61	2
valid_sources[0x58]	11036	1			T6	3		T12	4		T60	1
valid_sources[0x59]	11831	1			T6	3		T10	3		T12	1
valid_sources[0x5a]	6306	1			T4	1		T6	3		T8	1
valid_sources[0x5b]	11288	1			T4	1		T8	1		T12	3
valid_sources[0x5c]	9260	1			T6	2		T12	1		T14	2
valid_sources[0x5d]	6539	1			T4	1		T14	2		T16	21
valid_sources[0x5e]	7979	1			T4	1		T6	1		T10	1
valid_sources[0x5f]	6386	1			T12	3		T14	1		T16	11
valid_sources[0x60]	10956	1			T8	1		T69	4		T61	2
valid_sources[0x61]	10844	1			T10	4		T12	4		T69	1
valid_sources[0x62]	6722	1			T4	1		T60	1		T14	2
valid_sources[0x63]	8478	1			T6	10		T8	1		T10	1
valid_sources[0x64]	7502	1			T4	1		T6	1		T8	1
valid_sources[0x65]	7057	1			T6	3		T11	1		T12	1
valid_sources[0x66]	7480	1			T4	2		T69	1		T14	3
valid_sources[0x67]	6545	1			T12	1		T14	1		T16	24
valid_sources[0x68]	7480	1			T8	1		T14	2		T16	16
valid_sources[0x69]	15547	1			T4	3		T8	1		T10	4
valid_sources[0x6a]	7705	1			T4	1		T6	5		T14	1
valid_sources[0x6b]	13328	1			T8	1		T10	1		T12	5
valid_sources[0x6c]	6618	1			T8	1		T12	1		T72	3
valid_sources[0x6d]	7736	1			T13	1		T14	3		T15	1
valid_sources[0x6e]	6650	1			T4	2		T12	2		T60	1
valid_sources[0x6f]	10897	1			T12	1		T13	1		T69	1
valid_sources[0x70]	7186	1			T8	1		T12	2		T60	4
valid_sources[0x71]	6342	1			T6	2		T16	25		T18	1
valid_sources[0x72]	6511	1			T7	2		T12	3		T13	1
valid_sources[0x73]	7671	1			T4	1		T12	2		T61	1
valid_sources[0x74]	11532	1			T12	1		T69	5		T14	2
valid_sources[0x75]	11460	1			T6	1		T7	2		T12	2
valid_sources[0x76]	10865	1			T4	1		T6	1		T7	3
valid_sources[0x77]	6673	1			T10	1		T12	1		T14	4
valid_sources[0x78]	8308	1			T12	1		T60	1		T16	30
valid_sources[0x79]	9467	1			T4	2		T7	2		T10	2
valid_sources[0x7a]	22695	1			T8	3		T12	1		T60	1
valid_sources[0x7b]	6863	1			T4	1		T6	1		T8	1
valid_sources[0x7c]	6270	1			T7	1		T8	1		T12	4
valid_sources[0x7d]	6917	1			T2	1		T8	2		T69	2
valid_sources[0x7e]	6532	1			T6	2		T12	4		T13	1
valid_sources[0x7f]	12371	1			T4	1		T12	3		T60	3
valid_sources[0x80]	6444	1			T8	1		T12	1		T60	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

981749

1

T1

1

T3

1

T4

43

values[0x0]

all_enables

biggest_size

75736

1

T1

1

T2

2

T3

4

values[0x1]

all_enables

biggest_size

55075

1

T3

1

T4

6

T5

17