Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26877	1			T16	9		T17	14		T18	10
auto[PWRUP]	84	1			T76	2		T73	1		T219	2
auto[ONEST_0]	57	1			T73	1		T77	1		T219	2
auto[ONEST_021]	16	1			T76	1		T75	1		T212	2
auto[ONEST_1]	75	1			T76	1		T73	1		T77	1
auto[ONEST_DONE]	5	1			T76	2		T220	1		T221	1
auto[LP_0]	108	1			T32	1		T76	4		T73	3
auto[LP_021]	17	1			T73	1		T214	1		T222	1
auto[LP_1]	139	1			T76	1		T73	1		T77	2
auto[LP_EVAL]	47	1			T32	1		T76	1		T74	1
auto[LP_SLP]	440	1			T76	5		T73	5		T77	4
auto[LP_PWRUP]	24	1			T76	1		T74	1		T223	1
auto[NP_0]	138	1			T76	2		T73	1		T77	1
auto[NP_021]	35	1			T76	1		T73	1		T77	1
auto[NP_1]	122	1			T32	1		T76	1		T73	2
auto[NP_EVAL]	36	1			T73	1		T77	1		T219	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T224

1

T225

1

T78

1

min

26431

1

T16

9

T17

14

T18

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26434	1			T16	9		T17	14		T18	10
pow[0x1]	3	1			T73	1		T226	1		T227	1
pow[0x2]	14	1			T76	1		T219	2		T74	1
pow[0x3]	31	1			T76	1		T219	1		T228	1
pow[0x4]	57	1			T73	2		T219	1		T195	1
pow[0x5]	96	1			T76	3		T73	1		T77	2
pow[0x6]	217	1			T76	5		T73	4		T77	3
pow[0x7]	440	1			T32	3		T76	6		T73	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

171

1

T76

2

T73

4

T77

1

min

26019

1

T16

9

T17

14

T18

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26020	1			T16	9		T17	14		T18	10
pow[0x4]	2	1			T73	1		T222	1		-	-
pow[0x5]	1	1			T229	1		-	-		-	-
pow[0x7]	2	1			T230	1		T231	1		-	-
pow[0x8]	5	1			T104	1		T232	1		T233	2
pow[0x9]	8	1			T74	1		T234	1		T225	1
pow[0xa]	16	1			T76	1		T74	1		T235	1
pow[0xb]	36	1			T76	1		T73	1		T219	1
pow[0xc]	72	1			T32	1		T76	2		T73	1
pow[0xd]	107	1			T76	1		T73	1		T219	6
pow[0xe]	271	1			T76	5		T73	6		T77	5
pow[0xf]	536	1			T32	2		T76	6		T73	10