Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2041	1			T6	5		T24	20		T26	10
auto[PWRUP]	115	1			T14	1		T15	1		T76	2
auto[ONEST_0]	83	1			T12	1		T76	1		T73	1
auto[ONEST_021]	15	1			T76	2		T77	1		T74	1
auto[ONEST_1]	87	1			T60	1		T19	1		T76	2
auto[ONEST_DONE]	2	1			T222	1		T387	1		-	-
auto[LP_0]	109	1			T12	1		T73	1		T77	2
auto[LP_021]	20	1			T73	1		T74	1		T75	1
auto[LP_1]	131	1			T14	2		T76	3		T73	2
auto[LP_EVAL]	54	1			T60	1		T15	2		T76	2
auto[LP_SLP]	464	1			T60	1		T14	1		T19	1
auto[LP_PWRUP]	19	1			T77	2		T75	1		T223	1
auto[NP_0]	160	1			T6	1		T12	1		T14	2
auto[NP_021]	36	1			T76	1		T77	1		T219	2
auto[NP_1]	161	1			T6	1		T12	1		T14	1
auto[NP_EVAL]	21	1			T62	1		T76	1		T74	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T388

1

T79

1

T227

1

min

1716

1

T6

7

T24

20

T26

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1726	1			T6	7		T24	20		T26	10
pow[0x1]	6	1			T389	1		T390	1		T391	1
pow[0x2]	15	1			T76	1		T75	2		T234	1
pow[0x3]	29	1			T73	1		T77	1		T219	1
pow[0x4]	54	1			T32	2		T76	2		T73	2
pow[0x5]	122	1			T73	1		T77	1		T64	1
pow[0x6]	219	1			T76	3		T73	2		T77	2
pow[0x7]	456	1			T15	2		T76	9		T73	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

186

1

T76

3

T73

3

T77

7

min

1237

1

T6

7

T24

20

T26

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1241	1			T6	7		T24	20		T26	10
pow[0x1]	10	1			T14	1		T62	2		T64	1
pow[0x2]	10	1			T270	1		T311	1		T35	1
pow[0x3]	27	1			T146	1		T171	1		T270	1
pow[0x4]	8	1			T15	1		T19	1		T197	1
pow[0x6]	1	1			T164	1		-	-		-	-
pow[0x7]	1	1			T235	1		-	-		-	-
pow[0x8]	4	1			T235	1		T392	1		T227	2
pow[0x9]	11	1			T74	1		T222	1		T390	1
pow[0xa]	27	1			T73	2		T77	1		T74	1
pow[0xb]	34	1			T73	2		T77	1		T195	1
pow[0xc]	66	1			T74	1		T195	2		T223	2
pow[0xd]	129	1			T15	1		T76	2		T73	1
pow[0xe]	256	1			T60	1		T15	1		T32	1
pow[0xf]	468	1			T76	8		T73	5		T77	10