Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	31715451	31643906	0	0
FsmStateHwReset_A	1002	1002	0	0
FsmStateSwReset_A	31715451	6394	0	0
LpSampleCntHwReset_A	1002	1002	0	0
LpSampleCntSwReset_A	31715451	6394	0	0
NpSampleCntHwReset_A	1002	1002	0	0
NpSampleCntSwReset_A	31715451	6394	0	0
PwrupTimerCntHwReset_A	1002	1002	0	0
PwrupTimerCntSwReset_A	31715451	6394	0	0
WakeupTimerCntHwReset_A	1002	1002	0	0
WakeupTimerCntSwReset_A	31715451	6394	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31715451	31643906	0	0
T1	77	1	0	0
T2	75	1	0	0
T3	86	1	0	0
T4	1176	1109	0	0
T5	691	631	0	0
T6	87	1	0	0
T7	1185	1113	0	0
T8	1232	1142	0	0
T9	721	667	0	0
T24	84	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T24	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31715451	6394	0	0
T16	32741	9	0	0
T17	64651	14	0	0
T18	33209	10	0	0
T19	8233	0	0	0
T20	0	22	0	0
T21	0	10	0	0
T22	0	6	0	0
T23	0	6	0	0
T27	6858	0	0	0
T28	4465	0	0	0
T29	5724	0	0	0
T30	611	0	0	0
T31	57	0	0	0
T67	0	23	0	0
T68	0	13	0	0
T96	0	10	0	0
T97	17468	0	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T24	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31715451	6394	0	0
T16	32741	9	0	0
T17	64651	14	0	0
T18	33209	10	0	0
T19	8233	0	0	0
T20	0	22	0	0
T21	0	10	0	0
T22	0	6	0	0
T23	0	6	0	0
T27	6858	0	0	0
T28	4465	0	0	0
T29	5724	0	0	0
T30	611	0	0	0
T31	57	0	0	0
T67	0	23	0	0
T68	0	13	0	0
T96	0	10	0	0
T97	17468	0	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T24	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31715451	6394	0	0
T16	32741	9	0	0
T17	64651	14	0	0
T18	33209	10	0	0
T19	8233	0	0	0
T20	0	22	0	0
T21	0	10	0	0
T22	0	6	0	0
T23	0	6	0	0
T27	6858	0	0	0
T28	4465	0	0	0
T29	5724	0	0	0
T30	611	0	0	0
T31	57	0	0	0
T67	0	23	0	0
T68	0	13	0	0
T96	0	10	0	0
T97	17468	0	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T24	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31715451	6394	0	0
T16	32741	9	0	0
T17	64651	14	0	0
T18	33209	10	0	0
T19	8233	0	0	0
T20	0	22	0	0
T21	0	10	0	0
T22	0	6	0	0
T23	0	6	0	0
T27	6858	0	0	0
T28	4465	0	0	0
T29	5724	0	0	0
T30	611	0	0	0
T31	57	0	0	0
T67	0	23	0	0
T68	0	13	0	0
T96	0	10	0	0
T97	17468	0	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T24	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31715451	6394	0	0
T16	32741	9	0	0
T17	64651	14	0	0
T18	33209	10	0	0
T19	8233	0	0	0
T20	0	22	0	0
T21	0	10	0	0
T22	0	6	0	0
T23	0	6	0	0
T27	6858	0	0	0
T28	4465	0	0	0
T29	5724	0	0	0
T30	611	0	0	0
T31	57	0	0	0
T67	0	23	0	0
T68	0	13	0	0
T96	0	10	0	0
T97	17468	0	0	0