Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	317600	0	0
SrcPulseCheck_M	2147483647	321013	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	317600
T4	224886	102
T5	693015	64
T6	3011296	72
T7	10266717	102
T8	5351392	102
T9	987119	59
T10	2612815	102
T11	1304331	49
T12	5915440	62
T13	0	92
T14	593172	68
T15	500053	44
T16	818564	34
T17	193955	68
T18	0	34
T19	0	32
T20	0	102
T21	0	30
T22	0	2
T24	3679018	0
T25	191293	0
T26	1387184	0
T27	168061	0
T28	223323	0
T29	269102	0
T60	250332	6
T61	276163	0
T69	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	321013
T4	114207	102
T5	347544	64
T6	2846689	72
T7	9698648	102
T8	5056488	102
T9	933681	59
T10	2469990	102
T11	1233029	49
T12	5915440	62
T13	0	92
T14	1185	68
T15	1599	44
T16	32741	34
T17	64651	68
T18	0	34
T19	0	32
T20	0	102
T21	0	30
T22	0	2
T24	3477782	0
T25	180827	0
T26	1387184	0
T27	6858	0
T28	4465	0
T29	5724	0
T60	2001	6
T61	1126	0
T69	0	20

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	5	2	40.00
Logical	5	2	40.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Excluded		VC_COV_UNR
1	1	Unreachable

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Percent
Assertions	2	2	100.00	0.00
Cover properties	0	0
Cover sequences	0	0
Total	2	2	100.00	0.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	0	0	0
SrcPulseCheck_M	2147483647	0	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33407435	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	5	2	40.00
Logical	5	2	40.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Excluded		VC_COV_UNR
1	1	Unreachable

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Percent
Assertions	2	2	100.00	0.00
Cover properties	0	0
Cover sequences	0	0
Total	2	2	100.00	0.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	0	0	0
SrcPulseCheck_M	2147483647	0	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33407435	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	6	75.00
Logical	8	6	75.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T6,T12,T60
1	1	Not Covered

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Not Covered
1	1	Covered	T6,T12,T60

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	87	0	0
SrcPulseCheck_M	2147483647	365	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	87
T6	1382	1
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	1
T15	0	1
T19	0	1
T24	1622	0
T25	83	0
T26	901	0
T32	0	1
T60	0	1
T62	0	1
T63	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	365
T6	165989	5
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	9
T14	0	9
T15	0	9
T19	0	5
T24	202858	0
T25	10549	0
T26	85798	0
T32	0	5
T60	0	4
T62	0	10
T63	0	5
T64	0	5

Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	32654	0	0
SrcPulseCheck_M	2147483647	32838	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	32654
T4	1176	41
T5	691	29
T6	1382	4
T7	1185	41
T8	1232	41
T9	721	27
T10	1199	41
T11	597	23
T12	0	12
T13	0	41
T24	1622	0
T25	83	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	32838
T4	111855	41
T5	346162	29
T6	165989	4
T7	569254	41
T8	296136	41
T9	54159	27
T10	144024	41
T11	71899	23
T12	0	12
T13	0	41
T24	202858	0
T25	10549	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	32778	0	0
SrcPulseCheck_M	33407435	32794	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	32778
T4	111855	41
T5	346162	29
T6	165989	4
T7	569254	41
T8	296136	41
T9	54159	27
T10	144024	41
T11	71899	23
T12	0	12
T13	0	41
T24	202858	0
T25	10549	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	32794
T4	1176	41
T5	691	29
T6	1382	4
T7	1185	41
T8	1232	41
T9	721	27
T10	1199	41
T11	597	23
T12	0	12
T13	0	41
T24	1622	0
T25	83	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T9
1	1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	15693	0	0
SrcPulseCheck_M	2147483647	15827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	15693
T4	1176	1
T5	691	14
T6	1382	4
T7	1185	1
T8	1232	1
T9	721	13
T10	1199	1
T11	597	11
T12	0	6
T13	0	20
T24	1622	0
T25	83	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	15827
T4	111855	1
T5	346162	14
T6	165989	4
T7	569254	1
T8	296136	1
T9	54159	13
T10	144024	1
T11	71899	11
T12	0	6
T13	0	20
T24	202858	0
T25	10549	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T9
1	1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	15814	0	0
SrcPulseCheck_M	33407435	15814	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	15814
T4	111855	1
T5	346162	14
T6	165989	4
T7	569254	1
T8	296136	1
T9	54159	13
T10	144024	1
T11	71899	11
T12	0	6
T13	0	20
T24	202858	0
T25	10549	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	15814
T4	1176	1
T5	691	14
T6	1382	4
T7	1185	1
T8	1232	1
T9	721	13
T10	1199	1
T11	597	11
T12	0	6
T13	0	20
T24	1622	0
T25	83	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T60,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T17,T20
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	12601	0	0
SrcPulseCheck_M	2147483647	12776	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	12601
T1	82	1
T2	80	1
T3	90	1
T4	1176	0
T5	691	0
T6	1382	3
T7	1185	0
T8	1232	0
T9	721	0
T12	0	4
T24	1622	1
T25	0	1
T26	0	1
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	12776
T1	17101	1
T2	18359	1
T3	42897	1
T4	111855	0
T5	346162	0
T6	165989	3
T7	569254	0
T8	296136	0
T9	54159	0
T12	0	4
T24	202858	1
T25	0	1
T26	0	1
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T60,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T17,T20
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	12733	0	0
SrcPulseCheck_M	33407435	12733	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	12733
T1	17101	1
T2	18359	1
T3	42897	1
T4	111855	0
T5	346162	0
T6	165989	3
T7	569254	0
T8	296136	0
T9	54159	0
T12	0	4
T24	202858	1
T25	0	1
T26	0	1
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	12733
T1	82	1
T2	80	1
T3	90	1
T4	1176	0
T5	691	0
T6	1382	3
T7	1185	0
T8	1232	0
T9	721	0
T12	0	4
T24	1622	1
T25	0	1
T26	0	1
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T60,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T17,T20
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	12633	0	0
SrcPulseCheck_M	2147483647	12801	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	12633
T1	82	1
T2	80	1
T3	90	1
T4	1176	0
T5	691	0
T6	1382	3
T7	1185	0
T8	1232	0
T9	721	0
T12	0	4
T24	1622	1
T25	0	1
T26	0	1
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	12801
T1	17101	1
T2	18359	1
T3	42897	1
T4	111855	0
T5	346162	0
T6	165989	3
T7	569254	0
T8	296136	0
T9	54159	0
T12	0	4
T24	202858	1
T25	0	1
T26	0	1
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T60,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T17,T20
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	12760	0	0
SrcPulseCheck_M	33407435	12760	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	12760
T1	17101	1
T2	18359	1
T3	42897	1
T4	111855	0
T5	346162	0
T6	165989	3
T7	569254	0
T8	296136	0
T9	54159	0
T12	0	4
T24	202858	1
T25	0	1
T26	0	1
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	12760
T1	82	1
T2	80	1
T3	90	1
T4	1176	0
T5	691	0
T6	1382	3
T7	1185	0
T8	1232	0
T9	721	0
T12	0	4
T24	1622	1
T25	0	1
T26	0	1
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T16,T17
1	0	Covered	T60,T16,T17
1	1	Covered	T60,T16,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T16,T17
1	0	Covered	T60,T16,T17
1	1	Covered	T60,T16,T17

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	17768	0	0
SrcPulseCheck_M	2147483647	17900	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	17768
T14	1185	0
T15	1599	0
T16	32741	2
T17	64651	4
T18	33209	2
T20	0	6
T21	0	2
T22	0	2
T23	0	2
T27	6858	0
T28	4465	0
T29	5724	0
T60	2001	2
T61	1126	0
T67	0	6
T68	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	17900
T14	593172	0
T15	500053	0
T16	818564	2
T17	193955	4
T18	231523	2
T20	0	6
T21	0	2
T22	0	2
T23	0	2
T27	168061	0
T28	223323	0
T29	269102	0
T60	250332	2
T61	276163	0
T67	0	6
T68	0	4

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T16,T17
1	0	Covered	T60,T16,T17
1	1	Covered	T60,T16,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T16,T17
1	0	Covered	T60,T16,T17
1	1	Covered	T60,T16,T17

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	17890	0	0
SrcPulseCheck_M	33407435	17890	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	17890
T14	593172	0
T15	500053	0
T16	818564	2
T17	193955	4
T18	231523	2
T20	0	6
T21	0	2
T22	0	2
T23	0	2
T27	168061	0
T28	223323	0
T29	269102	0
T60	250332	2
T61	276163	0
T67	0	6
T68	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	17890
T14	1185	0
T15	1599	0
T16	32741	2
T17	64651	4
T18	33209	2
T20	0	6
T21	0	2
T22	0	2
T23	0	2
T27	6858	0
T28	4465	0
T29	5724	0
T60	2001	2
T61	1126	0
T67	0	6
T68	0	4

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T6,T12,T60
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T60

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1919	0	0
SrcPulseCheck_M	2147483647	2048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1919
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	2
T14	0	3
T15	0	4
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T24	1622	0
T25	83	0
T26	901	0
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	2048
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	2
T14	0	3
T15	0	4
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T24	202858	0
T25	10549	0
T26	85798	0
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T6,T12,T60
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T60

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	2038	0	0
SrcPulseCheck_M	33407435	2038	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	2038
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	2
T14	0	3
T15	0	4
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T24	202858	0
T25	10549	0
T26	85798	0
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	2038
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	2
T14	0	3
T15	0	4
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T24	1622	0
T25	83	0
T26	901	0
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1800	0	0
SrcPulseCheck_M	2147483647	1930	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1800
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1930
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1918	0	0
SrcPulseCheck_M	33407435	1918	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1918
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1918
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1811	0	0
SrcPulseCheck_M	2147483647	1941	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1811
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1941
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1931	0	0
SrcPulseCheck_M	33407435	1931	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1931
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1931
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1820	0	0
SrcPulseCheck_M	2147483647	1946	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1820
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1946
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1938	0	0
SrcPulseCheck_M	33407435	1938	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1938
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1938
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1792	0	0
SrcPulseCheck_M	2147483647	1920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1792
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1920
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1910	0	0
SrcPulseCheck_M	33407435	1910	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1910
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1910
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1831	0	0
SrcPulseCheck_M	2147483647	1963	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1831
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1963
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1953	0	0
SrcPulseCheck_M	33407435	1953	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1953
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1953
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1805	0	0
SrcPulseCheck_M	2147483647	1935	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1805
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1935
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1926	0	0
SrcPulseCheck_M	33407435	1926	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1926
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1926
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1796	0	0
SrcPulseCheck_M	2147483647	1923	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1796
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1923
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1913	0	0
SrcPulseCheck_M	33407435	1913	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1913
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1913
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T6,T12,T60
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T60

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1925	0	0
SrcPulseCheck_M	2147483647	2050	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1925
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	2
T14	0	3
T15	0	4
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T24	1622	0
T25	83	0
T26	901	0
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	2050
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	2
T14	0	3
T15	0	4
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T24	202858	0
T25	10549	0
T26	85798	0
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T6,T12,T60
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T60
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T60

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	2040	0	0
SrcPulseCheck_M	33407435	2040	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	2040
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	2
T14	0	3
T15	0	4
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T24	202858	0
T25	10549	0
T26	85798	0
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	2040
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	2
T14	0	3
T15	0	4
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T24	1622	0
T25	83	0
T26	901	0
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1817	0	0
SrcPulseCheck_M	2147483647	1946	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1817
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1946
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1936	0	0
SrcPulseCheck_M	33407435	1936	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1936
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1936
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1801	0	0
SrcPulseCheck_M	2147483647	1930	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1801
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1930
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1921	0	0
SrcPulseCheck_M	33407435	1921	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1921
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1921
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1819	0	0
SrcPulseCheck_M	2147483647	1950	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1819
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1950
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1939	0	0
SrcPulseCheck_M	33407435	1939	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1939
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1939
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1850	0	0
SrcPulseCheck_M	2147483647	1976	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1850
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1976
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1967	0	0
SrcPulseCheck_M	33407435	1967	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1967
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1967
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1813	0	0
SrcPulseCheck_M	2147483647	1941	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1813
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1941
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1931	0	0
SrcPulseCheck_M	33407435	1931	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1931
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1931
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1849	0	0
SrcPulseCheck_M	2147483647	1979	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1849
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1979
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1971	0	0
SrcPulseCheck_M	33407435	1971	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1971
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1971
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1797	0	0
SrcPulseCheck_M	2147483647	1929	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1797
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1929
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14
1	1	Covered	T17,T20,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T17,T20,T68
1	1	Covered	T6,T12,T14

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1920	0	0
SrcPulseCheck_M	33407435	1920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1920
T6	165989	2
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	202858	0
T25	10549	0
T26	85798	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1920
T6	1382	2
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	1
T14	0	2
T15	0	1
T16	0	1
T17	0	2
T18	0	1
T19	0	1
T20	0	3
T21	0	1
T24	1622	0
T25	83	0
T26	901	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T68,T84,T42

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T15
1	0	Covered	T68,T84,T42
1	1	Covered	T12,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	1304	0	0
SrcPulseCheck_M	2147483647	1435	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	1304
T12	751	1
T13	1134	0
T14	0	1
T15	0	1
T18	0	1
T19	0	1
T21	0	1
T22	0	1
T23	0	1
T60	2001	0
T61	1126	0
T65	1614	0
T66	1601	0
T67	0	2
T68	0	2
T69	1205	0
T70	934	0
T71	80	0
T72	1607	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1435
T12	368964	1
T13	539289	0
T14	0	1
T15	0	1
T18	0	1
T19	0	1
T21	0	1
T22	0	1
T23	0	1
T60	250332	0
T61	276163	0
T65	710881	0
T66	792944	0
T67	0	2
T68	0	2
T69	223147	0
T70	37454	0
T71	13928	0
T72	176951	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T68,T84,T42

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T15
1	0	Covered	T68,T84,T42
1	1	Covered	T12,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1426	0	0
SrcPulseCheck_M	33407435	1426	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1426
T12	368964	1
T13	539289	0
T14	0	1
T15	0	1
T18	0	1
T19	0	1
T21	0	1
T22	0	1
T23	0	1
T60	250332	0
T61	276163	0
T65	710881	0
T66	792944	0
T67	0	2
T68	0	2
T69	223147	0
T70	37454	0
T71	13928	0
T72	176951	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33407435	1426
T12	751	1
T13	1134	0
T14	0	1
T15	0	1
T18	0	1
T19	0	1
T21	0	1
T22	0	1
T23	0	1
T60	2001	0
T61	1126	0
T65	1614	0
T66	1601	0
T67	0	2
T68	0	2
T69	1205	0
T70	934	0
T71	80	0
T72	1607	0

Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T16
1	0	Covered	T6,T14,T16
1	1	Covered	T6,T16,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T16
1	0	Covered	T6,T16,T17
1	1	Covered	T6,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33407435	65791	0	0
SrcPulseCheck_M	2147483647	65923	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33407435	65791
T6	1382	3
T7	1185	0
T8	1232	0
T9	721	0
T10	1199	0
T11	597	0
T12	751	0
T16	0	65
T17	0	181
T18	0	80
T19	0	2
T20	0	225
T21	0	82
T22	0	73
T23	0	83
T24	1622	0
T25	83	0
T26	901	0
T67	0	238

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	65923
T6	165989	3
T7	569254	0
T8	296136	0
T9	54159	0
T10	144024	0
T11	71899	0
T12	368964	0
T14	0	1
T16	0	65
T17	0	181
T18	0	80
T19	0	2
T20	0	225
T21	0	82
T22	0	73
T23	0	83
T24	202858	0
T25	10549	0
T26	85798	0

Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T1 T2 T3 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	5271	0	0
SrcPulseCheck_M	33317119	5272	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	5271
T4	111855	20
T5	346162	6
T6	165989	0
T7	569254	20
T8	296136	20
T9	54159	5
T10	144024	20
T11	71899	3
T12	0	2
T13	0	10
T24	202858	0
T25	10549	0
T69	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33317119	5272
T4	1176	20
T5	691	6
T6	1382	0
T7	1185	20
T8	1232	20
T9	721	5
T10	1199	20
T11	597	3
T12	0	2
T13	0	10
T24	1622	0
T25	83	0
T69	0	20

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.12	85.71			83.33	50.00	u_adc_chn_val_0_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.12	85.71			83.33	50.00	u_adc_chn_val_1_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_adc_fsm_state_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_adc_en_ctl_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_adc_pd_ctl_cdc