Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1434	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1513	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1440	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1326	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1391	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1418	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1570	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1526	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1534	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1374	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1451	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1425	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1467	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1494	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1545	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1574	0	0
adc_en_ctl_rd_A	2147483647	1170	0	0
adc_fsm_rst_rd_A	2147483647	990	0	0
adc_intr_ctl_rd_A	2147483647	1588	0	0
adc_lp_sample_ctl_rd_A	2147483647	974	0	0
adc_pd_ctl_rd_A	2147483647	1360	0	0
adc_sample_ctl_rd_A	2147483647	961	0	0
adc_wakeup_ctl_rd_A	2147483647	1141	0	0
intr_enable_rd_A	2147483647	1351	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1434	0	0
T32	125504	10	0	0
T33	0	15	0	0
T34	0	17	0	0
T35	0	18	0	0
T36	0	17	0	0
T37	0	28	0	0
T38	0	45	0	0
T39	0	23	0	0
T40	0	6	0	0
T41	0	18	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513	0	0
T32	125504	18	0	0
T33	0	25	0	0
T34	0	29	0	0
T35	0	7	0	0
T36	0	18	0	0
T37	0	34	0	0
T38	0	36	0	0
T39	0	24	0	0
T40	0	8	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	10	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1440	0	0
T32	125504	12	0	0
T33	0	11	0	0
T34	0	12	0	0
T35	0	11	0	0
T36	0	25	0	0
T37	0	22	0	0
T38	0	46	0	0
T39	0	16	0	0
T40	0	3	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	2	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1326	0	0
T32	125504	13	0	0
T33	0	9	0	0
T34	0	25	0	0
T35	0	16	0	0
T36	0	19	0	0
T37	0	26	0	0
T38	0	32	0	0
T39	0	3	0	0
T40	0	7	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	5	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1391	0	0
T32	125504	19	0	0
T33	0	4	0	0
T34	0	22	0	0
T35	0	17	0	0
T36	0	12	0	0
T37	0	32	0	0
T38	0	54	0	0
T39	0	32	0	0
T40	0	5	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	7	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1418	0	0
T32	125504	12	0	0
T33	0	9	0	0
T34	0	13	0	0
T35	0	3	0	0
T36	0	14	0	0
T37	0	37	0	0
T38	0	30	0	0
T39	0	23	0	0
T40	0	3	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	6	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1570	0	0
T32	125504	31	0	0
T33	0	13	0	0
T34	0	25	0	0
T35	0	23	0	0
T36	0	20	0	0
T37	0	39	0	0
T38	0	47	0	0
T39	0	19	0	0
T40	0	9	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	16	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1526	0	0
T32	125504	22	0	0
T33	0	21	0	0
T34	0	16	0	0
T35	0	10	0	0
T36	0	23	0	0
T37	0	46	0	0
T38	0	39	0	0
T39	0	27	0	0
T40	0	13	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	5	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1534	0	0
T32	125504	13	0	0
T33	0	9	0	0
T34	0	18	0	0
T35	0	13	0	0
T36	0	16	0	0
T37	0	42	0	0
T38	0	37	0	0
T39	0	28	0	0
T40	0	13	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	22	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1374	0	0
T32	125504	19	0	0
T33	0	22	0	0
T34	0	18	0	0
T35	0	33	0	0
T36	0	20	0	0
T37	0	32	0	0
T38	0	24	0	0
T39	0	14	0	0
T40	0	4	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	15	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1451	0	0
T32	125504	25	0	0
T33	0	15	0	0
T34	0	28	0	0
T35	0	6	0	0
T36	0	14	0	0
T37	0	16	0	0
T38	0	42	0	0
T39	0	42	0	0
T40	0	11	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	17	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1425	0	0
T32	125504	17	0	0
T33	0	22	0	0
T34	0	21	0	0
T35	0	8	0	0
T36	0	20	0	0
T37	0	42	0	0
T38	0	32	0	0
T39	0	6	0	0
T41	0	23	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	8	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1467	0	0
T32	125504	16	0	0
T33	0	20	0	0
T34	0	9	0	0
T35	0	17	0	0
T36	0	18	0	0
T37	0	32	0	0
T38	0	36	0	0
T39	0	39	0	0
T40	0	2	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	21	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1494	0	0
T32	125504	34	0	0
T33	0	19	0	0
T34	0	24	0	0
T35	0	11	0	0
T36	0	29	0	0
T37	0	19	0	0
T38	0	37	0	0
T39	0	11	0	0
T40	0	12	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	7	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1545	0	0
T32	125504	25	0	0
T33	0	15	0	0
T34	0	16	0	0
T35	0	6	0	0
T36	0	16	0	0
T37	0	51	0	0
T38	0	53	0	0
T39	0	27	0	0
T40	0	12	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	5	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1574	0	0
T32	125504	13	0	0
T33	0	23	0	0
T34	0	6	0	0
T35	0	14	0	0
T36	0	15	0	0
T37	0	44	0	0
T38	0	35	0	0
T39	0	17	0	0
T40	0	9	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	15	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1170	0	0
T32	125504	19	0	0
T33	0	17	0	0
T34	0	14	0	0
T35	0	14	0	0
T36	0	9	0	0
T37	0	55	0	0
T38	0	44	0	0
T39	0	14	0	0
T40	0	13	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	8	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	990	0	0
T32	125504	20	0	0
T33	0	17	0	0
T34	0	17	0	0
T35	0	8	0	0
T36	0	13	0	0
T37	0	34	0	0
T38	0	37	0	0
T39	0	9	0	0
T40	0	11	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	19	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T32	125504	20	0	0
T33	0	25	0	0
T34	0	6	0	0
T35	0	15	0	0
T36	0	18	0	0
T37	0	38	0	0
T38	0	39	0	0
T39	0	20	0	0
T40	0	3	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	16	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	974	0	0
T32	125504	10	0	0
T33	0	9	0	0
T34	0	25	0	0
T35	0	8	0	0
T36	0	22	0	0
T37	0	37	0	0
T38	0	42	0	0
T39	0	12	0	0
T40	0	8	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	10	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1360	0	0
T32	125504	16	0	0
T33	0	18	0	0
T34	0	32	0	0
T35	0	6	0	0
T36	0	15	0	0
T37	0	44	0	0
T38	0	24	0	0
T39	0	16	0	0
T40	0	14	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	16	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	961	0	0
T32	125504	17	0	0
T33	0	10	0	0
T34	0	17	0	0
T35	0	9	0	0
T36	0	15	0	0
T37	0	39	0	0
T38	0	52	0	0
T39	0	9	0	0
T40	0	10	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	4	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1141	0	0
T32	125504	26	0	0
T33	0	16	0	0
T34	0	16	0	0
T35	0	12	0	0
T36	0	19	0	0
T37	0	49	0	0
T38	0	42	0	0
T39	0	26	0	0
T40	0	13	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T44	615210	0	0	0
T45	122170	0	0	0
T46	187507	0	0	0
T47	407227	0	0	0
T48	283547	0	0	0
T49	152693	0	0	0
T50	145146	0	0	0
T51	0	28	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1351	0	0
T32	125504	11	0	0
T33	0	16	0	0
T34	0	18	0	0
T35	0	31	0	0
T36	0	23	0	0
T37	0	53	0	0
T38	0	37	0	0
T42	127263	0	0	0
T43	49969	0	0	0
T51	0	8	0	0
T52	808882	7	0	0
T53	0	13	0	0
T54	881978	0	0	0
T55	363280	0	0	0
T56	128659	0	0	0
T57	322573	0	0	0
T58	182297	0	0	0
T59	230294	0	0	0