Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.24

Total test records in report: 920

T276	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.1510954754	Aug 27 06:35:53 AM UTC 24	Aug 27 07:01:52 AM UTC 24	480511577368 ps
T798	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.3162272069	Aug 27 06:41:31 AM UTC 24	Aug 27 07:03:32 AM UTC 24	489358422979 ps
T314	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.2600261502	Aug 27 06:40:27 AM UTC 24	Aug 27 07:03:55 AM UTC 24	495728619769 ps
T298	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1357963690	Aug 27 06:42:34 AM UTC 24	Aug 27 07:25:22 AM UTC 24	591004540412 ps
T799	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.968609898	Aug 27 06:15:38 AM UTC 24	Aug 27 07:40:41 AM UTC 24	1679619361670 ps
T89	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3048921228	Aug 27 04:31:50 AM UTC 24	Aug 27 04:31:56 AM UTC 24	391697211 ps
T800	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.3990166954	Aug 27 04:32:02 AM UTC 24	Aug 27 04:32:05 AM UTC 24	446628278 ps
T113	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2028292531	Aug 27 04:32:06 AM UTC 24	Aug 27 04:32:13 AM UTC 24	940882802 ps
T114	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1934634351	Aug 27 04:32:12 AM UTC 24	Aug 27 04:32:15 AM UTC 24	571575667 ps
T115	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3776290357	Aug 27 04:32:15 AM UTC 24	Aug 27 04:32:21 AM UTC 24	1216725194 ps
T98	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.124662633	Aug 27 04:32:33 AM UTC 24	Aug 27 04:32:38 AM UTC 24	581236272 ps
T90	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.451803278	Aug 27 04:32:35 AM UTC 24	Aug 27 04:32:40 AM UTC 24	405721679 ps
T81	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.669806207	Aug 27 04:32:21 AM UTC 24	Aug 27 04:32:41 AM UTC 24	3957051973 ps
T85	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3670847757	Aug 27 04:31:57 AM UTC 24	Aug 27 04:32:42 AM UTC 24	8195057669 ps
T801	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2396526676	Aug 27 04:32:41 AM UTC 24	Aug 27 04:32:43 AM UTC 24	426087435 ps
T129	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1967916035	Aug 27 04:32:43 AM UTC 24	Aug 27 04:32:46 AM UTC 24	613540850 ps
T116	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2182857008	Aug 27 04:32:42 AM UTC 24	Aug 27 04:32:46 AM UTC 24	685127730 ps
T99	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.451056399	Aug 27 04:32:46 AM UTC 24	Aug 27 04:32:49 AM UTC 24	419991766 ps
T802	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1420370344	Aug 27 04:32:48 AM UTC 24	Aug 27 04:32:50 AM UTC 24	468739509 ps
T135	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2722066181	Aug 27 04:32:45 AM UTC 24	Aug 27 04:32:50 AM UTC 24	938134685 ps
T91	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1348096672	Aug 27 04:32:48 AM UTC 24	Aug 27 04:32:52 AM UTC 24	686785483 ps
T117	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3721109599	Aug 27 04:32:50 AM UTC 24	Aug 27 04:32:55 AM UTC 24	1146783776 ps
T118	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.156223318	Aug 27 04:32:51 AM UTC 24	Aug 27 04:32:56 AM UTC 24	523330797 ps
T82	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4070583374	Aug 27 04:32:46 AM UTC 24	Aug 27 04:32:58 AM UTC 24	4477218034 ps
T100	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1011870691	Aug 27 04:32:57 AM UTC 24	Aug 27 04:33:00 AM UTC 24	546830387 ps
T92	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2661087404	Aug 27 04:32:59 AM UTC 24	Aug 27 04:33:04 AM UTC 24	391712315 ps
T86	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2555227523	Aug 27 04:32:40 AM UTC 24	Aug 27 04:33:04 AM UTC 24	4571035016 ps
T803	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1689866653	Aug 27 04:32:53 AM UTC 24	Aug 27 04:33:06 AM UTC 24	1407295316 ps
T804	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4249879173	Aug 27 04:33:04 AM UTC 24	Aug 27 04:33:07 AM UTC 24	732587608 ps
T805	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.2014462536	Aug 27 04:33:04 AM UTC 24	Aug 27 04:33:08 AM UTC 24	340220930 ps
T130	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1545451284	Aug 27 04:33:06 AM UTC 24	Aug 27 04:33:10 AM UTC 24	509925501 ps
T87	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2369771223	Aug 27 04:33:01 AM UTC 24	Aug 27 04:33:11 AM UTC 24	5045992004 ps
T101	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2588209332	Aug 27 04:33:11 AM UTC 24	Aug 27 04:33:14 AM UTC 24	488018873 ps
T119	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.768402783	Aug 27 04:33:08 AM UTC 24	Aug 27 04:33:15 AM UTC 24	750300555 ps
T83	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4174325282	Aug 27 04:33:10 AM UTC 24	Aug 27 04:33:16 AM UTC 24	2762299695 ps
T93	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1892713314	Aug 27 04:33:13 AM UTC 24	Aug 27 04:33:16 AM UTC 24	667702390 ps
T806	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3277978640	Aug 27 04:33:16 AM UTC 24	Aug 27 04:33:18 AM UTC 24	535405331 ps
T120	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.308743871	Aug 27 04:32:44 AM UTC 24	Aug 27 04:33:19 AM UTC 24	29548410190 ps
T121	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.123368884	Aug 27 04:32:13 AM UTC 24	Aug 27 04:33:19 AM UTC 24	53574720658 ps
T383	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1194806045	Aug 27 04:33:15 AM UTC 24	Aug 27 04:33:20 AM UTC 24	4749162578 ps
T131	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3320713943	Aug 27 04:33:17 AM UTC 24	Aug 27 04:33:22 AM UTC 24	512411995 ps
T122	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.202885924	Aug 27 04:33:17 AM UTC 24	Aug 27 04:33:22 AM UTC 24	1167322717 ps
T807	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3725421758	Aug 27 04:33:21 AM UTC 24	Aug 27 04:33:24 AM UTC 24	538990717 ps
T132	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2784933175	Aug 27 04:33:20 AM UTC 24	Aug 27 04:33:25 AM UTC 24	2063536404 ps
T133	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3065195646	Aug 27 04:32:56 AM UTC 24	Aug 27 04:33:25 AM UTC 24	4713527270 ps
T94	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.608651959	Aug 27 04:33:22 AM UTC 24	Aug 27 04:33:26 AM UTC 24	494826939 ps
T808	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.3238737700	Aug 27 04:33:24 AM UTC 24	Aug 27 04:33:27 AM UTC 24	333824151 ps
T123	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.487916048	Aug 27 04:33:19 AM UTC 24	Aug 27 04:33:28 AM UTC 24	1029154596 ps
T134	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3058920777	Aug 27 04:33:25 AM UTC 24	Aug 27 04:33:28 AM UTC 24	327737907 ps
T809	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3030697295	Aug 27 04:33:25 AM UTC 24	Aug 27 04:33:29 AM UTC 24	1967433393 ps
T810	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2980375624	Aug 27 04:33:27 AM UTC 24	Aug 27 04:33:31 AM UTC 24	421816292 ps
T811	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1946180945	Aug 27 04:33:45 AM UTC 24	Aug 27 04:33:53 AM UTC 24	4449369060 ps
T812	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2611839694	Aug 27 04:33:29 AM UTC 24	Aug 27 04:33:32 AM UTC 24	551761036 ps
T813	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1166756038	Aug 27 04:33:28 AM UTC 24	Aug 27 04:33:32 AM UTC 24	381059183 ps
T814	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.2707399627	Aug 27 04:33:29 AM UTC 24	Aug 27 04:33:33 AM UTC 24	514379996 ps
T386	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2537376701	Aug 27 04:32:48 AM UTC 24	Aug 27 04:33:35 AM UTC 24	8421517167 ps
T815	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.627076187	Aug 27 04:33:32 AM UTC 24	Aug 27 04:33:35 AM UTC 24	439136002 ps
T124	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3949847863	Aug 27 04:33:33 AM UTC 24	Aug 27 04:33:36 AM UTC 24	480778160 ps
T816	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.141262388	Aug 27 04:33:32 AM UTC 24	Aug 27 04:33:36 AM UTC 24	707283668 ps
T817	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1674655125	Aug 27 04:33:33 AM UTC 24	Aug 27 04:33:37 AM UTC 24	387207594 ps
T818	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2054701782	Aug 27 04:33:36 AM UTC 24	Aug 27 04:33:41 AM UTC 24	552055107 ps
T819	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1256753199	Aug 27 04:33:36 AM UTC 24	Aug 27 04:33:41 AM UTC 24	456590723 ps
T820	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.695886477	Aug 27 04:33:38 AM UTC 24	Aug 27 04:33:42 AM UTC 24	505125879 ps
T821	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3863231545	Aug 27 04:33:30 AM UTC 24	Aug 27 04:33:44 AM UTC 24	5158215979 ps
T822	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1447995899	Aug 27 04:33:41 AM UTC 24	Aug 27 04:33:45 AM UTC 24	329210266 ps
T823	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1132537968	Aug 27 04:33:42 AM UTC 24	Aug 27 04:33:45 AM UTC 24	540757055 ps
T95	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.975571889	Aug 27 04:33:37 AM UTC 24	Aug 27 04:33:45 AM UTC 24	8805119371 ps
T824	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2502969667	Aug 27 04:33:43 AM UTC 24	Aug 27 04:33:47 AM UTC 24	684066362 ps
T825	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.268886400	Aug 27 04:33:45 AM UTC 24	Aug 27 04:33:49 AM UTC 24	392608568 ps
T384	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.421657619	Aug 27 04:33:23 AM UTC 24	Aug 27 04:33:49 AM UTC 24	4903375804 ps
T826	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3254723338	Aug 27 04:33:47 AM UTC 24	Aug 27 04:33:50 AM UTC 24	464485697 ps
T127	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4119092566	Aug 27 04:33:46 AM UTC 24	Aug 27 04:33:51 AM UTC 24	474258963 ps
T827	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.982284096	Aug 27 04:33:42 AM UTC 24	Aug 27 04:33:52 AM UTC 24	4987419060 ps
T828	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2175535618	Aug 27 04:33:50 AM UTC 24	Aug 27 04:33:53 AM UTC 24	391903619 ps
T829	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1147498146	Aug 27 04:33:49 AM UTC 24	Aug 27 04:33:54 AM UTC 24	654938827 ps
T830	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3390500091	Aug 27 04:33:52 AM UTC 24	Aug 27 04:33:55 AM UTC 24	400816754 ps
T831	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2791306452	Aug 27 04:33:35 AM UTC 24	Aug 27 04:33:55 AM UTC 24	4031939434 ps
T832	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3618585809	Aug 27 04:33:33 AM UTC 24	Aug 27 04:33:56 AM UTC 24	8563455852 ps
T833	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1328214130	Aug 27 04:33:29 AM UTC 24	Aug 27 04:33:57 AM UTC 24	4514202384 ps
T834	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2188521602	Aug 27 04:33:54 AM UTC 24	Aug 27 04:33:57 AM UTC 24	616678128 ps
T835	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3887998825	Aug 27 04:33:55 AM UTC 24	Aug 27 04:33:57 AM UTC 24	555350082 ps
T836	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3009499179	Aug 27 04:33:53 AM UTC 24	Aug 27 04:33:58 AM UTC 24	2537173999 ps
T837	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2557653401	Aug 27 04:33:56 AM UTC 24	Aug 27 04:33:58 AM UTC 24	402803391 ps
T838	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3063158369	Aug 27 04:33:56 AM UTC 24	Aug 27 04:33:59 AM UTC 24	566888472 ps
T839	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3115039170	Aug 27 04:33:58 AM UTC 24	Aug 27 04:34:01 AM UTC 24	553510751 ps
T840	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.488402925	Aug 27 04:33:58 AM UTC 24	Aug 27 04:34:02 AM UTC 24	747127092 ps
T841	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2622902348	Aug 27 04:33:58 AM UTC 24	Aug 27 04:34:02 AM UTC 24	415983189 ps
T842	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3499479025	Aug 27 04:33:55 AM UTC 24	Aug 27 04:34:02 AM UTC 24	5049625736 ps
T128	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3200254833	Aug 27 04:33:59 AM UTC 24	Aug 27 04:34:03 AM UTC 24	406005456 ps
T843	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2324379818	Aug 27 04:34:00 AM UTC 24	Aug 27 04:34:04 AM UTC 24	521152702 ps
T844	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1785326178	Aug 27 04:34:01 AM UTC 24	Aug 27 04:34:06 AM UTC 24	604970946 ps
T845	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.958104780	Aug 27 04:34:03 AM UTC 24	Aug 27 04:34:06 AM UTC 24	381314114 ps
T125	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.93446872	Aug 27 04:34:04 AM UTC 24	Aug 27 04:34:07 AM UTC 24	455826993 ps
T846	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3227561522	Aug 27 04:33:57 AM UTC 24	Aug 27 04:34:07 AM UTC 24	1873434585 ps
T847	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2908158394	Aug 27 04:33:46 AM UTC 24	Aug 27 04:34:07 AM UTC 24	4378289898 ps
T848	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3393178598	Aug 27 04:34:05 AM UTC 24	Aug 27 04:34:08 AM UTC 24	492557135 ps
T849	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2546267072	Aug 27 04:34:04 AM UTC 24	Aug 27 04:34:09 AM UTC 24	4403515954 ps
T850	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1968922441	Aug 27 04:33:07 AM UTC 24	Aug 27 04:34:10 AM UTC 24	26282009309 ps
T126	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1796548179	Aug 27 04:34:08 AM UTC 24	Aug 27 04:34:11 AM UTC 24	299773717 ps
T851	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2013424047	Aug 27 04:34:07 AM UTC 24	Aug 27 04:34:11 AM UTC 24	544397298 ps
T852	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1587557975	Aug 27 04:34:08 AM UTC 24	Aug 27 04:34:11 AM UTC 24	396812690 ps
T853	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.561856246	Aug 27 04:34:09 AM UTC 24	Aug 27 04:34:11 AM UTC 24	563907346 ps
T854	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.22923101	Aug 27 04:33:58 AM UTC 24	Aug 27 04:34:13 AM UTC 24	8823794670 ps
T855	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3892207253	Aug 27 04:34:11 AM UTC 24	Aug 27 04:34:14 AM UTC 24	566880794 ps
T856	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2199205388	Aug 27 04:34:10 AM UTC 24	Aug 27 04:34:14 AM UTC 24	476160980 ps
T857	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2701869689	Aug 27 04:34:12 AM UTC 24	Aug 27 04:34:16 AM UTC 24	335174832 ps
T858	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.321632614	Aug 27 04:34:12 AM UTC 24	Aug 27 04:34:17 AM UTC 24	462949872 ps
T859	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.787249616	Aug 27 04:34:02 AM UTC 24	Aug 27 04:34:17 AM UTC 24	4416300109 ps
T860	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3786900350	Aug 27 04:34:13 AM UTC 24	Aug 27 04:34:17 AM UTC 24	399273769 ps
T861	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.740173296	Aug 27 04:34:15 AM UTC 24	Aug 27 04:34:18 AM UTC 24	413655770 ps
T862	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2220817931	Aug 27 04:33:59 AM UTC 24	Aug 27 04:34:19 AM UTC 24	4605286295 ps
T863	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2133465570	Aug 27 04:34:17 AM UTC 24	Aug 27 04:34:19 AM UTC 24	586126070 ps
T385	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1334862077	Aug 27 04:34:11 AM UTC 24	Aug 27 04:34:21 AM UTC 24	9230868699 ps
T864	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.509507584	Aug 27 04:34:18 AM UTC 24	Aug 27 04:34:21 AM UTC 24	493501936 ps
T865	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.875120357	Aug 27 04:33:49 AM UTC 24	Aug 27 04:34:22 AM UTC 24	8034341005 ps
T866	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.3808991487	Aug 27 04:34:20 AM UTC 24	Aug 27 04:34:23 AM UTC 24	492287564 ps
T867	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.812792955	Aug 27 04:34:20 AM UTC 24	Aug 27 04:34:23 AM UTC 24	588401903 ps
T868	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1318814415	Aug 27 04:34:18 AM UTC 24	Aug 27 04:34:23 AM UTC 24	2681288469 ps
T869	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3087866610	Aug 27 04:34:12 AM UTC 24	Aug 27 04:34:23 AM UTC 24	5413915844 ps
T870	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4858481	Aug 27 04:32:51 AM UTC 24	Aug 27 04:34:24 AM UTC 24	26625304857 ps
T871	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1804104740	Aug 27 04:34:19 AM UTC 24	Aug 27 04:34:24 AM UTC 24	394390533 ps
T872	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2665923697	Aug 27 04:33:19 AM UTC 24	Aug 27 04:34:25 AM UTC 24	36812394356 ps
T873	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4139183967	Aug 27 04:34:22 AM UTC 24	Aug 27 04:34:25 AM UTC 24	645169634 ps
T874	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.821747118	Aug 27 04:34:23 AM UTC 24	Aug 27 04:34:26 AM UTC 24	512330020 ps
T875	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1005310192	Aug 27 04:34:08 AM UTC 24	Aug 27 04:34:26 AM UTC 24	4227498848 ps
T876	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2406428036	Aug 27 04:34:26 AM UTC 24	Aug 27 04:34:28 AM UTC 24	369382760 ps
T877	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4099093379	Aug 27 04:34:23 AM UTC 24	Aug 27 04:34:28 AM UTC 24	521125324 ps
T878	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1429603617	Aug 27 04:34:26 AM UTC 24	Aug 27 04:34:28 AM UTC 24	440469799 ps
T879	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4273408494	Aug 27 04:34:25 AM UTC 24	Aug 27 04:34:29 AM UTC 24	453264870 ps
T880	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2607052117	Aug 27 04:34:25 AM UTC 24	Aug 27 04:34:29 AM UTC 24	424211852 ps
T881	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2121266500	Aug 27 04:34:27 AM UTC 24	Aug 27 04:34:30 AM UTC 24	799788014 ps
T882	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1933725709	Aug 27 04:34:23 AM UTC 24	Aug 27 04:34:30 AM UTC 24	513008832 ps
T883	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2211982227	Aug 27 04:34:29 AM UTC 24	Aug 27 04:34:32 AM UTC 24	323003936 ps
T884	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2429745781	Aug 27 04:34:29 AM UTC 24	Aug 27 04:34:32 AM UTC 24	304919510 ps
T885	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3708557507	Aug 27 04:34:29 AM UTC 24	Aug 27 04:34:32 AM UTC 24	425931033 ps
T886	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.4250243699	Aug 27 04:34:29 AM UTC 24	Aug 27 04:34:32 AM UTC 24	317355937 ps
T887	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3605105939	Aug 27 04:34:30 AM UTC 24	Aug 27 04:34:33 AM UTC 24	454943346 ps
T888	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.3831404652	Aug 27 04:34:30 AM UTC 24	Aug 27 04:34:33 AM UTC 24	550414532 ps
T889	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2310119357	Aug 27 04:34:27 AM UTC 24	Aug 27 04:34:34 AM UTC 24	4730306997 ps
T890	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2319448795	Aug 27 04:34:30 AM UTC 24	Aug 27 04:34:34 AM UTC 24	466784918 ps
T891	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2491459778	Aug 27 04:34:32 AM UTC 24	Aug 27 04:34:35 AM UTC 24	479095222 ps
T892	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.272669542	Aug 27 04:34:32 AM UTC 24	Aug 27 04:34:35 AM UTC 24	438962046 ps
T893	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.1821579361	Aug 27 04:34:33 AM UTC 24	Aug 27 04:34:36 AM UTC 24	317749684 ps
T894	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2777388993	Aug 27 04:34:07 AM UTC 24	Aug 27 04:34:37 AM UTC 24	8192570438 ps
T895	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.144533576	Aug 27 04:34:32 AM UTC 24	Aug 27 04:34:37 AM UTC 24	477812160 ps
T896	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3606073079	Aug 27 04:34:35 AM UTC 24	Aug 27 04:34:37 AM UTC 24	547327658 ps
T897	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.3811348079	Aug 27 04:34:34 AM UTC 24	Aug 27 04:34:37 AM UTC 24	390699641 ps
T898	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1345569540	Aug 27 04:34:14 AM UTC 24	Aug 27 04:34:37 AM UTC 24	7846591337 ps
T899	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.4000388248	Aug 27 04:34:35 AM UTC 24	Aug 27 04:34:38 AM UTC 24	465772204 ps
T900	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2504792780	Aug 27 04:34:25 AM UTC 24	Aug 27 04:34:38 AM UTC 24	9066987593 ps
T901	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.3904480979	Aug 27 04:34:36 AM UTC 24	Aug 27 04:34:39 AM UTC 24	398461949 ps
T902	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2788855869	Aug 27 04:34:36 AM UTC 24	Aug 27 04:34:39 AM UTC 24	335177664 ps
T903	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.3809997453	Aug 27 04:34:36 AM UTC 24	Aug 27 04:34:39 AM UTC 24	278921871 ps
T904	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1496530	Aug 27 04:34:23 AM UTC 24	Aug 27 04:34:40 AM UTC 24	8665423162 ps
T905	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.554319536	Aug 27 04:34:37 AM UTC 24	Aug 27 04:34:40 AM UTC 24	484157734 ps
T906	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3452637222	Aug 27 04:34:19 AM UTC 24	Aug 27 04:34:40 AM UTC 24	8293992859 ps
T907	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.3593414557	Aug 27 04:34:38 AM UTC 24	Aug 27 04:34:41 AM UTC 24	297406013 ps
T908	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.1333603983	Aug 27 04:34:39 AM UTC 24	Aug 27 04:34:42 AM UTC 24	501686036 ps
T909	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.3182979869	Aug 27 04:34:38 AM UTC 24	Aug 27 04:34:42 AM UTC 24	392447324 ps
T910	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.1896686675	Aug 27 04:34:38 AM UTC 24	Aug 27 04:34:42 AM UTC 24	450484455 ps
T911	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.2887515549	Aug 27 04:34:39 AM UTC 24	Aug 27 04:34:42 AM UTC 24	464052866 ps
T912	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2299696145	Aug 27 04:34:38 AM UTC 24	Aug 27 04:34:42 AM UTC 24	411843534 ps
T913	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.244027565	Aug 27 04:34:39 AM UTC 24	Aug 27 04:34:43 AM UTC 24	318494717 ps
T914	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.552147713	Aug 27 04:34:40 AM UTC 24	Aug 27 04:34:43 AM UTC 24	308721903 ps
T915	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.1417589283	Aug 27 04:34:38 AM UTC 24	Aug 27 04:34:43 AM UTC 24	504479825 ps
T916	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.758241249	Aug 27 04:34:40 AM UTC 24	Aug 27 04:34:43 AM UTC 24	464022761 ps
T917	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.113890019	Aug 27 04:34:42 AM UTC 24	Aug 27 04:34:44 AM UTC 24	332344616 ps
T918	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.15693827	Aug 27 04:34:40 AM UTC 24	Aug 27 04:34:45 AM UTC 24	495895505 ps
T919	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1308269393	Aug 27 04:34:22 AM UTC 24	Aug 27 04:34:48 AM UTC 24	4760294824 ps
T920	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2570968291	Aug 27 04:34:25 AM UTC 24	Aug 27 04:34:56 AM UTC 24	4588642744 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2266214281
Short name	T6
Test name
Test status
Simulation time	6916351484 ps
CPU time	7.57 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:36:53 AM UTC 24
Peak memory	211520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2266214281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.adc_ctrl_stress_all_with_rand_reset.2266214281
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2570051787
Short name	T21
Test name
Test status
Simulation time	172578660599 ps
CPU time	102.87 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:38:40 AM UTC 24
Peak memory	211508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570051787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2570051787
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1071178268
Short name	T12
Test name
Test status
Simulation time	3764925895 ps
CPU time	10.78 seconds
Started	Aug 27 05:36:55 AM UTC 24
Finished	Aug 27 05:37:06 AM UTC 24
Peak memory	221948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1071178268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.adc_ctrl_stress_all_with_rand_reset.1071178268
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3586880544
Short name	T74
Test name
Test status
Simulation time	102333561963 ps
CPU time	542.4 seconds
Started	Aug 27 05:37:09 AM UTC 24
Finished	Aug 27 05:46:18 AM UTC 24
Peak memory	211964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586880544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3586880544
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3499118530
Short name	T20
Test name
Test status
Simulation time	487955674245 ps
CPU time	90.76 seconds
Started	Aug 27 05:36:52 AM UTC 24
Finished	Aug 27 05:38:24 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499118530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3499118530
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2103258678
Short name	T19
Test name
Test status
Simulation time	41500184890 ps
CPU time	13.17 seconds
Started	Aug 27 05:38:05 AM UTC 24
Finished	Aug 27 05:38:19 AM UTC 24
Peak memory	221620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2103258678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.adc_ctrl_stress_all_with_rand_reset.2103258678
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2540266125
Short name	T201
Test name
Test status
Simulation time	496467212296 ps
CPU time	728.78 seconds
Started	Aug 27 05:41:52 AM UTC 24
Finished	Aug 27 05:54:09 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540266125 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.2540266125
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2137136911
Short name	T67
Test name
Test status
Simulation time	497548394841 ps
CPU time	129.92 seconds
Started	Aug 27 05:36:56 AM UTC 24
Finished	Aug 27 05:39:11 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137136911 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.2137136911
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.1602827020
Short name	T248
Test name
Test status
Simulation time	496038792238 ps
CPU time	1021.78 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:54:10 AM UTC 24
Peak memory	211524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602827020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1602827020
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.421432490
Short name	T34
Test name
Test status
Simulation time	3073178051 ps
CPU time	14.06 seconds
Started	Aug 27 05:59:09 AM UTC 24
Finished	Aug 27 05:59:24 AM UTC 24
Peak memory	211336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=421432490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.421432490
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2923041608
Short name	T165
Test name
Test status
Simulation time	485112733463 ps
CPU time	208.68 seconds
Started	Aug 27 05:54:11 AM UTC 24
Finished	Aug 27 05:57:42 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923041608 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.2923041608
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.14841027
Short name	T153
Test name
Test status
Simulation time	634410557208 ps
CPU time	242.27 seconds
Started	Aug 27 05:57:34 AM UTC 24
Finished	Aug 27 06:01:39 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14841027 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.14841027
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.362734434
Short name	T9
Test name
Test status
Simulation time	3610751086 ps
CPU time	1.97 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:36:58 AM UTC 24
Peak memory	209780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362734434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.362734434
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2599435582
Short name	T80
Test name
Test status
Simulation time	21498797922 ps
CPU time	40.43 seconds
Started	Aug 27 06:41:07 AM UTC 24
Finished	Aug 27 06:41:49 AM UTC 24
Peak memory	228080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2599435582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.adc_ctrl_stress_all_with_rand_reset.2599435582
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3048921228
Short name	T89
Test name
Test status
Simulation time	391697211 ps
CPU time	4.12 seconds
Started	Aug 27 04:31:50 AM UTC 24
Finished	Aug 27 04:31:56 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048921228 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3048921228
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1262186767
Short name	T42
Test name
Test status
Simulation time	353513624186 ps
CPU time	364.24 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:42:53 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262186767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1262186767
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1945874411
Short name	T24
Test name
Test status
Simulation time	8114414039 ps
CPU time	5.71 seconds
Started	Aug 27 05:36:47 AM UTC 24
Finished	Aug 27 05:36:57 AM UTC 24
Peak memory	243620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945874411 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1945874411
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.863383353
Short name	T52
Test name
Test status
Simulation time	337486019750 ps
CPU time	211.62 seconds
Started	Aug 27 05:38:07 AM UTC 24
Finished	Aug 27 05:41:42 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863383353 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.863383353
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1822314657
Short name	T196
Test name
Test status
Simulation time	496485146082 ps
CPU time	82.21 seconds
Started	Aug 27 05:47:14 AM UTC 24
Finished	Aug 27 05:48:38 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822314657 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.1822314657
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.61706201
Short name	T84
Test name
Test status
Simulation time	385386403196 ps
CPU time	191.35 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:40:09 AM UTC 24
Peak memory	211544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61706201 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.61706201
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.3795412043
Short name	T173
Test name
Test status
Simulation time	383397610759 ps
CPU time	273.59 seconds
Started	Aug 27 05:56:05 AM UTC 24
Finished	Aug 27 06:00:42 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795412043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3795412043
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2192349122
Short name	T206
Test name
Test status
Simulation time	353373106482 ps
CPU time	606.56 seconds
Started	Aug 27 05:49:37 AM UTC 24
Finished	Aug 27 05:59:50 AM UTC 24
Peak memory	211532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192349122 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.2192349122
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3305085599
Short name	T150
Test name
Test status
Simulation time	485459532619 ps
CPU time	588.05 seconds
Started	Aug 27 05:39:40 AM UTC 24
Finished	Aug 27 05:49:34 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305085599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3305085599
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.123368884
Short name	T121
Test name
Test status
Simulation time	53574720658 ps
CPU time	64.07 seconds
Started	Aug 27 04:32:13 AM UTC 24
Finished	Aug 27 04:33:19 AM UTC 24
Peak memory	211620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123368884 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.123368884
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3445806479
Short name	T144
Test name
Test status
Simulation time	320684242284 ps
CPU time	170.05 seconds
Started	Aug 27 05:37:28 AM UTC 24
Finished	Aug 27 05:40:21 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445806479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.3445806479
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.3763911947
Short name	T140
Test name
Test status
Simulation time	553951436029 ps
CPU time	732.2 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:49:08 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763911947 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.3763911947
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.3438884086
Short name	T319
Test name
Test status
Simulation time	535231105396 ps
CPU time	795.21 seconds
Started	Aug 27 05:56:47 AM UTC 24
Finished	Aug 27 06:10:10 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438884086 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.3438884086
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.2706331948
Short name	T154
Test name
Test status
Simulation time	364883230507 ps
CPU time	151.93 seconds
Started	Aug 27 06:01:28 AM UTC 24
Finished	Aug 27 06:04:03 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706331948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2706331948
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.3428694353
Short name	T110
Test name
Test status
Simulation time	545592725474 ps
CPU time	887.08 seconds
Started	Aug 27 05:58:49 AM UTC 24
Finished	Aug 27 06:13:45 AM UTC 24
Peak memory	211520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428694353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3428694353
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.3952189135
Short name	T22
Test name
Test status
Simulation time	189061960793 ps
CPU time	124.99 seconds
Started	Aug 27 05:36:53 AM UTC 24
Finished	Aug 27 05:39:02 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952189135 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.3952189135
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.3787721179
Short name	T257
Test name
Test status
Simulation time	336272079220 ps
CPU time	928.56 seconds
Started	Aug 27 05:37:44 AM UTC 24
Finished	Aug 27 05:53:22 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787721179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3787721179
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2647759347
Short name	T245
Test name
Test status
Simulation time	542768243305 ps
CPU time	526.95 seconds
Started	Aug 27 05:45:26 AM UTC 24
Finished	Aug 27 05:54:19 AM UTC 24
Peak memory	211616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647759347 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.2647759347
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3379648471
Short name	T259
Test name
Test status
Simulation time	497368885488 ps
CPU time	695.45 seconds
Started	Aug 27 05:59:51 AM UTC 24
Finished	Aug 27 06:11:34 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379648471 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.3379648471
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.4138577657
Short name	T210
Test name
Test status
Simulation time	505980192484 ps
CPU time	542.95 seconds
Started	Aug 27 06:21:56 AM UTC 24
Finished	Aug 27 06:31:05 AM UTC 24
Peak memory	211532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138577657 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.4138577657
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.3500438576
Short name	T2
Test name
Test status
Simulation time	407988408 ps
CPU time	1 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:36:50 AM UTC 24
Peak memory	209796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500438576 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3500438576
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.1413480868
Short name	T163
Test name
Test status
Simulation time	384192013431 ps
CPU time	185.43 seconds
Started	Aug 27 05:51:56 AM UTC 24
Finished	Aug 27 05:55:04 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413480868 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.1413480868
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.63148028
Short name	T302
Test name
Test status
Simulation time	499582598930 ps
CPU time	1297.83 seconds
Started	Aug 27 05:45:30 AM UTC 24
Finished	Aug 27 06:07:21 AM UTC 24
Peak memory	211608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63148028 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.63148028
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3670847757
Short name	T85
Test name
Test status
Simulation time	8195057669 ps
CPU time	43.95 seconds
Started	Aug 27 04:31:57 AM UTC 24
Finished	Aug 27 04:32:42 AM UTC 24
Peak memory	211580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670847757 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.3670847757
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3200161895
Short name	T352
Test name
Test status
Simulation time	485958567072 ps
CPU time	1054.66 seconds
Started	Aug 27 05:46:26 AM UTC 24
Finished	Aug 27 06:04:11 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200161895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3200161895
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.1828456978
Short name	T340
Test name
Test status
Simulation time	325824136221 ps
CPU time	431.02 seconds
Started	Aug 27 06:13:57 AM UTC 24
Finished	Aug 27 06:21:12 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828456978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1828456978
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.669806207
Short name	T81
Test name
Test status
Simulation time	3957051973 ps
CPU time	19.1 seconds
Started	Aug 27 04:32:21 AM UTC 24
Finished	Aug 27 04:32:41 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669806207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.669806207
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4163414778
Short name	T50
Test name
Test status
Simulation time	604782259878 ps
CPU time	445.45 seconds
Started	Aug 27 05:36:40 AM UTC 24
Finished	Aug 27 05:44:11 AM UTC 24
Peak memory	211716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163414778 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.4163414778
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.2408750137
Short name	T212
Test name
Test status
Simulation time	402720264665 ps
CPU time	794.8 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:50:24 AM UTC 24
Peak memory	223892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408750137 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.2408750137
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.4051973536
Short name	T203
Test name
Test status
Simulation time	512242634550 ps
CPU time	238.07 seconds
Started	Aug 27 06:15:25 AM UTC 24
Finished	Aug 27 06:19:26 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051973536 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.4051973536
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.2319719566
Short name	T363
Test name
Test status
Simulation time	503160574246 ps
CPU time	1691.87 seconds
Started	Aug 27 06:01:25 AM UTC 24
Finished	Aug 27 06:29:54 AM UTC 24
Peak memory	212752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319719566 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.2319719566
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.2294095872
Short name	T338
Test name
Test status
Simulation time	331289207746 ps
CPU time	918.91 seconds
Started	Aug 27 06:19:34 AM UTC 24
Finished	Aug 27 06:35:03 AM UTC 24
Peak memory	212552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294095872 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.2294095872
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.618496448
Short name	T310
Test name
Test status
Simulation time	358551304090 ps
CPU time	882.03 seconds
Started	Aug 27 06:24:42 AM UTC 24
Finished	Aug 27 06:39:33 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618496448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.618496448
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.2438411662
Short name	T54
Test name
Test status
Simulation time	169613410954 ps
CPU time	287.3 seconds
Started	Aug 27 05:37:01 AM UTC 24
Finished	Aug 27 05:41:52 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438411662 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.2438411662
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3720602622
Short name	T285
Test name
Test status
Simulation time	581742233995 ps
CPU time	1609.09 seconds
Started	Aug 27 05:47:05 AM UTC 24
Finished	Aug 27 06:14:09 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720602622 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.3720602622
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.860903272
Short name	T188
Test name
Test status
Simulation time	540167582468 ps
CPU time	322.29 seconds
Started	Aug 27 06:37:51 AM UTC 24
Finished	Aug 27 06:43:18 AM UTC 24
Peak memory	211864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860903272 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.860903272
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1690473195
Short name	T236
Test name
Test status
Simulation time	329871830013 ps
CPU time	200.43 seconds
Started	Aug 27 05:50:25 AM UTC 24
Finished	Aug 27 05:53:48 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690473195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1690473195
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.1918396089
Short name	T331
Test name
Test status
Simulation time	478892829553 ps
CPU time	1868.75 seconds
Started	Aug 27 05:42:51 AM UTC 24
Finished	Aug 27 06:14:17 AM UTC 24
Peak memory	221816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918396089 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.1918396089
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2028825942
Short name	T281
Test name
Test status
Simulation time	163549364181 ps
CPU time	174.22 seconds
Started	Aug 27 05:55:06 AM UTC 24
Finished	Aug 27 05:58:03 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028825942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2028825942
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3192366265
Short name	T324
Test name
Test status
Simulation time	179911946038 ps
CPU time	219.52 seconds
Started	Aug 27 06:04:45 AM UTC 24
Finished	Aug 27 06:08:28 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192366265 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.3192366265
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.4267775116
Short name	T291
Test name
Test status
Simulation time	543239680769 ps
CPU time	1375.95 seconds
Started	Aug 27 06:35:18 AM UTC 24
Finished	Aug 27 06:58:27 AM UTC 24
Peak memory	212488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267775116 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.4267775116
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1790839527
Short name	T254
Test name
Test status
Simulation time	208370799411 ps
CPU time	663.96 seconds
Started	Aug 27 05:53:27 AM UTC 24
Finished	Aug 27 06:04:38 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790839527 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.1790839527
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.519372981
Short name	T373
Test name
Test status
Simulation time	509999840566 ps
CPU time	1595.72 seconds
Started	Aug 27 05:57:39 AM UTC 24
Finished	Aug 27 06:24:31 AM UTC 24
Peak memory	212600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519372981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.519372981
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.3940266994
Short name	T309
Test name
Test status
Simulation time	509689121193 ps
CPU time	1186.5 seconds
Started	Aug 27 06:08:29 AM UTC 24
Finished	Aug 27 06:28:27 AM UTC 24
Peak memory	212540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940266994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3940266994
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.997181223
Short name	T354
Test name
Test status
Simulation time	8209423183 ps
CPU time	14.09 seconds
Started	Aug 27 06:25:46 AM UTC 24
Finished	Aug 27 06:26:01 AM UTC 24
Peak memory	211336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=997181223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.997181223
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1357963690
Short name	T298
Test name
Test status
Simulation time	591004540412 ps
CPU time	2543.95 seconds
Started	Aug 27 06:42:34 AM UTC 24
Finished	Aug 27 07:25:22 AM UTC 24
Peak memory	212816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357963690 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.1357963690
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.849474370
Short name	T253
Test name
Test status
Simulation time	52060429268 ps
CPU time	15.07 seconds
Started	Aug 27 06:42:17 AM UTC 24
Finished	Aug 27 06:42:33 AM UTC 24
Peak memory	221624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=849474370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.849474370
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.112433791
Short name	T222
Test name
Test status
Simulation time	364949335348 ps
CPU time	1096.67 seconds
Started	Aug 27 05:39:29 AM UTC 24
Finished	Aug 27 05:57:56 AM UTC 24
Peak memory	221836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112433791 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.112433791
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1319633899
Short name	T279
Test name
Test status
Simulation time	23003983264 ps
CPU time	9.21 seconds
Started	Aug 27 05:53:25 AM UTC 24
Finished	Aug 27 05:53:35 AM UTC 24
Peak memory	221884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1319633899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.adc_ctrl_stress_all_with_rand_reset.1319633899
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.4214489636
Short name	T68
Test name
Test status
Simulation time	342801869883 ps
CPU time	150.13 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:39:21 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214489636 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.4214489636
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.2078620640
Short name	T303
Test name
Test status
Simulation time	352909128952 ps
CPU time	716.62 seconds
Started	Aug 27 06:10:12 AM UTC 24
Finished	Aug 27 06:22:16 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078620640 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.2078620640
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.2680328388
Short name	T382
Test name
Test status
Simulation time	165536332016 ps
CPU time	154.5 seconds
Started	Aug 27 06:13:17 AM UTC 24
Finished	Aug 27 06:15:54 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680328388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2680328388
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.2832575224
Short name	T304
Test name
Test status
Simulation time	166838244844 ps
CPU time	63.26 seconds
Started	Aug 27 06:36:46 AM UTC 24
Finished	Aug 27 06:37:51 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832575224 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.2832575224
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.1952127049
Short name	T293
Test name
Test status
Simulation time	329535551000 ps
CPU time	243.86 seconds
Started	Aug 27 05:59:25 AM UTC 24
Finished	Aug 27 06:03:32 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952127049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1952127049
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.179858749
Short name	T355
Test name
Test status
Simulation time	356905408671 ps
CPU time	66.91 seconds
Started	Aug 27 06:07:45 AM UTC 24
Finished	Aug 27 06:08:54 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179858749 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.179858749
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.2621790927
Short name	T284
Test name
Test status
Simulation time	176487933263 ps
CPU time	154.56 seconds
Started	Aug 27 06:15:32 AM UTC 24
Finished	Aug 27 06:18:09 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621790927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2621790927
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3266847455
Short name	T321
Test name
Test status
Simulation time	215938211928 ps
CPU time	39.81 seconds
Started	Aug 27 06:22:42 AM UTC 24
Finished	Aug 27 06:23:23 AM UTC 24
Peak memory	222156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3266847455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.adc_ctrl_stress_all_with_rand_reset.3266847455
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.1441590876
Short name	T227
Test name
Test status
Simulation time	89717160445 ps
CPU time	482.59 seconds
Started	Aug 27 06:32:11 AM UTC 24
Finished	Aug 27 06:40:19 AM UTC 24
Peak memory	212096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441590876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1441590876
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.2886346139
Short name	T339
Test name
Test status
Simulation time	163738670848 ps
CPU time	482.46 seconds
Started	Aug 27 06:41:33 AM UTC 24
Finished	Aug 27 06:49:41 AM UTC 24
Peak memory	211556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886346139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2886346139
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.975571889
Short name	T95
Test name
Test status
Simulation time	8805119371 ps
CPU time	7.46 seconds
Started	Aug 27 04:33:37 AM UTC 24
Finished	Aug 27 04:33:45 AM UTC 24
Peak memory	211524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975571889 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.975571889
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.1651481554
Short name	T77
Test name
Test status
Simulation time	114982177106 ps
CPU time	478.62 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:44:48 AM UTC 24
Peak memory	211884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651481554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1651481554
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2232315299
Short name	T312
Test name
Test status
Simulation time	166843157804 ps
CPU time	478.93 seconds
Started	Aug 27 05:52:23 AM UTC 24
Finished	Aug 27 06:00:28 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232315299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2232315299
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.3242448922
Short name	T343
Test name
Test status
Simulation time	167009766623 ps
CPU time	323.64 seconds
Started	Aug 27 05:58:04 AM UTC 24
Finished	Aug 27 06:03:32 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242448922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3242448922
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.692375733
Short name	T221
Test name
Test status
Simulation time	125773653644 ps
CPU time	931.36 seconds
Started	Aug 27 06:08:50 AM UTC 24
Finished	Aug 27 06:24:31 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692375733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.692375733
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.1012486879
Short name	T301
Test name
Test status
Simulation time	625690708102 ps
CPU time	541.65 seconds
Started	Aug 27 06:29:11 AM UTC 24
Finished	Aug 27 06:38:19 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012486879 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.1012486879
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.2600261502
Short name	T314
Test name
Test status
Simulation time	495728619769 ps
CPU time	1393.43 seconds
Started	Aug 27 06:40:27 AM UTC 24
Finished	Aug 27 07:03:55 AM UTC 24
Peak memory	212496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600261502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2600261502
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2777388993
Short name	T894
Test name
Test status
Simulation time	8192570438 ps
CPU time	28.63 seconds
Started	Aug 27 04:34:07 AM UTC 24
Finished	Aug 27 04:34:37 AM UTC 24
Peak memory	211556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777388993 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.2777388993
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.1267041402
Short name	T230
Test name
Test status
Simulation time	4004232089912 ps
CPU time	1886.65 seconds
Started	Aug 27 05:46:18 AM UTC 24
Finished	Aug 27 06:18:02 AM UTC 24
Peak memory	224116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267041402 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.1267041402
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1540374882
Short name	T235
Test name
Test status
Simulation time	117538160443 ps
CPU time	527.11 seconds
Started	Aug 27 05:48:18 AM UTC 24
Finished	Aug 27 05:57:10 AM UTC 24
Peak memory	211768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540374882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1540374882
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.2464277264
Short name	T164
Test name
Test status
Simulation time	254128930529 ps
CPU time	426.52 seconds
Started	Aug 27 05:50:16 AM UTC 24
Finished	Aug 27 05:57:27 AM UTC 24
Peak memory	211884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464277264 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.2464277264
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.1535444798
Short name	T229
Test name
Test status
Simulation time	106538189183 ps
CPU time	611.46 seconds
Started	Aug 27 06:18:47 AM UTC 24
Finished	Aug 27 06:29:05 AM UTC 24
Peak memory	212036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535444798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1535444798
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.940280467
Short name	T361
Test name
Test status
Simulation time	173928335660 ps
CPU time	344.84 seconds
Started	Aug 27 06:24:24 AM UTC 24
Finished	Aug 27 06:30:13 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940280467 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.940280467
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.1129954836
Short name	T187
Test name
Test status
Simulation time	350187669064 ps
CPU time	297.85 seconds
Started	Aug 27 06:26:20 AM UTC 24
Finished	Aug 27 06:31:22 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129954836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1129954836
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.4181249300
Short name	T305
Test name
Test status
Simulation time	406269892421 ps
CPU time	1184.61 seconds
Started	Aug 27 06:27:10 AM UTC 24
Finished	Aug 27 06:47:06 AM UTC 24
Peak memory	212552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181249300 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.4181249300
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.917961579
Short name	T189
Test name
Test status
Simulation time	560316935452 ps
CPU time	904.61 seconds
Started	Aug 27 06:31:59 AM UTC 24
Finished	Aug 27 06:47:13 AM UTC 24
Peak memory	212560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917961579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.917961579
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.652484525
Short name	T193
Test name
Test status
Simulation time	540830130794 ps
CPU time	285.51 seconds
Started	Aug 27 06:40:41 AM UTC 24
Finished	Aug 27 06:45:30 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652484525 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.652484525
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3776290357
Short name	T115
Test name
Test status
Simulation time	1216725194 ps
CPU time	4.67 seconds
Started	Aug 27 04:32:15 AM UTC 24
Finished	Aug 27 04:32:21 AM UTC 24
Peak memory	211428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776290357 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.3776290357
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2028292531
Short name	T113
Test name
Test status
Simulation time	940882802 ps
CPU time	5.69 seconds
Started	Aug 27 04:32:06 AM UTC 24
Finished	Aug 27 04:32:13 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028292531 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.2028292531
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.124662633
Short name	T98
Test name
Test status
Simulation time	581236272 ps
CPU time	3.97 seconds
Started	Aug 27 04:32:33 AM UTC 24
Finished	Aug 27 04:32:38 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=124662633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr _mem_rw_with_rand_reset.124662633
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1934634351
Short name	T114
Test name
Test status
Simulation time	571575667 ps
CPU time	1.69 seconds
Started	Aug 27 04:32:12 AM UTC 24
Finished	Aug 27 04:32:15 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934634351 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1934634351
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.3990166954
Short name	T800
Test name
Test status
Simulation time	446628278 ps
CPU time	2.08 seconds
Started	Aug 27 04:32:02 AM UTC 24
Finished	Aug 27 04:32:05 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990166954 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3990166954
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2722066181
Short name	T135
Test name
Test status
Simulation time	938134685 ps
CPU time	4.32 seconds
Started	Aug 27 04:32:45 AM UTC 24
Finished	Aug 27 04:32:50 AM UTC 24
Peak memory	211428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722066181 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.2722066181
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.308743871
Short name	T120
Test name
Test status
Simulation time	29548410190 ps
CPU time	33.46 seconds
Started	Aug 27 04:32:44 AM UTC 24
Finished	Aug 27 04:33:19 AM UTC 24
Peak memory	211400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308743871 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.308743871
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2182857008
Short name	T116
Test name
Test status
Simulation time	685127730 ps
CPU time	3.6 seconds
Started	Aug 27 04:32:42 AM UTC 24
Finished	Aug 27 04:32:46 AM UTC 24
Peak memory	211344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182857008 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.2182857008
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.451056399
Short name	T99
Test name
Test status
Simulation time	419991766 ps
CPU time	1.52 seconds
Started	Aug 27 04:32:46 AM UTC 24
Finished	Aug 27 04:32:49 AM UTC 24
Peak memory	209920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=451056399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr _mem_rw_with_rand_reset.451056399
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1967916035
Short name	T129
Test name
Test status
Simulation time	613540850 ps
CPU time	1.79 seconds
Started	Aug 27 04:32:43 AM UTC 24
Finished	Aug 27 04:32:46 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967916035 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1967916035
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2396526676
Short name	T801
Test name
Test status
Simulation time	426087435 ps
CPU time	1.28 seconds
Started	Aug 27 04:32:41 AM UTC 24
Finished	Aug 27 04:32:43 AM UTC 24
Peak memory	209916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396526676 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2396526676
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4070583374
Short name	T82
Test name
Test status
Simulation time	4477218034 ps
CPU time	10.57 seconds
Started	Aug 27 04:32:46 AM UTC 24
Finished	Aug 27 04:32:58 AM UTC 24
Peak memory	211588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070583374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.4070583374
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.451803278
Short name	T90
Test name
Test status
Simulation time	405721679 ps
CPU time	4.68 seconds
Started	Aug 27 04:32:35 AM UTC 24
Finished	Aug 27 04:32:40 AM UTC 24
Peak memory	221340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451803278 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.451803278
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2555227523
Short name	T86
Test name
Test status
Simulation time	4571035016 ps
CPU time	22.76 seconds
Started	Aug 27 04:32:40 AM UTC 24
Finished	Aug 27 04:33:04 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555227523 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.2555227523
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2188521602
Short name	T834
Test name
Test status
Simulation time	616678128 ps
CPU time	2.15 seconds
Started	Aug 27 04:33:54 AM UTC 24
Finished	Aug 27 04:33:57 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2188521602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c sr_mem_rw_with_rand_reset.2188521602
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3390500091
Short name	T830
Test name
Test status
Simulation time	400816754 ps
CPU time	2.11 seconds
Started	Aug 27 04:33:52 AM UTC 24
Finished	Aug 27 04:33:55 AM UTC 24
Peak memory	211224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390500091 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3390500091
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2175535618
Short name	T828
Test name
Test status
Simulation time	391903619 ps
CPU time	2.02 seconds
Started	Aug 27 04:33:50 AM UTC 24
Finished	Aug 27 04:33:53 AM UTC 24
Peak memory	211180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175535618 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2175535618
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3009499179
Short name	T836
Test name
Test status
Simulation time	2537173999 ps
CPU time	4.24 seconds
Started	Aug 27 04:33:53 AM UTC 24
Finished	Aug 27 04:33:58 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009499179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.3009499179
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1147498146
Short name	T829
Test name
Test status
Simulation time	654938827 ps
CPU time	3.3 seconds
Started	Aug 27 04:33:49 AM UTC 24
Finished	Aug 27 04:33:54 AM UTC 24
Peak memory	227520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147498146 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1147498146
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.875120357
Short name	T865
Test name
Test status
Simulation time	8034341005 ps
CPU time	31.08 seconds
Started	Aug 27 04:33:49 AM UTC 24
Finished	Aug 27 04:34:22 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875120357 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.875120357
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3115039170
Short name	T839
Test name
Test status
Simulation time	553510751 ps
CPU time	1.95 seconds
Started	Aug 27 04:33:58 AM UTC 24
Finished	Aug 27 04:34:01 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3115039170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_c sr_mem_rw_with_rand_reset.3115039170
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3063158369
Short name	T838
Test name
Test status
Simulation time	566888472 ps
CPU time	2.08 seconds
Started	Aug 27 04:33:56 AM UTC 24
Finished	Aug 27 04:33:59 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063158369 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3063158369
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2557653401
Short name	T837
Test name
Test status
Simulation time	402803391 ps
CPU time	1.43 seconds
Started	Aug 27 04:33:56 AM UTC 24
Finished	Aug 27 04:33:58 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557653401 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2557653401
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3227561522
Short name	T846
Test name
Test status
Simulation time	1873434585 ps
CPU time	9.02 seconds
Started	Aug 27 04:33:57 AM UTC 24
Finished	Aug 27 04:34:07 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227561522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.3227561522
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3887998825
Short name	T835
Test name
Test status
Simulation time	555350082 ps
CPU time	1.72 seconds
Started	Aug 27 04:33:55 AM UTC 24
Finished	Aug 27 04:33:57 AM UTC 24
Peak memory	210336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887998825 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3887998825
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3499479025
Short name	T842
Test name
Test status
Simulation time	5049625736 ps
CPU time	6.43 seconds
Started	Aug 27 04:33:55 AM UTC 24
Finished	Aug 27 04:34:02 AM UTC 24
Peak memory	211392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499479025 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.3499479025
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2324379818
Short name	T843
Test name
Test status
Simulation time	521152702 ps
CPU time	2.76 seconds
Started	Aug 27 04:34:00 AM UTC 24
Finished	Aug 27 04:34:04 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2324379818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c sr_mem_rw_with_rand_reset.2324379818
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3200254833
Short name	T128
Test name
Test status
Simulation time	406005456 ps
CPU time	2.79 seconds
Started	Aug 27 04:33:59 AM UTC 24
Finished	Aug 27 04:34:03 AM UTC 24
Peak memory	211220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200254833 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3200254833
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2622902348
Short name	T841
Test name
Test status
Simulation time	415983189 ps
CPU time	3.14 seconds
Started	Aug 27 04:33:58 AM UTC 24
Finished	Aug 27 04:34:02 AM UTC 24
Peak memory	211180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622902348 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2622902348
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2220817931
Short name	T862
Test name
Test status
Simulation time	4605286295 ps
CPU time	18.26 seconds
Started	Aug 27 04:33:59 AM UTC 24
Finished	Aug 27 04:34:19 AM UTC 24
Peak memory	211516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220817931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.2220817931
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.488402925
Short name	T840
Test name
Test status
Simulation time	747127092 ps
CPU time	2.72 seconds
Started	Aug 27 04:33:58 AM UTC 24
Finished	Aug 27 04:34:02 AM UTC 24
Peak memory	211396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488402925 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.488402925
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.22923101
Short name	T854
Test name
Test status
Simulation time	8823794670 ps
CPU time	13.72 seconds
Started	Aug 27 04:33:58 AM UTC 24
Finished	Aug 27 04:34:13 AM UTC 24
Peak memory	211428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22923101 -assert nopostproc +UVM_TESTN AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.22923101
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3393178598
Short name	T848
Test name
Test status
Simulation time	492557135 ps
CPU time	2.07 seconds
Started	Aug 27 04:34:05 AM UTC 24
Finished	Aug 27 04:34:08 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3393178598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_c sr_mem_rw_with_rand_reset.3393178598
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.93446872
Short name	T125
Test name
Test status
Simulation time	455826993 ps
CPU time	2.14 seconds
Started	Aug 27 04:34:04 AM UTC 24
Finished	Aug 27 04:34:07 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93446872 -assert nopostproc +UVM_TESTNAME=adc_c trl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.93446872
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.958104780
Short name	T845
Test name
Test status
Simulation time	381314114 ps
CPU time	1.96 seconds
Started	Aug 27 04:34:03 AM UTC 24
Finished	Aug 27 04:34:06 AM UTC 24
Peak memory	210280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958104780 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.958104780
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2546267072
Short name	T849
Test name
Test status
Simulation time	4403515954 ps
CPU time	4.11 seconds
Started	Aug 27 04:34:04 AM UTC 24
Finished	Aug 27 04:34:09 AM UTC 24
Peak memory	211428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546267072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.2546267072
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1785326178
Short name	T844
Test name
Test status
Simulation time	604970946 ps
CPU time	3.52 seconds
Started	Aug 27 04:34:01 AM UTC 24
Finished	Aug 27 04:34:06 AM UTC 24
Peak memory	221452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785326178 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1785326178
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.787249616
Short name	T859
Test name
Test status
Simulation time	4416300109 ps
CPU time	13.75 seconds
Started	Aug 27 04:34:02 AM UTC 24
Finished	Aug 27 04:34:17 AM UTC 24
Peak memory	211560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787249616 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.787249616
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.561856246
Short name	T853
Test name
Test status
Simulation time	563907346 ps
CPU time	1.4 seconds
Started	Aug 27 04:34:09 AM UTC 24
Finished	Aug 27 04:34:11 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=561856246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_cs r_mem_rw_with_rand_reset.561856246
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1796548179
Short name	T126
Test name
Test status
Simulation time	299773717 ps
CPU time	1.8 seconds
Started	Aug 27 04:34:08 AM UTC 24
Finished	Aug 27 04:34:11 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796548179 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1796548179
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1587557975
Short name	T852
Test name
Test status
Simulation time	396812690 ps
CPU time	2.44 seconds
Started	Aug 27 04:34:08 AM UTC 24
Finished	Aug 27 04:34:11 AM UTC 24
Peak memory	211096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587557975 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1587557975
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1005310192
Short name	T875
Test name
Test status
Simulation time	4227498848 ps
CPU time	16.76 seconds
Started	Aug 27 04:34:08 AM UTC 24
Finished	Aug 27 04:34:26 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005310192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.1005310192
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2013424047
Short name	T851
Test name
Test status
Simulation time	544397298 ps
CPU time	3.2 seconds
Started	Aug 27 04:34:07 AM UTC 24
Finished	Aug 27 04:34:11 AM UTC 24
Peak memory	211460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013424047 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2013424047
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.321632614
Short name	T858
Test name
Test status
Simulation time	462949872 ps
CPU time	3.67 seconds
Started	Aug 27 04:34:12 AM UTC 24
Finished	Aug 27 04:34:17 AM UTC 24
Peak memory	211336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=321632614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_cs r_mem_rw_with_rand_reset.321632614
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2701869689
Short name	T857
Test name
Test status
Simulation time	335174832 ps
CPU time	2.79 seconds
Started	Aug 27 04:34:12 AM UTC 24
Finished	Aug 27 04:34:16 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701869689 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2701869689
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3892207253
Short name	T855
Test name
Test status
Simulation time	566880794 ps
CPU time	1.42 seconds
Started	Aug 27 04:34:11 AM UTC 24
Finished	Aug 27 04:34:14 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892207253 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3892207253
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3087866610
Short name	T869
Test name
Test status
Simulation time	5413915844 ps
CPU time	9.77 seconds
Started	Aug 27 04:34:12 AM UTC 24
Finished	Aug 27 04:34:23 AM UTC 24
Peak memory	211652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087866610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.3087866610
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2199205388
Short name	T856
Test name
Test status
Simulation time	476160980 ps
CPU time	2.58 seconds
Started	Aug 27 04:34:10 AM UTC 24
Finished	Aug 27 04:34:14 AM UTC 24
Peak memory	211372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199205388 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2199205388
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1334862077
Short name	T385
Test name
Test status
Simulation time	9230868699 ps
CPU time	9 seconds
Started	Aug 27 04:34:11 AM UTC 24
Finished	Aug 27 04:34:21 AM UTC 24
Peak memory	211444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334862077 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.1334862077
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.509507584
Short name	T864
Test name
Test status
Simulation time	493501936 ps
CPU time	2.59 seconds
Started	Aug 27 04:34:18 AM UTC 24
Finished	Aug 27 04:34:21 AM UTC 24
Peak memory	211336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=509507584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_cs r_mem_rw_with_rand_reset.509507584
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2133465570
Short name	T863
Test name
Test status
Simulation time	586126070 ps
CPU time	1.58 seconds
Started	Aug 27 04:34:17 AM UTC 24
Finished	Aug 27 04:34:19 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133465570 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2133465570
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.740173296
Short name	T861
Test name
Test status
Simulation time	413655770 ps
CPU time	2.52 seconds
Started	Aug 27 04:34:15 AM UTC 24
Finished	Aug 27 04:34:18 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740173296 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.740173296
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1318814415
Short name	T868
Test name
Test status
Simulation time	2681288469 ps
CPU time	4.16 seconds
Started	Aug 27 04:34:18 AM UTC 24
Finished	Aug 27 04:34:23 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318814415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.1318814415
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3786900350
Short name	T860
Test name
Test status
Simulation time	399273769 ps
CPU time	2.95 seconds
Started	Aug 27 04:34:13 AM UTC 24
Finished	Aug 27 04:34:17 AM UTC 24
Peak memory	211328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786900350 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3786900350
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1345569540
Short name	T898
Test name
Test status
Simulation time	7846591337 ps
CPU time	21.86 seconds
Started	Aug 27 04:34:14 AM UTC 24
Finished	Aug 27 04:34:37 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345569540 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.1345569540
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4139183967
Short name	T873
Test name
Test status
Simulation time	645169634 ps
CPU time	2.07 seconds
Started	Aug 27 04:34:22 AM UTC 24
Finished	Aug 27 04:34:25 AM UTC 24
Peak memory	221516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4139183967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c sr_mem_rw_with_rand_reset.4139183967
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.812792955
Short name	T867
Test name
Test status
Simulation time	588401903 ps
CPU time	1.91 seconds
Started	Aug 27 04:34:20 AM UTC 24
Finished	Aug 27 04:34:23 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812792955 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.812792955
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.3808991487
Short name	T866
Test name
Test status
Simulation time	492287564 ps
CPU time	1.85 seconds
Started	Aug 27 04:34:20 AM UTC 24
Finished	Aug 27 04:34:23 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808991487 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3808991487
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1308269393
Short name	T919
Test name
Test status
Simulation time	4760294824 ps
CPU time	24.05 seconds
Started	Aug 27 04:34:22 AM UTC 24
Finished	Aug 27 04:34:48 AM UTC 24
Peak memory	211516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308269393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.1308269393
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1804104740
Short name	T871
Test name
Test status
Simulation time	394390533 ps
CPU time	4.11 seconds
Started	Aug 27 04:34:19 AM UTC 24
Finished	Aug 27 04:34:24 AM UTC 24
Peak memory	211460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804104740 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1804104740
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3452637222
Short name	T906
Test name
Test status
Simulation time	8293992859 ps
CPU time	20.26 seconds
Started	Aug 27 04:34:19 AM UTC 24
Finished	Aug 27 04:34:40 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452637222 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.3452637222
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2607052117
Short name	T880
Test name
Test status
Simulation time	424211852 ps
CPU time	3.3 seconds
Started	Aug 27 04:34:25 AM UTC 24
Finished	Aug 27 04:34:29 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2607052117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c sr_mem_rw_with_rand_reset.2607052117
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4099093379
Short name	T877
Test name
Test status
Simulation time	521125324 ps
CPU time	3.88 seconds
Started	Aug 27 04:34:23 AM UTC 24
Finished	Aug 27 04:34:28 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099093379 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4099093379
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.821747118
Short name	T874
Test name
Test status
Simulation time	512330020 ps
CPU time	1.42 seconds
Started	Aug 27 04:34:23 AM UTC 24
Finished	Aug 27 04:34:26 AM UTC 24
Peak memory	210280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821747118 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.821747118
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2570968291
Short name	T920
Test name
Test status
Simulation time	4588642744 ps
CPU time	29.67 seconds
Started	Aug 27 04:34:25 AM UTC 24
Finished	Aug 27 04:34:56 AM UTC 24
Peak memory	211560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570968291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.2570968291
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1933725709
Short name	T882
Test name
Test status
Simulation time	513008832 ps
CPU time	5.46 seconds
Started	Aug 27 04:34:23 AM UTC 24
Finished	Aug 27 04:34:30 AM UTC 24
Peak memory	211432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933725709 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1933725709
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1496530
Short name	T904
Test name
Test status
Simulation time	8665423162 ps
CPU time	15 seconds
Started	Aug 27 04:34:23 AM UTC 24
Finished	Aug 27 04:34:40 AM UTC 24
Peak memory	211724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496530 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.1496530
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2121266500
Short name	T881
Test name
Test status
Simulation time	799788014 ps
CPU time	1.65 seconds
Started	Aug 27 04:34:27 AM UTC 24
Finished	Aug 27 04:34:30 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2121266500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_c sr_mem_rw_with_rand_reset.2121266500
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1429603617
Short name	T878
Test name
Test status
Simulation time	440469799 ps
CPU time	1.65 seconds
Started	Aug 27 04:34:26 AM UTC 24
Finished	Aug 27 04:34:28 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429603617 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1429603617
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2406428036
Short name	T876
Test name
Test status
Simulation time	369382760 ps
CPU time	1.41 seconds
Started	Aug 27 04:34:26 AM UTC 24
Finished	Aug 27 04:34:28 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406428036 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2406428036
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2310119357
Short name	T889
Test name
Test status
Simulation time	4730306997 ps
CPU time	5.57 seconds
Started	Aug 27 04:34:27 AM UTC 24
Finished	Aug 27 04:34:34 AM UTC 24
Peak memory	211652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310119357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.2310119357
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4273408494
Short name	T879
Test name
Test status
Simulation time	453264870 ps
CPU time	2.72 seconds
Started	Aug 27 04:34:25 AM UTC 24
Finished	Aug 27 04:34:29 AM UTC 24
Peak memory	227744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273408494 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4273408494
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2504792780
Short name	T900
Test name
Test status
Simulation time	9066987593 ps
CPU time	12.1 seconds
Started	Aug 27 04:34:25 AM UTC 24
Finished	Aug 27 04:34:38 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504792780 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.2504792780
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1689866653
Short name	T803
Test name
Test status
Simulation time	1407295316 ps
CPU time	11.12 seconds
Started	Aug 27 04:32:53 AM UTC 24
Finished	Aug 27 04:33:06 AM UTC 24
Peak memory	211368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689866653 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.1689866653
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4858481
Short name	T870
Test name
Test status
Simulation time	26625304857 ps
CPU time	91.06 seconds
Started	Aug 27 04:32:51 AM UTC 24
Finished	Aug 27 04:34:24 AM UTC 24
Peak memory	211660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4858481 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.4858481
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3721109599
Short name	T117
Test name
Test status
Simulation time	1146783776 ps
CPU time	3.78 seconds
Started	Aug 27 04:32:50 AM UTC 24
Finished	Aug 27 04:32:55 AM UTC 24
Peak memory	211216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721109599 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.3721109599
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1011870691
Short name	T100
Test name
Test status
Simulation time	546830387 ps
CPU time	2.13 seconds
Started	Aug 27 04:32:57 AM UTC 24
Finished	Aug 27 04:33:00 AM UTC 24
Peak memory	221260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1011870691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs r_mem_rw_with_rand_reset.1011870691
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.156223318
Short name	T118
Test name
Test status
Simulation time	523330797 ps
CPU time	3.95 seconds
Started	Aug 27 04:32:51 AM UTC 24
Finished	Aug 27 04:32:56 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156223318 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.156223318
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1420370344
Short name	T802
Test name
Test status
Simulation time	468739509 ps
CPU time	1.53 seconds
Started	Aug 27 04:32:48 AM UTC 24
Finished	Aug 27 04:32:50 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420370344 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1420370344
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3065195646
Short name	T133
Test name
Test status
Simulation time	4713527270 ps
CPU time	27.09 seconds
Started	Aug 27 04:32:56 AM UTC 24
Finished	Aug 27 04:33:25 AM UTC 24
Peak memory	211516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065195646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.3065195646
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1348096672
Short name	T91
Test name
Test status
Simulation time	686785483 ps
CPU time	3.45 seconds
Started	Aug 27 04:32:48 AM UTC 24
Finished	Aug 27 04:32:52 AM UTC 24
Peak memory	211432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348096672 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1348096672
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2537376701
Short name	T386
Test name
Test status
Simulation time	8421517167 ps
CPU time	45.78 seconds
Started	Aug 27 04:32:48 AM UTC 24
Finished	Aug 27 04:33:35 AM UTC 24
Peak memory	211396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537376701 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.2537376701
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2429745781
Short name	T884
Test name
Test status
Simulation time	304919510 ps
CPU time	1.71 seconds
Started	Aug 27 04:34:29 AM UTC 24
Finished	Aug 27 04:34:32 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429745781 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2429745781
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.4250243699
Short name	T886
Test name
Test status
Simulation time	317355937 ps
CPU time	2.08 seconds
Started	Aug 27 04:34:29 AM UTC 24
Finished	Aug 27 04:34:32 AM UTC 24
Peak memory	211100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250243699 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4250243699
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2211982227
Short name	T883
Test name
Test status
Simulation time	323003936 ps
CPU time	1.34 seconds
Started	Aug 27 04:34:29 AM UTC 24
Finished	Aug 27 04:34:32 AM UTC 24
Peak memory	209856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211982227 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2211982227
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3708557507
Short name	T885
Test name
Test status
Simulation time	425931033 ps
CPU time	1.76 seconds
Started	Aug 27 04:34:29 AM UTC 24
Finished	Aug 27 04:34:32 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708557507 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3708557507
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2319448795
Short name	T890
Test name
Test status
Simulation time	466784918 ps
CPU time	3.19 seconds
Started	Aug 27 04:34:30 AM UTC 24
Finished	Aug 27 04:34:34 AM UTC 24
Peak memory	211220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319448795 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2319448795
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3605105939
Short name	T887
Test name
Test status
Simulation time	454943346 ps
CPU time	1.29 seconds
Started	Aug 27 04:34:30 AM UTC 24
Finished	Aug 27 04:34:33 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605105939 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3605105939
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.3831404652
Short name	T888
Test name
Test status
Simulation time	550414532 ps
CPU time	1.61 seconds
Started	Aug 27 04:34:30 AM UTC 24
Finished	Aug 27 04:34:33 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831404652 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3831404652
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.272669542
Short name	T892
Test name
Test status
Simulation time	438962046 ps
CPU time	1.53 seconds
Started	Aug 27 04:34:32 AM UTC 24
Finished	Aug 27 04:34:35 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272669542 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.272669542
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2491459778
Short name	T891
Test name
Test status
Simulation time	479095222 ps
CPU time	1.34 seconds
Started	Aug 27 04:34:32 AM UTC 24
Finished	Aug 27 04:34:35 AM UTC 24
Peak memory	209856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491459778 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2491459778
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.144533576
Short name	T895
Test name
Test status
Simulation time	477812160 ps
CPU time	3.29 seconds
Started	Aug 27 04:34:32 AM UTC 24
Finished	Aug 27 04:34:37 AM UTC 24
Peak memory	211092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144533576 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.144533576
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.768402783
Short name	T119
Test name
Test status
Simulation time	750300555 ps
CPU time	5.43 seconds
Started	Aug 27 04:33:08 AM UTC 24
Finished	Aug 27 04:33:15 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768402783 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.768402783
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1968922441
Short name	T850
Test name
Test status
Simulation time	26282009309 ps
CPU time	60.91 seconds
Started	Aug 27 04:33:07 AM UTC 24
Finished	Aug 27 04:34:10 AM UTC 24
Peak memory	211620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968922441 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.1968922441
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4249879173
Short name	T804
Test name
Test status
Simulation time	732587608 ps
CPU time	1.42 seconds
Started	Aug 27 04:33:04 AM UTC 24
Finished	Aug 27 04:33:07 AM UTC 24
Peak memory	209984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249879173 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.4249879173
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2588209332
Short name	T101
Test name
Test status
Simulation time	488018873 ps
CPU time	2.09 seconds
Started	Aug 27 04:33:11 AM UTC 24
Finished	Aug 27 04:33:14 AM UTC 24
Peak memory	211404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2588209332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cs r_mem_rw_with_rand_reset.2588209332
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1545451284
Short name	T130
Test name
Test status
Simulation time	509925501 ps
CPU time	2.39 seconds
Started	Aug 27 04:33:06 AM UTC 24
Finished	Aug 27 04:33:10 AM UTC 24
Peak memory	211200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545451284 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1545451284
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.2014462536
Short name	T805
Test name
Test status
Simulation time	340220930 ps
CPU time	2.43 seconds
Started	Aug 27 04:33:04 AM UTC 24
Finished	Aug 27 04:33:08 AM UTC 24
Peak memory	211096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014462536 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2014462536
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4174325282
Short name	T83
Test name
Test status
Simulation time	2762299695 ps
CPU time	5.08 seconds
Started	Aug 27 04:33:10 AM UTC 24
Finished	Aug 27 04:33:16 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174325282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.4174325282
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2661087404
Short name	T92
Test name
Test status
Simulation time	391712315 ps
CPU time	3.23 seconds
Started	Aug 27 04:32:59 AM UTC 24
Finished	Aug 27 04:33:04 AM UTC 24
Peak memory	211268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661087404 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2661087404
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2369771223
Short name	T87
Test name
Test status
Simulation time	5045992004 ps
CPU time	9.29 seconds
Started	Aug 27 04:33:01 AM UTC 24
Finished	Aug 27 04:33:11 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369771223 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.2369771223
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.1821579361
Short name	T893
Test name
Test status
Simulation time	317749684 ps
CPU time	1.29 seconds
Started	Aug 27 04:34:33 AM UTC 24
Finished	Aug 27 04:34:36 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821579361 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1821579361
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.3811348079
Short name	T897
Test name
Test status
Simulation time	390699641 ps
CPU time	2.86 seconds
Started	Aug 27 04:34:34 AM UTC 24
Finished	Aug 27 04:34:37 AM UTC 24
Peak memory	211180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811348079 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3811348079
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.4000388248
Short name	T899
Test name
Test status
Simulation time	465772204 ps
CPU time	2.56 seconds
Started	Aug 27 04:34:35 AM UTC 24
Finished	Aug 27 04:34:38 AM UTC 24
Peak memory	211176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000388248 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.4000388248
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3606073079
Short name	T896
Test name
Test status
Simulation time	547327658 ps
CPU time	1.62 seconds
Started	Aug 27 04:34:35 AM UTC 24
Finished	Aug 27 04:34:37 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606073079 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3606073079
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.3809997453
Short name	T903
Test name
Test status
Simulation time	278921871 ps
CPU time	2.28 seconds
Started	Aug 27 04:34:36 AM UTC 24
Finished	Aug 27 04:34:39 AM UTC 24
Peak memory	211100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809997453 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3809997453
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2788855869
Short name	T902
Test name
Test status
Simulation time	335177664 ps
CPU time	2.04 seconds
Started	Aug 27 04:34:36 AM UTC 24
Finished	Aug 27 04:34:39 AM UTC 24
Peak memory	211180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788855869 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2788855869
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.3904480979
Short name	T901
Test name
Test status
Simulation time	398461949 ps
CPU time	1.63 seconds
Started	Aug 27 04:34:36 AM UTC 24
Finished	Aug 27 04:34:39 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904480979 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3904480979
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.554319536
Short name	T905
Test name
Test status
Simulation time	484157734 ps
CPU time	1.45 seconds
Started	Aug 27 04:34:37 AM UTC 24
Finished	Aug 27 04:34:40 AM UTC 24
Peak memory	209920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554319536 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.554319536
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.1896686675
Short name	T910
Test name
Test status
Simulation time	450484455 ps
CPU time	2.93 seconds
Started	Aug 27 04:34:38 AM UTC 24
Finished	Aug 27 04:34:42 AM UTC 24
Peak memory	211100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896686675 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1896686675
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.1417589283
Short name	T915
Test name
Test status
Simulation time	504479825 ps
CPU time	3.44 seconds
Started	Aug 27 04:34:38 AM UTC 24
Finished	Aug 27 04:34:43 AM UTC 24
Peak memory	211180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417589283 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1417589283
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.487916048
Short name	T123
Test name
Test status
Simulation time	1029154596 ps
CPU time	7.8 seconds
Started	Aug 27 04:33:19 AM UTC 24
Finished	Aug 27 04:33:28 AM UTC 24
Peak memory	211356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487916048 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.487916048
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2665923697
Short name	T872
Test name
Test status
Simulation time	36812394356 ps
CPU time	64.46 seconds
Started	Aug 27 04:33:19 AM UTC 24
Finished	Aug 27 04:34:25 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665923697 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.2665923697
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.202885924
Short name	T122
Test name
Test status
Simulation time	1167322717 ps
CPU time	4.02 seconds
Started	Aug 27 04:33:17 AM UTC 24
Finished	Aug 27 04:33:22 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202885924 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.202885924
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3725421758
Short name	T807
Test name
Test status
Simulation time	538990717 ps
CPU time	1.82 seconds
Started	Aug 27 04:33:21 AM UTC 24
Finished	Aug 27 04:33:24 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3725421758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cs r_mem_rw_with_rand_reset.3725421758
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3320713943
Short name	T131
Test name
Test status
Simulation time	512411995 ps
CPU time	3.74 seconds
Started	Aug 27 04:33:17 AM UTC 24
Finished	Aug 27 04:33:22 AM UTC 24
Peak memory	211336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320713943 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3320713943
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3277978640
Short name	T806
Test name
Test status
Simulation time	535405331 ps
CPU time	1.67 seconds
Started	Aug 27 04:33:16 AM UTC 24
Finished	Aug 27 04:33:18 AM UTC 24
Peak memory	209916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277978640 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3277978640
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2784933175
Short name	T132
Test name
Test status
Simulation time	2063536404 ps
CPU time	3.82 seconds
Started	Aug 27 04:33:20 AM UTC 24
Finished	Aug 27 04:33:25 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784933175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.2784933175
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1892713314
Short name	T93
Test name
Test status
Simulation time	667702390 ps
CPU time	2.5 seconds
Started	Aug 27 04:33:13 AM UTC 24
Finished	Aug 27 04:33:16 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892713314 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1892713314
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1194806045
Short name	T383
Test name
Test status
Simulation time	4749162578 ps
CPU time	4.44 seconds
Started	Aug 27 04:33:15 AM UTC 24
Finished	Aug 27 04:33:20 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194806045 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.1194806045
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2299696145
Short name	T912
Test name
Test status
Simulation time	411843534 ps
CPU time	2.83 seconds
Started	Aug 27 04:34:38 AM UTC 24
Finished	Aug 27 04:34:42 AM UTC 24
Peak memory	211096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299696145 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2299696145
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.3593414557
Short name	T907
Test name
Test status
Simulation time	297406013 ps
CPU time	1.52 seconds
Started	Aug 27 04:34:38 AM UTC 24
Finished	Aug 27 04:34:41 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593414557 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3593414557
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.3182979869
Short name	T909
Test name
Test status
Simulation time	392447324 ps
CPU time	2.7 seconds
Started	Aug 27 04:34:38 AM UTC 24
Finished	Aug 27 04:34:42 AM UTC 24
Peak memory	211096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182979869 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3182979869
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.1333603983
Short name	T908
Test name
Test status
Simulation time	501686036 ps
CPU time	1.56 seconds
Started	Aug 27 04:34:39 AM UTC 24
Finished	Aug 27 04:34:42 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333603983 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1333603983
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.244027565
Short name	T913
Test name
Test status
Simulation time	318494717 ps
CPU time	2.21 seconds
Started	Aug 27 04:34:39 AM UTC 24
Finished	Aug 27 04:34:43 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244027565 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.244027565
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.2887515549
Short name	T911
Test name
Test status
Simulation time	464052866 ps
CPU time	1.66 seconds
Started	Aug 27 04:34:39 AM UTC 24
Finished	Aug 27 04:34:42 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887515549 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2887515549
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.15693827
Short name	T918
Test name
Test status
Simulation time	495895505 ps
CPU time	3.26 seconds
Started	Aug 27 04:34:40 AM UTC 24
Finished	Aug 27 04:34:45 AM UTC 24
Peak memory	211096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15693827 -assert nopostproc +UVM_TESTNAME=adc_ctrl _base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.15693827
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.758241249
Short name	T916
Test name
Test status
Simulation time	464022761 ps
CPU time	1.98 seconds
Started	Aug 27 04:34:40 AM UTC 24
Finished	Aug 27 04:34:43 AM UTC 24
Peak memory	209920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758241249 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.758241249
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.552147713
Short name	T914
Test name
Test status
Simulation time	308721903 ps
CPU time	1.34 seconds
Started	Aug 27 04:34:40 AM UTC 24
Finished	Aug 27 04:34:43 AM UTC 24
Peak memory	210280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552147713 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.552147713
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.113890019
Short name	T917
Test name
Test status
Simulation time	332344616 ps
CPU time	1.46 seconds
Started	Aug 27 04:34:42 AM UTC 24
Finished	Aug 27 04:34:44 AM UTC 24
Peak memory	210280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113890019 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.113890019
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2980375624
Short name	T810
Test name
Test status
Simulation time	421816292 ps
CPU time	3.75 seconds
Started	Aug 27 04:33:27 AM UTC 24
Finished	Aug 27 04:33:31 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2980375624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_cs r_mem_rw_with_rand_reset.2980375624
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3058920777
Short name	T134
Test name
Test status
Simulation time	327737907 ps
CPU time	1.72 seconds
Started	Aug 27 04:33:25 AM UTC 24
Finished	Aug 27 04:33:28 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058920777 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3058920777
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.3238737700
Short name	T808
Test name
Test status
Simulation time	333824151 ps
CPU time	1.75 seconds
Started	Aug 27 04:33:24 AM UTC 24
Finished	Aug 27 04:33:27 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238737700 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3238737700
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3030697295
Short name	T809
Test name
Test status
Simulation time	1967433393 ps
CPU time	2.31 seconds
Started	Aug 27 04:33:25 AM UTC 24
Finished	Aug 27 04:33:29 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030697295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.3030697295
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.608651959
Short name	T94
Test name
Test status
Simulation time	494826939 ps
CPU time	2.85 seconds
Started	Aug 27 04:33:22 AM UTC 24
Finished	Aug 27 04:33:26 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608651959 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.608651959
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.421657619
Short name	T384
Test name
Test status
Simulation time	4903375804 ps
CPU time	24.37 seconds
Started	Aug 27 04:33:23 AM UTC 24
Finished	Aug 27 04:33:49 AM UTC 24
Peak memory	211508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421657619 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.421657619
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.627076187
Short name	T815
Test name
Test status
Simulation time	439136002 ps
CPU time	2.29 seconds
Started	Aug 27 04:33:32 AM UTC 24
Finished	Aug 27 04:33:35 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=627076187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr _mem_rw_with_rand_reset.627076187
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2611839694
Short name	T812
Test name
Test status
Simulation time	551761036 ps
CPU time	1.77 seconds
Started	Aug 27 04:33:29 AM UTC 24
Finished	Aug 27 04:33:32 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611839694 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2611839694
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.2707399627
Short name	T814
Test name
Test status
Simulation time	514379996 ps
CPU time	3.03 seconds
Started	Aug 27 04:33:29 AM UTC 24
Finished	Aug 27 04:33:33 AM UTC 24
Peak memory	211176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707399627 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2707399627
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3863231545
Short name	T821
Test name
Test status
Simulation time	5158215979 ps
CPU time	13.07 seconds
Started	Aug 27 04:33:30 AM UTC 24
Finished	Aug 27 04:33:44 AM UTC 24
Peak memory	211528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863231545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.3863231545
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1166756038
Short name	T813
Test name
Test status
Simulation time	381059183 ps
CPU time	3.13 seconds
Started	Aug 27 04:33:28 AM UTC 24
Finished	Aug 27 04:33:32 AM UTC 24
Peak memory	211360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166756038 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1166756038
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1328214130
Short name	T833
Test name
Test status
Simulation time	4514202384 ps
CPU time	26.68 seconds
Started	Aug 27 04:33:29 AM UTC 24
Finished	Aug 27 04:33:57 AM UTC 24
Peak memory	211624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328214130 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.1328214130
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1256753199
Short name	T819
Test name
Test status
Simulation time	456590723 ps
CPU time	3.47 seconds
Started	Aug 27 04:33:36 AM UTC 24
Finished	Aug 27 04:33:41 AM UTC 24
Peak memory	211268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1256753199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_cs r_mem_rw_with_rand_reset.1256753199
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3949847863
Short name	T124
Test name
Test status
Simulation time	480778160 ps
CPU time	1.24 seconds
Started	Aug 27 04:33:33 AM UTC 24
Finished	Aug 27 04:33:36 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949847863 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3949847863
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1674655125
Short name	T817
Test name
Test status
Simulation time	387207594 ps
CPU time	2.71 seconds
Started	Aug 27 04:33:33 AM UTC 24
Finished	Aug 27 04:33:37 AM UTC 24
Peak memory	211180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674655125 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1674655125
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2791306452
Short name	T831
Test name
Test status
Simulation time	4031939434 ps
CPU time	18.47 seconds
Started	Aug 27 04:33:35 AM UTC 24
Finished	Aug 27 04:33:55 AM UTC 24
Peak memory	211560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791306452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.2791306452
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.141262388
Short name	T816
Test name
Test status
Simulation time	707283668 ps
CPU time	2.94 seconds
Started	Aug 27 04:33:32 AM UTC 24
Finished	Aug 27 04:33:36 AM UTC 24
Peak memory	221440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141262388 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.141262388
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3618585809
Short name	T832
Test name
Test status
Simulation time	8563455852 ps
CPU time	21.78 seconds
Started	Aug 27 04:33:33 AM UTC 24
Finished	Aug 27 04:33:56 AM UTC 24
Peak memory	211616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618585809 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.3618585809
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1132537968
Short name	T823
Test name
Test status
Simulation time	540757055 ps
CPU time	2.16 seconds
Started	Aug 27 04:33:42 AM UTC 24
Finished	Aug 27 04:33:45 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1132537968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs r_mem_rw_with_rand_reset.1132537968
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1447995899
Short name	T822
Test name
Test status
Simulation time	329210266 ps
CPU time	2.79 seconds
Started	Aug 27 04:33:41 AM UTC 24
Finished	Aug 27 04:33:45 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447995899 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1447995899
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.695886477
Short name	T820
Test name
Test status
Simulation time	505125879 ps
CPU time	3.63 seconds
Started	Aug 27 04:33:38 AM UTC 24
Finished	Aug 27 04:33:42 AM UTC 24
Peak memory	211272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695886477 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.695886477
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.982284096
Short name	T827
Test name
Test status
Simulation time	4987419060 ps
CPU time	8.73 seconds
Started	Aug 27 04:33:42 AM UTC 24
Finished	Aug 27 04:33:52 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982284096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.982284096
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2054701782
Short name	T818
Test name
Test status
Simulation time	552055107 ps
CPU time	3.09 seconds
Started	Aug 27 04:33:36 AM UTC 24
Finished	Aug 27 04:33:41 AM UTC 24
Peak memory	227596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054701782 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2054701782
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3254723338
Short name	T826
Test name
Test status
Simulation time	464485697 ps
CPU time	1.72 seconds
Started	Aug 27 04:33:47 AM UTC 24
Finished	Aug 27 04:33:50 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3254723338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs r_mem_rw_with_rand_reset.3254723338
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4119092566
Short name	T127
Test name
Test status
Simulation time	474258963 ps
CPU time	3.56 seconds
Started	Aug 27 04:33:46 AM UTC 24
Finished	Aug 27 04:33:51 AM UTC 24
Peak memory	211196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119092566 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4119092566
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.268886400
Short name	T825
Test name
Test status
Simulation time	392608568 ps
CPU time	2.72 seconds
Started	Aug 27 04:33:45 AM UTC 24
Finished	Aug 27 04:33:49 AM UTC 24
Peak memory	211232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268886400 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.268886400
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2908158394
Short name	T847
Test name
Test status
Simulation time	4378289898 ps
CPU time	19.8 seconds
Started	Aug 27 04:33:46 AM UTC 24
Finished	Aug 27 04:34:07 AM UTC 24
Peak memory	211560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908158394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.2908158394
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2502969667
Short name	T824
Test name
Test status
Simulation time	684066362 ps
CPU time	2.64 seconds
Started	Aug 27 04:33:43 AM UTC 24
Finished	Aug 27 04:33:47 AM UTC 24
Peak memory	211432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502969667 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2502969667
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1946180945
Short name	T811
Test name
Test status
Simulation time	4449369060 ps
CPU time	7.16 seconds
Started	Aug 27 04:33:45 AM UTC 24
Finished	Aug 27 04:33:53 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946180945 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.1946180945
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1516684543
Short name	T1
Test name
Test status
Simulation time	417110582 ps
CPU time	0.9 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:36:44 AM UTC 24
Peak memory	210628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516684543 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1516684543
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.371727672
Short name	T260
Test name
Test status
Simulation time	440915041952 ps
CPU time	964.1 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:52:58 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371727672 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.371727672
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2388843714
Short name	T145
Test name
Test status
Simulation time	318213558264 ps
CPU time	283.33 seconds
Started	Aug 27 05:36:39 AM UTC 24
Finished	Aug 27 05:41:27 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388843714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2388843714
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3703863232
Short name	T56
Test name
Test status
Simulation time	155009002889 ps
CPU time	314.71 seconds
Started	Aug 27 05:36:39 AM UTC 24
Finished	Aug 27 05:41:58 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703863232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.3703863232
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.256537911
Short name	T246
Test name
Test status
Simulation time	167632157397 ps
CPU time	617.64 seconds
Started	Aug 27 05:36:38 AM UTC 24
Finished	Aug 27 05:47:04 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256537911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.256537911
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.2275274334
Short name	T397
Test name
Test status
Simulation time	323731950580 ps
CPU time	516.67 seconds
Started	Aug 27 05:36:38 AM UTC 24
Finished	Aug 27 05:45:21 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275274334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.2275274334
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.32382049
Short name	T247
Test name
Test status
Simulation time	178166320593 ps
CPU time	568.55 seconds
Started	Aug 27 05:36:40 AM UTC 24
Finished	Aug 27 05:46:15 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32382049 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.32382049
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.3479213425
Short name	T29
Test name
Test status
Simulation time	28627148615 ps
CPU time	78.25 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:38:05 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479213425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3479213425
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.4087959500
Short name	T5
Test name
Test status
Simulation time	3461652527 ps
CPU time	7.45 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:36:53 AM UTC 24
Peak memory	211532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087959500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4087959500
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.3602668573
Short name	T65
Test name
Test status
Simulation time	8078478091 ps
CPU time	15.14 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:37:08 AM UTC 24
Peak memory	243488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602668573 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3602668573
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.2009798261
Short name	T7
Test name
Test status
Simulation time	5929953625 ps
CPU time	14.4 seconds
Started	Aug 27 05:36:38 AM UTC 24
Finished	Aug 27 05:36:55 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009798261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2009798261
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1491823874
Short name	T97
Test name
Test status
Simulation time	87401772754 ps
CPU time	93.36 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:38:20 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491823874 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.1491823874
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3266083317
Short name	T242
Test name
Test status
Simulation time	492475472222 ps
CPU time	1231.08 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:57:38 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266083317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3266083317
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3593731389
Short name	T454
Test name
Test status
Simulation time	492561999242 ps
CPU time	1345.04 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:59:33 AM UTC 24
Peak memory	211528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593731389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.3593731389
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.2430463149
Short name	T280
Test name
Test status
Simulation time	325668817702 ps
CPU time	1152.52 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:56:20 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430463149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2430463149
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.740128352
Short name	T216
Test name
Test status
Simulation time	331132237555 ps
CPU time	839.81 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:51:03 AM UTC 24
Peak memory	211172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740128352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.740128352
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3878320906
Short name	T162
Test name
Test status
Simulation time	348586152450 ps
CPU time	959.94 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:53:05 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878320906 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.3878320906
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3230756453
Short name	T23
Test name
Test status
Simulation time	217739274089 ps
CPU time	127.54 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:39:05 AM UTC 24
Peak memory	211788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230756453 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.3230756453
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.1144480726
Short name	T76
Test name
Test status
Simulation time	104098223594 ps
CPU time	443.89 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:44:23 AM UTC 24
Peak memory	211784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144480726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1144480726
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.890916105
Short name	T28
Test name
Test status
Simulation time	22332411293 ps
CPU time	52.04 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:37:56 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890916105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.890916105
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3279353423
Short name	T66
Test name
Test status
Simulation time	8009551718 ps
CPU time	22.26 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:37:12 AM UTC 24
Peak memory	243484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279353423 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3279353423
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.2877708843
Short name	T10
Test name
Test status
Simulation time	6001128114 ps
CPU time	3.74 seconds
Started	Aug 27 05:36:42 AM UTC 24
Finished	Aug 27 05:37:00 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877708843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2877708843
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2578148299
Short name	T14
Test name
Test status
Simulation time	5931747661 ps
CPU time	27.68 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:37:31 AM UTC 24
Peak memory	222076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2578148299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.adc_ctrl_stress_all_with_rand_reset.2578148299
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2042427895
Short name	T404
Test name
Test status
Simulation time	505356451 ps
CPU time	2.99 seconds
Started	Aug 27 05:46:21 AM UTC 24
Finished	Aug 27 05:46:25 AM UTC 24
Peak memory	211544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042427895 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2042427895
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.3976791846
Short name	T185
Test name
Test status
Simulation time	375332657477 ps
CPU time	254.31 seconds
Started	Aug 27 05:45:57 AM UTC 24
Finished	Aug 27 05:50:15 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976791846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3976791846
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.193829937
Short name	T282
Test name
Test status
Simulation time	327521413954 ps
CPU time	814.8 seconds
Started	Aug 27 05:45:23 AM UTC 24
Finished	Aug 27 05:59:06 AM UTC 24
Peak memory	211632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193829937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.193829937
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.974944839
Short name	T417
Test name
Test status
Simulation time	165235816751 ps
CPU time	395.07 seconds
Started	Aug 27 05:45:25 AM UTC 24
Finished	Aug 27 05:52:04 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974944839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.974944839
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2218828111
Short name	T240
Test name
Test status
Simulation time	490478538836 ps
CPU time	576.2 seconds
Started	Aug 27 05:45:13 AM UTC 24
Finished	Aug 27 05:54:55 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218828111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2218828111
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.2648297455
Short name	T412
Test name
Test status
Simulation time	324043857695 ps
CPU time	357.35 seconds
Started	Aug 27 05:45:20 AM UTC 24
Finished	Aug 27 05:51:22 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648297455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.2648297455
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3757758508
Short name	T410
Test name
Test status
Simulation time	403567864492 ps
CPU time	280.05 seconds
Started	Aug 27 05:45:26 AM UTC 24
Finished	Aug 27 05:50:09 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757758508 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.3757758508
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.905304353
Short name	T234
Test name
Test status
Simulation time	74669169025 ps
CPU time	408.5 seconds
Started	Aug 27 05:46:05 AM UTC 24
Finished	Aug 27 05:52:58 AM UTC 24
Peak memory	211884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905304353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.905304353
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.4137886256
Short name	T406
Test name
Test status
Simulation time	33265733848 ps
CPU time	52.26 seconds
Started	Aug 27 05:46:02 AM UTC 24
Finished	Aug 27 05:46:56 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137886256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4137886256
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.2838163669
Short name	T402
Test name
Test status
Simulation time	2879795770 ps
CPU time	3.64 seconds
Started	Aug 27 05:45:57 AM UTC 24
Finished	Aug 27 05:46:02 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838163669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2838163669
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1243679676
Short name	T399
Test name
Test status
Simulation time	6002583518 ps
CPU time	21.92 seconds
Started	Aug 27 05:45:01 AM UTC 24
Finished	Aug 27 05:45:24 AM UTC 24
Peak memory	211296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243679676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1243679676
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1723816871
Short name	T146
Test name
Test status
Simulation time	4897544382 ps
CPU time	12.52 seconds
Started	Aug 27 05:46:15 AM UTC 24
Finished	Aug 27 05:46:29 AM UTC 24
Peak memory	221964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1723816871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.adc_ctrl_stress_all_with_rand_reset.1723816871
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.628752259
Short name	T199
Test name
Test status
Simulation time	396375775 ps
CPU time	1.35 seconds
Started	Aug 27 05:48:49 AM UTC 24
Finished	Aug 27 05:48:52 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628752259 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.628752259
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.4118945863
Short name	T255
Test name
Test status
Simulation time	346815624670 ps
CPU time	594.88 seconds
Started	Aug 27 05:47:48 AM UTC 24
Finished	Aug 27 05:57:49 AM UTC 24
Peak memory	211604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118945863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.4118945863
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.2550962013
Short name	T241
Test name
Test status
Simulation time	160541125616 ps
CPU time	411.61 seconds
Started	Aug 27 05:46:30 AM UTC 24
Finished	Aug 27 05:53:26 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550962013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2550962013
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.990821105
Short name	T456
Test name
Test status
Simulation time	332387736646 ps
CPU time	798.12 seconds
Started	Aug 27 05:46:57 AM UTC 24
Finished	Aug 27 06:00:23 AM UTC 24
Peak memory	211596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990821105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.990821105
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.3892373175
Short name	T413
Test name
Test status
Simulation time	325369321316 ps
CPU time	300.88 seconds
Started	Aug 27 05:46:30 AM UTC 24
Finished	Aug 27 05:51:34 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892373175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.3892373175
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1566498488
Short name	T472
Test name
Test status
Simulation time	380764791025 ps
CPU time	909.12 seconds
Started	Aug 27 05:47:11 AM UTC 24
Finished	Aug 27 06:02:29 AM UTC 24
Peak memory	211444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566498488 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.1566498488
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.1214451090
Short name	T198
Test name
Test status
Simulation time	28319876066 ps
CPU time	33.01 seconds
Started	Aug 27 05:48:14 AM UTC 24
Finished	Aug 27 05:48:48 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214451090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1214451090
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.3841446562
Short name	T194
Test name
Test status
Simulation time	2855434790 ps
CPU time	4.55 seconds
Started	Aug 27 05:48:08 AM UTC 24
Finished	Aug 27 05:48:14 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841446562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3841446562
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.726084963
Short name	T405
Test name
Test status
Simulation time	5862401592 ps
CPU time	5.93 seconds
Started	Aug 27 05:46:21 AM UTC 24
Finished	Aug 27 05:46:28 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726084963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.726084963
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1677075149
Short name	T268
Test name
Test status
Simulation time	354872972726 ps
CPU time	593.48 seconds
Started	Aug 27 05:48:46 AM UTC 24
Finished	Aug 27 05:58:46 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677075149 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.1677075149
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.977495285
Short name	T197
Test name
Test status
Simulation time	4871202523 ps
CPU time	6.62 seconds
Started	Aug 27 05:48:38 AM UTC 24
Finished	Aug 27 05:48:46 AM UTC 24
Peak memory	211608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=977495285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.977495285
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.911447761
Short name	T211
Test name
Test status
Simulation time	307207634 ps
CPU time	2.06 seconds
Started	Aug 27 05:50:21 AM UTC 24
Finished	Aug 27 05:50:24 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911447761 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.911447761
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.4044590668
Short name	T315
Test name
Test status
Simulation time	202033643167 ps
CPU time	452.76 seconds
Started	Aug 27 05:49:55 AM UTC 24
Finished	Aug 27 05:57:33 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044590668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.4044590668
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.3750024056
Short name	T262
Test name
Test status
Simulation time	167934412715 ps
CPU time	167.97 seconds
Started	Aug 27 05:49:09 AM UTC 24
Finished	Aug 27 05:52:00 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750024056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3750024056
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2702764749
Short name	T425
Test name
Test status
Simulation time	490364603936 ps
CPU time	277.14 seconds
Started	Aug 27 05:49:20 AM UTC 24
Finished	Aug 27 05:54:01 AM UTC 24
Peak memory	211668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702764749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.2702764749
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.1892386847
Short name	T445
Test name
Test status
Simulation time	330946291164 ps
CPU time	555.53 seconds
Started	Aug 27 05:48:57 AM UTC 24
Finished	Aug 27 05:58:18 AM UTC 24
Peak memory	211564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892386847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1892386847
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.1702959085
Short name	T447
Test name
Test status
Simulation time	163943296472 ps
CPU time	555.25 seconds
Started	Aug 27 05:49:06 AM UTC 24
Finished	Aug 27 05:58:27 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702959085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.1702959085
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.491741461
Short name	T172
Test name
Test status
Simulation time	576662674312 ps
CPU time	581.03 seconds
Started	Aug 27 05:49:27 AM UTC 24
Finished	Aug 27 05:59:14 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491741461 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.491741461
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3442664109
Short name	T473
Test name
Test status
Simulation time	395252378935 ps
CPU time	777.06 seconds
Started	Aug 27 05:49:35 AM UTC 24
Finished	Aug 27 06:02:40 AM UTC 24
Peak memory	211728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442664109 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.3442664109
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2882334334
Short name	T224
Test name
Test status
Simulation time	93053865202 ps
CPU time	658.58 seconds
Started	Aug 27 05:50:10 AM UTC 24
Finished	Aug 27 06:01:16 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882334334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2882334334
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1133942420
Short name	T414
Test name
Test status
Simulation time	36290811956 ps
CPU time	92.13 seconds
Started	Aug 27 05:50:02 AM UTC 24
Finished	Aug 27 05:51:36 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133942420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1133942420
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1819503804
Short name	T411
Test name
Test status
Simulation time	4775770587 ps
CPU time	10 seconds
Started	Aug 27 05:50:01 AM UTC 24
Finished	Aug 27 05:50:12 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819503804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1819503804
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.2373356144
Short name	T407
Test name
Test status
Simulation time	5942099539 ps
CPU time	11.22 seconds
Started	Aug 27 05:48:53 AM UTC 24
Finished	Aug 27 05:49:05 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373356144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2373356144
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1080356302
Short name	T171
Test name
Test status
Simulation time	8740851809 ps
CPU time	4.94 seconds
Started	Aug 27 05:50:14 AM UTC 24
Finished	Aug 27 05:50:19 AM UTC 24
Peak memory	211652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1080356302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.adc_ctrl_stress_all_with_rand_reset.1080356302
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.1848896322
Short name	T416
Test name
Test status
Simulation time	507960314 ps
CPU time	1.32 seconds
Started	Aug 27 05:52:00 AM UTC 24
Finished	Aug 27 05:52:02 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848896322 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1848896322
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.2351217263
Short name	T151
Test name
Test status
Simulation time	490495476083 ps
CPU time	558.33 seconds
Started	Aug 27 05:51:09 AM UTC 24
Finished	Aug 27 06:00:34 AM UTC 24
Peak memory	211528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351217263 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.2351217263
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1100186057
Short name	T158
Test name
Test status
Simulation time	197288221003 ps
CPU time	98.7 seconds
Started	Aug 27 05:51:22 AM UTC 24
Finished	Aug 27 05:53:03 AM UTC 24
Peak memory	211464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100186057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1100186057
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3261623120
Short name	T202
Test name
Test status
Simulation time	325684405977 ps
CPU time	241.74 seconds
Started	Aug 27 05:50:33 AM UTC 24
Finished	Aug 27 05:54:38 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261623120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3261623120
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1927834038
Short name	T423
Test name
Test status
Simulation time	337310485008 ps
CPU time	191.46 seconds
Started	Aug 27 05:50:43 AM UTC 24
Finished	Aug 27 05:53:57 AM UTC 24
Peak memory	211456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927834038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.1927834038
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.678046384
Short name	T448
Test name
Test status
Simulation time	168286146061 ps
CPU time	493.17 seconds
Started	Aug 27 05:50:29 AM UTC 24
Finished	Aug 27 05:58:48 AM UTC 24
Peak memory	211648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678046384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.678046384
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2910958191
Short name	T322
Test name
Test status
Simulation time	367782422724 ps
CPU time	621.23 seconds
Started	Aug 27 05:50:56 AM UTC 24
Finished	Aug 27 06:01:24 AM UTC 24
Peak memory	211544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910958191 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.2910958191
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.585249884
Short name	T420
Test name
Test status
Simulation time	192544297025 ps
CPU time	133.54 seconds
Started	Aug 27 05:51:04 AM UTC 24
Finished	Aug 27 05:53:20 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585249884 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.585249884
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.1249926896
Short name	T389
Test name
Test status
Simulation time	111666079433 ps
CPU time	478.28 seconds
Started	Aug 27 05:51:37 AM UTC 24
Finished	Aug 27 05:59:40 AM UTC 24
Peak memory	211768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249926896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1249926896
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.2868202684
Short name	T419
Test name
Test status
Simulation time	35400609461 ps
CPU time	45.83 seconds
Started	Aug 27 05:51:36 AM UTC 24
Finished	Aug 27 05:52:23 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868202684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2868202684
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.929063578
Short name	T415
Test name
Test status
Simulation time	3407003944 ps
CPU time	9.6 seconds
Started	Aug 27 05:51:34 AM UTC 24
Finished	Aug 27 05:51:45 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929063578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.929063578
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.830331353
Short name	T213
Test name
Test status
Simulation time	6084888929 ps
CPU time	2.58 seconds
Started	Aug 27 05:50:25 AM UTC 24
Finished	Aug 27 05:50:28 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830331353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.830331353
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1652322587
Short name	T270
Test name
Test status
Simulation time	25778712878 ps
CPU time	39.28 seconds
Started	Aug 27 05:51:47 AM UTC 24
Finished	Aug 27 05:52:27 AM UTC 24
Peak memory	228088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1652322587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.adc_ctrl_stress_all_with_rand_reset.1652322587
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.480617912
Short name	T422
Test name
Test status
Simulation time	326049620 ps
CPU time	2.18 seconds
Started	Aug 27 05:53:36 AM UTC 24
Finished	Aug 27 05:53:39 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480617912 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.480617912
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.186411344
Short name	T269
Test name
Test status
Simulation time	499283572585 ps
CPU time	203.73 seconds
Started	Aug 27 05:52:59 AM UTC 24
Finished	Aug 27 05:56:26 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186411344 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.186411344
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1686000204
Short name	T274
Test name
Test status
Simulation time	337730250145 ps
CPU time	779.85 seconds
Started	Aug 27 05:53:04 AM UTC 24
Finished	Aug 27 06:06:12 AM UTC 24
Peak memory	211456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686000204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1686000204
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.4128678265
Short name	T442
Test name
Test status
Simulation time	324360960376 ps
CPU time	328.06 seconds
Started	Aug 27 05:52:28 AM UTC 24
Finished	Aug 27 05:58:01 AM UTC 24
Peak memory	211396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128678265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.4128678265
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.3078675238
Short name	T530
Test name
Test status
Simulation time	502690181238 ps
CPU time	1256.67 seconds
Started	Aug 27 05:52:05 AM UTC 24
Finished	Aug 27 06:13:13 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078675238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3078675238
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.546213182
Short name	T428
Test name
Test status
Simulation time	498838542975 ps
CPU time	162.35 seconds
Started	Aug 27 05:52:11 AM UTC 24
Finished	Aug 27 05:54:56 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546213182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.546213182
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.1295916479
Short name	T320
Test name
Test status
Simulation time	188293943665 ps
CPU time	114.35 seconds
Started	Aug 27 05:52:37 AM UTC 24
Finished	Aug 27 05:54:34 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295916479 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.1295916479
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3399941194
Short name	T431
Test name
Test status
Simulation time	197988221216 ps
CPU time	169.81 seconds
Started	Aug 27 05:52:58 AM UTC 24
Finished	Aug 27 05:55:51 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399941194 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.3399941194
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2332939975
Short name	T225
Test name
Test status
Simulation time	91120376450 ps
CPU time	536.92 seconds
Started	Aug 27 05:53:23 AM UTC 24
Finished	Aug 27 06:02:25 AM UTC 24
Peak memory	211972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332939975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2332939975
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1520306220
Short name	T434
Test name
Test status
Simulation time	41636213011 ps
CPU time	161.14 seconds
Started	Aug 27 05:53:21 AM UTC 24
Finished	Aug 27 05:56:04 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520306220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1520306220
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.2657351838
Short name	T421
Test name
Test status
Simulation time	4265734183 ps
CPU time	17.28 seconds
Started	Aug 27 05:53:06 AM UTC 24
Finished	Aug 27 05:53:24 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657351838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2657351838
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.1789322138
Short name	T418
Test name
Test status
Simulation time	5912956034 ps
CPU time	6.3 seconds
Started	Aug 27 05:52:03 AM UTC 24
Finished	Aug 27 05:52:10 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789322138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1789322138
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.4107510818
Short name	T429
Test name
Test status
Simulation time	319918031 ps
CPU time	1.18 seconds
Started	Aug 27 05:54:56 AM UTC 24
Finished	Aug 27 05:54:58 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107510818 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.4107510818
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1167039064
Short name	T166
Test name
Test status
Simulation time	336481704413 ps
CPU time	307.09 seconds
Started	Aug 27 05:54:20 AM UTC 24
Finished	Aug 27 05:59:31 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167039064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1167039064
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.556811344
Short name	T287
Test name
Test status
Simulation time	486724528493 ps
CPU time	1282.55 seconds
Started	Aug 27 05:54:00 AM UTC 24
Finished	Aug 27 06:15:35 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556811344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.556811344
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.817875512
Short name	T444
Test name
Test status
Simulation time	332607751205 ps
CPU time	247.24 seconds
Started	Aug 27 05:54:01 AM UTC 24
Finished	Aug 27 05:58:12 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817875512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.817875512
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.2883104110
Short name	T176
Test name
Test status
Simulation time	489809053075 ps
CPU time	1513.19 seconds
Started	Aug 27 05:53:49 AM UTC 24
Finished	Aug 27 06:19:17 AM UTC 24
Peak memory	212544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883104110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2883104110
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.1203336295
Short name	T449
Test name
Test status
Simulation time	494265897149 ps
CPU time	296.41 seconds
Started	Aug 27 05:53:58 AM UTC 24
Finished	Aug 27 05:58:58 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203336295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.1203336295
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.443889761
Short name	T308
Test name
Test status
Simulation time	199314941166 ps
CPU time	458.88 seconds
Started	Aug 27 05:54:07 AM UTC 24
Finished	Aug 27 06:01:52 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443889761 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.443889761
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1874460278
Short name	T439
Test name
Test status
Simulation time	410982570913 ps
CPU time	184.73 seconds
Started	Aug 27 05:54:09 AM UTC 24
Finished	Aug 27 05:57:17 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874460278 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.1874460278
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.1173570004
Short name	T390
Test name
Test status
Simulation time	113750300098 ps
CPU time	668.04 seconds
Started	Aug 27 05:54:39 AM UTC 24
Finished	Aug 27 06:05:54 AM UTC 24
Peak memory	211768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173570004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1173570004
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.2416807621
Short name	T433
Test name
Test status
Simulation time	35612555799 ps
CPU time	85.93 seconds
Started	Aug 27 05:54:36 AM UTC 24
Finished	Aug 27 05:56:04 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416807621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2416807621
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.2729432047
Short name	T427
Test name
Test status
Simulation time	4994791150 ps
CPU time	6.33 seconds
Started	Aug 27 05:54:35 AM UTC 24
Finished	Aug 27 05:54:42 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729432047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2729432047
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.550029144
Short name	T426
Test name
Test status
Simulation time	5984806442 ps
CPU time	25.46 seconds
Started	Aug 27 05:53:40 AM UTC 24
Finished	Aug 27 05:54:07 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550029144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.550029144
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.2673992171
Short name	T328
Test name
Test status
Simulation time	171319266405 ps
CPU time	535.72 seconds
Started	Aug 27 05:54:51 AM UTC 24
Finished	Aug 27 06:03:53 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673992171 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.2673992171
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1167901137
Short name	T311
Test name
Test status
Simulation time	18895506975 ps
CPU time	6.38 seconds
Started	Aug 27 05:54:43 AM UTC 24
Finished	Aug 27 05:54:50 AM UTC 24
Peak memory	221676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1167901137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.adc_ctrl_stress_all_with_rand_reset.1167901137
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.684155088
Short name	T437
Test name
Test status
Simulation time	338413087 ps
CPU time	1.18 seconds
Started	Aug 27 05:56:51 AM UTC 24
Finished	Aug 27 05:56:53 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684155088 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.684155088
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.888238218
Short name	T283
Test name
Test status
Simulation time	166832152682 ps
CPU time	27.81 seconds
Started	Aug 27 05:56:05 AM UTC 24
Finished	Aug 27 05:56:34 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888238218 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.888238218
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.678434503
Short name	T436
Test name
Test status
Simulation time	164620686530 ps
CPU time	80.52 seconds
Started	Aug 27 05:55:28 AM UTC 24
Finished	Aug 27 05:56:51 AM UTC 24
Peak memory	211784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678434503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.678434503
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1039762836
Short name	T471
Test name
Test status
Simulation time	331063032262 ps
CPU time	427.56 seconds
Started	Aug 27 05:54:59 AM UTC 24
Finished	Aug 27 06:02:12 AM UTC 24
Peak memory	211500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039762836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1039762836
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.1826567953
Short name	T501
Test name
Test status
Simulation time	322642805801 ps
CPU time	751.22 seconds
Started	Aug 27 05:55:04 AM UTC 24
Finished	Aug 27 06:07:43 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826567953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.1826567953
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.497605584
Short name	T271
Test name
Test status
Simulation time	552377185906 ps
CPU time	431.52 seconds
Started	Aug 27 05:55:52 AM UTC 24
Finished	Aug 27 06:03:08 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497605584 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.497605584
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.4208230487
Short name	T534
Test name
Test status
Simulation time	619966290126 ps
CPU time	1093.19 seconds
Started	Aug 27 05:55:58 AM UTC 24
Finished	Aug 27 06:14:22 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208230487 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.4208230487
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.3989618917
Short name	T475
Test name
Test status
Simulation time	85088289336 ps
CPU time	373.61 seconds
Started	Aug 27 05:56:27 AM UTC 24
Finished	Aug 27 06:02:45 AM UTC 24
Peak memory	212032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989618917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3989618917
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.1991843488
Short name	T440
Test name
Test status
Simulation time	33307841329 ps
CPU time	51.44 seconds
Started	Aug 27 05:56:26 AM UTC 24
Finished	Aug 27 05:57:19 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991843488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1991843488
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.2818791853
Short name	T435
Test name
Test status
Simulation time	2998190586 ps
CPU time	2.92 seconds
Started	Aug 27 05:56:21 AM UTC 24
Finished	Aug 27 05:56:25 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818791853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2818791853
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.2509415123
Short name	T430
Test name
Test status
Simulation time	5842204393 ps
CPU time	7.09 seconds
Started	Aug 27 05:54:57 AM UTC 24
Finished	Aug 27 05:55:05 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509415123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2509415123
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1836936924
Short name	T51
Test name
Test status
Simulation time	9234028546 ps
CPU time	10.35 seconds
Started	Aug 27 05:56:35 AM UTC 24
Finished	Aug 27 05:56:46 AM UTC 24
Peak memory	211600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1836936924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.adc_ctrl_stress_all_with_rand_reset.1836936924
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.1946967519
Short name	T443
Test name
Test status
Simulation time	306266713 ps
CPU time	1.18 seconds
Started	Aug 27 05:58:01 AM UTC 24
Finished	Aug 27 05:58:03 AM UTC 24
Peak memory	210340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946967519 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1946967519
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.1947546541
Short name	T323
Test name
Test status
Simulation time	159858489748 ps
CPU time	363.81 seconds
Started	Aug 27 05:57:18 AM UTC 24
Finished	Aug 27 06:03:26 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947546541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1947546541
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.338667822
Short name	T482
Test name
Test status
Simulation time	492473733811 ps
CPU time	371.04 seconds
Started	Aug 27 05:57:20 AM UTC 24
Finished	Aug 27 06:03:35 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338667822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.338667822
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.2719305769
Short name	T174
Test name
Test status
Simulation time	329715632079 ps
CPU time	936.82 seconds
Started	Aug 27 05:57:03 AM UTC 24
Finished	Aug 27 06:12:50 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719305769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2719305769
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.79668189
Short name	T464
Test name
Test status
Simulation time	330591605632 ps
CPU time	254.6 seconds
Started	Aug 27 05:57:11 AM UTC 24
Finished	Aug 27 06:01:29 AM UTC 24
Peak memory	211400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79668189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.79668189
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.48885125
Short name	T288
Test name
Test status
Simulation time	183536084449 ps
CPU time	227.38 seconds
Started	Aug 27 05:57:23 AM UTC 24
Finished	Aug 27 06:01:13 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48885125 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.48885125
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4277631756
Short name	T499
Test name
Test status
Simulation time	392522042085 ps
CPU time	585.66 seconds
Started	Aug 27 05:57:28 AM UTC 24
Finished	Aug 27 06:07:20 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277631756 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.4277631756
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.2268746399
Short name	T486
Test name
Test status
Simulation time	69356833067 ps
CPU time	384.74 seconds
Started	Aug 27 05:57:51 AM UTC 24
Finished	Aug 27 06:04:20 AM UTC 24
Peak memory	211760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268746399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2268746399
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.2629624634
Short name	T455
Test name
Test status
Simulation time	46195068992 ps
CPU time	103.5 seconds
Started	Aug 27 05:57:50 AM UTC 24
Finished	Aug 27 05:59:35 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629624634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2629624634
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3239738797
Short name	T441
Test name
Test status
Simulation time	5454139530 ps
CPU time	6.45 seconds
Started	Aug 27 05:57:43 AM UTC 24
Finished	Aug 27 05:57:51 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239738797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3239738797
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.788369509
Short name	T438
Test name
Test status
Simulation time	5964574905 ps
CPU time	7.41 seconds
Started	Aug 27 05:56:54 AM UTC 24
Finished	Aug 27 05:57:03 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788369509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.788369509
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.537187636
Short name	T497
Test name
Test status
Simulation time	203553565852 ps
CPU time	521 seconds
Started	Aug 27 05:57:57 AM UTC 24
Finished	Aug 27 06:06:44 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537187636 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.537187636
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3341818994
Short name	T33
Test name
Test status
Simulation time	5028633221 ps
CPU time	40.31 seconds
Started	Aug 27 05:57:53 AM UTC 24
Finished	Aug 27 05:58:35 AM UTC 24
Peak memory	221752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3341818994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.adc_ctrl_stress_all_with_rand_reset.3341818994
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.792310750
Short name	T452
Test name
Test status
Simulation time	314300902 ps
CPU time	2.1 seconds
Started	Aug 27 05:59:18 AM UTC 24
Finished	Aug 27 05:59:21 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792310750 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.792310750
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.1042059586
Short name	T292
Test name
Test status
Simulation time	343890105463 ps
CPU time	836.43 seconds
Started	Aug 27 05:58:47 AM UTC 24
Finished	Aug 27 06:12:51 AM UTC 24
Peak memory	211528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042059586 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.1042059586
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.3836052364
Short name	T372
Test name
Test status
Simulation time	165914830662 ps
CPU time	384.96 seconds
Started	Aug 27 05:58:19 AM UTC 24
Finished	Aug 27 06:04:49 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836052364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3836052364
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1894379693
Short name	T451
Test name
Test status
Simulation time	162744870757 ps
CPU time	50.88 seconds
Started	Aug 27 05:58:26 AM UTC 24
Finished	Aug 27 05:59:18 AM UTC 24
Peak memory	211592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894379693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.1894379693
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.1087089367
Short name	T568
Test name
Test status
Simulation time	500313300629 ps
CPU time	1248.16 seconds
Started	Aug 27 05:58:13 AM UTC 24
Finished	Aug 27 06:19:13 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087089367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.1087089367
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.3414612719
Short name	T495
Test name
Test status
Simulation time	179888737123 ps
CPU time	457.2 seconds
Started	Aug 27 05:58:28 AM UTC 24
Finished	Aug 27 06:06:10 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414612719 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.3414612719
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.290751905
Short name	T547
Test name
Test status
Simulation time	395862011115 ps
CPU time	1011.72 seconds
Started	Aug 27 05:58:36 AM UTC 24
Finished	Aug 27 06:15:37 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290751905 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.290751905
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.394744841
Short name	T517
Test name
Test status
Simulation time	100392368224 ps
CPU time	708.67 seconds
Started	Aug 27 05:59:07 AM UTC 24
Finished	Aug 27 06:11:03 AM UTC 24
Peak memory	211772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394744841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.394744841
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.4021195550
Short name	T459
Test name
Test status
Simulation time	46954534857 ps
CPU time	112.8 seconds
Started	Aug 27 05:58:59 AM UTC 24
Finished	Aug 27 06:00:54 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021195550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4021195550
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.2666975310
Short name	T450
Test name
Test status
Simulation time	4584865762 ps
CPU time	10.18 seconds
Started	Aug 27 05:58:57 AM UTC 24
Finished	Aug 27 05:59:08 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666975310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2666975310
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2572377814
Short name	T446
Test name
Test status
Simulation time	6066013964 ps
CPU time	19.63 seconds
Started	Aug 27 05:58:04 AM UTC 24
Finished	Aug 27 05:58:25 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572377814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2572377814
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.324241762
Short name	T297
Test name
Test status
Simulation time	328189363653 ps
CPU time	825.75 seconds
Started	Aug 27 05:59:15 AM UTC 24
Finished	Aug 27 06:13:09 AM UTC 24
Peak memory	211608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324241762 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.324241762
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.3951066884
Short name	T460
Test name
Test status
Simulation time	298335810 ps
CPU time	1.49 seconds
Started	Aug 27 06:00:54 AM UTC 24
Finished	Aug 27 06:00:57 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951066884 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3951066884
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.2765939845
Short name	T327
Test name
Test status
Simulation time	344251680855 ps
CPU time	182.51 seconds
Started	Aug 27 06:00:23 AM UTC 24
Finished	Aug 27 06:03:28 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765939845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2765939845
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.1803631414
Short name	T208
Test name
Test status
Simulation time	491279745312 ps
CPU time	867.18 seconds
Started	Aug 27 05:59:32 AM UTC 24
Finished	Aug 27 06:14:07 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803631414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1803631414
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1102900556
Short name	T466
Test name
Test status
Simulation time	169020979416 ps
CPU time	121.64 seconds
Started	Aug 27 05:59:34 AM UTC 24
Finished	Aug 27 06:01:38 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102900556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.1102900556
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.2432054247
Short name	T462
Test name
Test status
Simulation time	163284198721 ps
CPU time	99.49 seconds
Started	Aug 27 05:59:30 AM UTC 24
Finished	Aug 27 06:01:12 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432054247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.2432054247
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2473312008
Short name	T306
Test name
Test status
Simulation time	172935594363 ps
CPU time	524.92 seconds
Started	Aug 27 05:59:37 AM UTC 24
Finished	Aug 27 06:08:28 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473312008 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.2473312008
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4066491597
Short name	T526
Test name
Test status
Simulation time	196400411487 ps
CPU time	786.67 seconds
Started	Aug 27 05:59:41 AM UTC 24
Finished	Aug 27 06:12:56 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066491597 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.4066491597
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.3705452379
Short name	T78
Test name
Test status
Simulation time	95387898629 ps
CPU time	515.39 seconds
Started	Aug 27 06:00:35 AM UTC 24
Finished	Aug 27 06:09:16 AM UTC 24
Peak memory	211816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705452379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3705452379
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.2409899202
Short name	T465
Test name
Test status
Simulation time	36268753588 ps
CPU time	57.44 seconds
Started	Aug 27 06:00:32 AM UTC 24
Finished	Aug 27 06:01:31 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409899202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2409899202
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1089117929
Short name	T457
Test name
Test status
Simulation time	4746138359 ps
CPU time	2.31 seconds
Started	Aug 27 06:00:28 AM UTC 24
Finished	Aug 27 06:00:31 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089117929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1089117929
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.3209148472
Short name	T453
Test name
Test status
Simulation time	5566122202 ps
CPU time	6.35 seconds
Started	Aug 27 05:59:22 AM UTC 24
Finished	Aug 27 05:59:30 AM UTC 24
Peak memory	211220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209148472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3209148472
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.3588673976
Short name	T53
Test name
Test status
Simulation time	128726698745 ps
CPU time	377.29 seconds
Started	Aug 27 06:00:42 AM UTC 24
Finished	Aug 27 06:07:03 AM UTC 24
Peak memory	211764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588673976 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.3588673976
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2675762922
Short name	T362
Test name
Test status
Simulation time	2311551546 ps
CPU time	10.73 seconds
Started	Aug 27 06:00:42 AM UTC 24
Finished	Aug 27 06:00:54 AM UTC 24
Peak memory	211596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2675762922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.adc_ctrl_stress_all_with_rand_reset.2675762922
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.1905085230
Short name	T3
Test name
Test status
Simulation time	456363153 ps
CPU time	1.4 seconds
Started	Aug 27 05:36:48 AM UTC 24
Finished	Aug 27 05:36:51 AM UTC 24
Peak memory	209796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905085230 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1905085230
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.1700078062
Short name	T17
Test name
Test status
Simulation time	323259821397 ps
CPU time	62.59 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:37:52 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700078062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1700078062
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1457756773
Short name	T159
Test name
Test status
Simulation time	163029468309 ps
CPU time	170.53 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:39:42 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457756773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.1457756773
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.3988154516
Short name	T161
Test name
Test status
Simulation time	164296580042 ps
CPU time	549.93 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:46:04 AM UTC 24
Peak memory	211616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988154516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3988154516
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3147469945
Short name	T463
Test name
Test status
Simulation time	493959438663 ps
CPU time	1460.1 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 06:01:27 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147469945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.3147469945
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3720516694
Short name	T458
Test name
Test status
Simulation time	612084949663 ps
CPU time	1419.33 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 06:00:41 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720516694 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.3720516694
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3232299337
Short name	T195
Test name
Test status
Simulation time	138520646062 ps
CPU time	672.29 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:48:17 AM UTC 24
Peak memory	211836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232299337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3232299337
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1777368119
Short name	T147
Test name
Test status
Simulation time	43194229298 ps
CPU time	96.16 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:38:37 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777368119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1777368119
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.4057720399
Short name	T11
Test name
Test status
Simulation time	2995859395 ps
CPU time	2.15 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:37:02 AM UTC 24
Peak memory	211404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057720399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4057720399
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.2012254329
Short name	T4
Test name
Test status
Simulation time	5887297225 ps
CPU time	3.3 seconds
Started	Aug 27 05:36:45 AM UTC 24
Finished	Aug 27 05:36:53 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012254329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2012254329
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.125562195
Short name	T168
Test name
Test status
Simulation time	168517644791 ps
CPU time	209.31 seconds
Started	Aug 27 05:36:47 AM UTC 24
Finished	Aug 27 05:40:22 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125562195 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.125562195
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1908482676
Short name	T15
Test name
Test status
Simulation time	8000448378 ps
CPU time	44.74 seconds
Started	Aug 27 05:36:47 AM UTC 24
Finished	Aug 27 05:37:36 AM UTC 24
Peak memory	222076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1908482676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.adc_ctrl_stress_all_with_rand_reset.1908482676
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.1076741038
Short name	T468
Test name
Test status
Simulation time	457028499 ps
CPU time	1.31 seconds
Started	Aug 27 06:01:40 AM UTC 24
Finished	Aug 27 06:01:43 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076741038 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1076741038
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.1441155436
Short name	T155
Test name
Test status
Simulation time	488779796273 ps
CPU time	314.71 seconds
Started	Aug 27 06:01:13 AM UTC 24
Finished	Aug 27 06:06:31 AM UTC 24
Peak memory	211500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441155436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1441155436
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2331384061
Short name	T579
Test name
Test status
Simulation time	504005084987 ps
CPU time	1131.15 seconds
Started	Aug 27 06:01:14 AM UTC 24
Finished	Aug 27 06:20:16 AM UTC 24
Peak memory	212588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331384061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.2331384061
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.1912719839
Short name	T367
Test name
Test status
Simulation time	163647211459 ps
CPU time	34.4 seconds
Started	Aug 27 06:00:57 AM UTC 24
Finished	Aug 27 06:01:33 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912719839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1912719839
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.1092048729
Short name	T490
Test name
Test status
Simulation time	166405906925 ps
CPU time	220.99 seconds
Started	Aug 27 06:01:05 AM UTC 24
Finished	Aug 27 06:04:49 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092048729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.1092048729
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.775666471
Short name	T336
Test name
Test status
Simulation time	353371347263 ps
CPU time	849.31 seconds
Started	Aug 27 06:01:17 AM UTC 24
Finished	Aug 27 06:15:34 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775666471 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.775666471
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.845906823
Short name	T510
Test name
Test status
Simulation time	194084585058 ps
CPU time	486.35 seconds
Started	Aug 27 06:01:19 AM UTC 24
Finished	Aug 27 06:09:30 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845906823 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.845906823
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.3315835243
Short name	T220
Test name
Test status
Simulation time	73879802806 ps
CPU time	436.02 seconds
Started	Aug 27 06:01:34 AM UTC 24
Finished	Aug 27 06:08:56 AM UTC 24
Peak memory	211700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315835243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3315835243
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.48018966
Short name	T478
Test name
Test status
Simulation time	25987805269 ps
CPU time	97.92 seconds
Started	Aug 27 06:01:32 AM UTC 24
Finished	Aug 27 06:03:12 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48018966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.48018966
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.3859996323
Short name	T467
Test name
Test status
Simulation time	5383163505 ps
CPU time	7 seconds
Started	Aug 27 06:01:30 AM UTC 24
Finished	Aug 27 06:01:38 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859996323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3859996323
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.2167008485
Short name	T461
Test name
Test status
Simulation time	5684060542 ps
CPU time	8.79 seconds
Started	Aug 27 06:00:54 AM UTC 24
Finished	Aug 27 06:01:04 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167008485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2167008485
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.3888300909
Short name	T469
Test name
Test status
Simulation time	6999962181 ps
CPU time	7.75 seconds
Started	Aug 27 06:01:39 AM UTC 24
Finished	Aug 27 06:01:48 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888300909 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.3888300909
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2357890166
Short name	T35
Test name
Test status
Simulation time	5352007051 ps
CPU time	16.92 seconds
Started	Aug 27 06:01:38 AM UTC 24
Finished	Aug 27 06:01:56 AM UTC 24
Peak memory	211732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2357890166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.adc_ctrl_stress_all_with_rand_reset.2357890166
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.1235033365
Short name	T477
Test name
Test status
Simulation time	466435148 ps
CPU time	1.37 seconds
Started	Aug 27 06:03:07 AM UTC 24
Finished	Aug 27 06:03:09 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235033365 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1235033365
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.532415849
Short name	T317
Test name
Test status
Simulation time	176248409873 ps
CPU time	151.17 seconds
Started	Aug 27 06:02:26 AM UTC 24
Finished	Aug 27 06:05:00 AM UTC 24
Peak memory	211604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532415849 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.532415849
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.682713432
Short name	T267
Test name
Test status
Simulation time	351677872742 ps
CPU time	497.87 seconds
Started	Aug 27 06:02:29 AM UTC 24
Finished	Aug 27 06:10:52 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682713432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.682713432
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.3939323247
Short name	T258
Test name
Test status
Simulation time	167043735914 ps
CPU time	72.62 seconds
Started	Aug 27 06:01:52 AM UTC 24
Finished	Aug 27 06:03:06 AM UTC 24
Peak memory	211556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939323247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3939323247
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2632553710
Short name	T481
Test name
Test status
Simulation time	161333598440 ps
CPU time	99.96 seconds
Started	Aug 27 06:01:53 AM UTC 24
Finished	Aug 27 06:03:35 AM UTC 24
Peak memory	211728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632553710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.2632553710
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.4005479048
Short name	T580
Test name
Test status
Simulation time	485786537215 ps
CPU time	1107.41 seconds
Started	Aug 27 06:01:47 AM UTC 24
Finished	Aug 27 06:20:25 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005479048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4005479048
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.2107341544
Short name	T559
Test name
Test status
Simulation time	326052945555 ps
CPU time	969.26 seconds
Started	Aug 27 06:01:49 AM UTC 24
Finished	Aug 27 06:18:08 AM UTC 24
Peak memory	211676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107341544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.2107341544
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.342036375
Short name	T612
Test name
Test status
Simulation time	558788579521 ps
CPU time	1398.58 seconds
Started	Aug 27 06:01:57 AM UTC 24
Finished	Aug 27 06:25:29 AM UTC 24
Peak memory	212484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342036375 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.342036375
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3855552080
Short name	T504
Test name
Test status
Simulation time	607082986512 ps
CPU time	367.07 seconds
Started	Aug 27 06:02:12 AM UTC 24
Finished	Aug 27 06:08:23 AM UTC 24
Peak memory	211556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855552080 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.3855552080
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.2567885331
Short name	T516
Test name
Test status
Simulation time	85861753237 ps
CPU time	490.74 seconds
Started	Aug 27 06:02:45 AM UTC 24
Finished	Aug 27 06:11:01 AM UTC 24
Peak memory	212032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567885331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2567885331
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.1069958886
Short name	T480
Test name
Test status
Simulation time	29494015890 ps
CPU time	45.55 seconds
Started	Aug 27 06:02:44 AM UTC 24
Finished	Aug 27 06:03:32 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069958886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1069958886
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.3918476904
Short name	T476
Test name
Test status
Simulation time	4039989032 ps
CPU time	5.01 seconds
Started	Aug 27 06:02:41 AM UTC 24
Finished	Aug 27 06:02:47 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918476904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3918476904
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.1021347274
Short name	T470
Test name
Test status
Simulation time	6109167628 ps
CPU time	6.69 seconds
Started	Aug 27 06:01:44 AM UTC 24
Finished	Aug 27 06:01:51 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021347274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1021347274
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.1283611277
Short name	T496
Test name
Test status
Simulation time	206440760417 ps
CPU time	208.43 seconds
Started	Aug 27 06:03:00 AM UTC 24
Finished	Aug 27 06:06:32 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283611277 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.1283611277
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2910807847
Short name	T296
Test name
Test status
Simulation time	2050288825 ps
CPU time	9.7 seconds
Started	Aug 27 06:02:48 AM UTC 24
Finished	Aug 27 06:03:00 AM UTC 24
Peak memory	211260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2910807847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.adc_ctrl_stress_all_with_rand_reset.2910807847
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.1299244942
Short name	T485
Test name
Test status
Simulation time	486266633 ps
CPU time	1.32 seconds
Started	Aug 27 06:04:04 AM UTC 24
Finished	Aug 27 06:04:06 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299244942 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1299244942
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.1127944737
Short name	T316
Test name
Test status
Simulation time	349013019881 ps
CPU time	229.97 seconds
Started	Aug 27 06:03:33 AM UTC 24
Finished	Aug 27 06:07:26 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127944737 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.1127944737
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.4190627061
Short name	T348
Test name
Test status
Simulation time	182547131773 ps
CPU time	526.97 seconds
Started	Aug 27 06:03:33 AM UTC 24
Finished	Aug 27 06:12:26 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190627061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4190627061
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.3835365398
Short name	T613
Test name
Test status
Simulation time	501807574687 ps
CPU time	1349.84 seconds
Started	Aug 27 06:03:16 AM UTC 24
Finished	Aug 27 06:25:58 AM UTC 24
Peak memory	212496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835365398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3835365398
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.847194423
Short name	T596
Test name
Test status
Simulation time	497023905495 ps
CPU time	1153.85 seconds
Started	Aug 27 06:03:27 AM UTC 24
Finished	Aug 27 06:22:51 AM UTC 24
Peak memory	211520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847194423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.847194423
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.1875171018
Short name	T535
Test name
Test status
Simulation time	162701971144 ps
CPU time	666.37 seconds
Started	Aug 27 06:03:10 AM UTC 24
Finished	Aug 27 06:14:23 AM UTC 24
Peak memory	211560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875171018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1875171018
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.4294008207
Short name	T603
Test name
Test status
Simulation time	495955658956 ps
CPU time	1210.34 seconds
Started	Aug 27 06:03:13 AM UTC 24
Finished	Aug 27 06:23:35 AM UTC 24
Peak memory	212488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294008207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.4294008207
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.4000808832
Short name	T337
Test name
Test status
Simulation time	379744385969 ps
CPU time	119.15 seconds
Started	Aug 27 06:03:29 AM UTC 24
Finished	Aug 27 06:05:30 AM UTC 24
Peak memory	211860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000808832 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.4000808832
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.228171907
Short name	T488
Test name
Test status
Simulation time	216434463347 ps
CPU time	69.18 seconds
Started	Aug 27 06:03:32 AM UTC 24
Finished	Aug 27 06:04:43 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228171907 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.228171907
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.839824732
Short name	T514
Test name
Test status
Simulation time	72746766953 ps
CPU time	414.93 seconds
Started	Aug 27 06:03:49 AM UTC 24
Finished	Aug 27 06:10:49 AM UTC 24
Peak memory	211696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839824732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.839824732
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.1290644806
Short name	T484
Test name
Test status
Simulation time	23689286582 ps
CPU time	25.73 seconds
Started	Aug 27 06:03:36 AM UTC 24
Finished	Aug 27 06:04:03 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290644806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1290644806
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.3906117553
Short name	T483
Test name
Test status
Simulation time	5156952703 ps
CPU time	11.81 seconds
Started	Aug 27 06:03:35 AM UTC 24
Finished	Aug 27 06:03:48 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906117553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3906117553
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.3961005232
Short name	T479
Test name
Test status
Simulation time	5683598429 ps
CPU time	5.06 seconds
Started	Aug 27 06:03:09 AM UTC 24
Finished	Aug 27 06:03:15 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961005232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3961005232
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.3104763775
Short name	T507
Test name
Test status
Simulation time	219294985234 ps
CPU time	286.72 seconds
Started	Aug 27 06:04:03 AM UTC 24
Finished	Aug 27 06:08:53 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104763775 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.3104763775
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2359967337
Short name	T36
Test name
Test status
Simulation time	3234157942 ps
CPU time	7.17 seconds
Started	Aug 27 06:03:53 AM UTC 24
Finished	Aug 27 06:04:02 AM UTC 24
Peak memory	211324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2359967337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.adc_ctrl_stress_all_with_rand_reset.2359967337
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.2474773945
Short name	T493
Test name
Test status
Simulation time	448713125 ps
CPU time	1.16 seconds
Started	Aug 27 06:05:24 AM UTC 24
Finished	Aug 27 06:05:26 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474773945 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2474773945
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.3589033980
Short name	T574
Test name
Test status
Simulation time	338405270514 ps
CPU time	885.63 seconds
Started	Aug 27 06:04:46 AM UTC 24
Finished	Aug 27 06:19:41 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589033980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3589033980
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.731421290
Short name	T380
Test name
Test status
Simulation time	165169014333 ps
CPU time	58.2 seconds
Started	Aug 27 06:04:21 AM UTC 24
Finished	Aug 27 06:05:21 AM UTC 24
Peak memory	211504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731421290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.731421290
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1101804021
Short name	T525
Test name
Test status
Simulation time	165249379237 ps
CPU time	494.41 seconds
Started	Aug 27 06:04:30 AM UTC 24
Finished	Aug 27 06:12:50 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101804021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.1101804021
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.3189707723
Short name	T111
Test name
Test status
Simulation time	484293532111 ps
CPU time	583.65 seconds
Started	Aug 27 06:04:07 AM UTC 24
Finished	Aug 27 06:13:56 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189707723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3189707723
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.1878450324
Short name	T513
Test name
Test status
Simulation time	164493813945 ps
CPU time	370.01 seconds
Started	Aug 27 06:04:12 AM UTC 24
Finished	Aug 27 06:10:26 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878450324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.1878450324
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.4239411515
Short name	T272
Test name
Test status
Simulation time	353302181814 ps
CPU time	935.13 seconds
Started	Aug 27 06:04:39 AM UTC 24
Finished	Aug 27 06:20:23 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239411515 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.4239411515
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1334069807
Short name	T588
Test name
Test status
Simulation time	394950901263 ps
CPU time	973.35 seconds
Started	Aug 27 06:04:44 AM UTC 24
Finished	Aug 27 06:21:07 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334069807 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.1334069807
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.3152157909
Short name	T104
Test name
Test status
Simulation time	118784117562 ps
CPU time	502.79 seconds
Started	Aug 27 06:04:56 AM UTC 24
Finished	Aug 27 06:13:24 AM UTC 24
Peak memory	211780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152157909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3152157909
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.1292056560
Short name	T492
Test name
Test status
Simulation time	35575040665 ps
CPU time	32.18 seconds
Started	Aug 27 06:04:49 AM UTC 24
Finished	Aug 27 06:05:23 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292056560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1292056560
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.1057116030
Short name	T491
Test name
Test status
Simulation time	3934621156 ps
CPU time	5.42 seconds
Started	Aug 27 06:04:49 AM UTC 24
Finished	Aug 27 06:04:56 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057116030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1057116030
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.964744077
Short name	T487
Test name
Test status
Simulation time	5770770245 ps
CPU time	23.86 seconds
Started	Aug 27 06:04:04 AM UTC 24
Finished	Aug 27 06:04:29 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964744077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.964744077
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.861600953
Short name	T207
Test name
Test status
Simulation time	211168107174 ps
CPU time	409.73 seconds
Started	Aug 27 06:05:22 AM UTC 24
Finished	Aug 27 06:12:16 AM UTC 24
Peak memory	211504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861600953 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.861600953
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.4123849601
Short name	T37
Test name
Test status
Simulation time	17421603519 ps
CPU time	24.35 seconds
Started	Aug 27 06:05:01 AM UTC 24
Finished	Aug 27 06:05:26 AM UTC 24
Peak memory	221996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4123849601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.adc_ctrl_stress_all_with_rand_reset.4123849601
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.2709755502
Short name	T500
Test name
Test status
Simulation time	452190873 ps
CPU time	1.38 seconds
Started	Aug 27 06:07:21 AM UTC 24
Finished	Aug 27 06:07:23 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709755502 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2709755502
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.1082999498
Short name	T365
Test name
Test status
Simulation time	348387567225 ps
CPU time	899.21 seconds
Started	Aug 27 06:06:32 AM UTC 24
Finished	Aug 27 06:21:41 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082999498 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.1082999498
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.1227664430
Short name	T263
Test name
Test status
Simulation time	330409676325 ps
CPU time	767.54 seconds
Started	Aug 27 06:06:32 AM UTC 24
Finished	Aug 27 06:19:28 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227664430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1227664430
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.1958470080
Short name	T364
Test name
Test status
Simulation time	165685428980 ps
CPU time	154.05 seconds
Started	Aug 27 06:05:42 AM UTC 24
Finished	Aug 27 06:08:18 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958470080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1958470080
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4181962046
Short name	T505
Test name
Test status
Simulation time	495007063764 ps
CPU time	170.67 seconds
Started	Aug 27 06:05:55 AM UTC 24
Finished	Aug 27 06:08:48 AM UTC 24
Peak memory	211728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181962046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.4181962046
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.1943167493
Short name	T610
Test name
Test status
Simulation time	497223278348 ps
CPU time	1147.87 seconds
Started	Aug 27 06:05:27 AM UTC 24
Finished	Aug 27 06:24:46 AM UTC 24
Peak memory	212488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943167493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1943167493
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.2393938120
Short name	T522
Test name
Test status
Simulation time	495603187532 ps
CPU time	362.14 seconds
Started	Aug 27 06:05:31 AM UTC 24
Finished	Aug 27 06:11:37 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393938120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.2393938120
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.4182235933
Short name	T175
Test name
Test status
Simulation time	385763168396 ps
CPU time	620.73 seconds
Started	Aug 27 06:06:11 AM UTC 24
Finished	Aug 27 06:16:39 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182235933 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.4182235933
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.320010118
Short name	T106
Test name
Test status
Simulation time	201674637081 ps
CPU time	431.97 seconds
Started	Aug 27 06:06:12 AM UTC 24
Finished	Aug 27 06:13:29 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320010118 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.320010118
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.507391157
Short name	T391
Test name
Test status
Simulation time	111728064610 ps
CPU time	603.12 seconds
Started	Aug 27 06:07:05 AM UTC 24
Finished	Aug 27 06:17:14 AM UTC 24
Peak memory	212076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507391157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.507391157
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.668200807
Short name	T503
Test name
Test status
Simulation time	31466531053 ps
CPU time	48.79 seconds
Started	Aug 27 06:06:55 AM UTC 24
Finished	Aug 27 06:07:45 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668200807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.668200807
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.4189849676
Short name	T498
Test name
Test status
Simulation time	3241287976 ps
CPU time	7.7 seconds
Started	Aug 27 06:06:45 AM UTC 24
Finished	Aug 27 06:06:53 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189849676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4189849676
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.1127077132
Short name	T494
Test name
Test status
Simulation time	5927042122 ps
CPU time	13.32 seconds
Started	Aug 27 06:05:27 AM UTC 24
Finished	Aug 27 06:05:41 AM UTC 24
Peak memory	211216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127077132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1127077132
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.453521977
Short name	T546
Test name
Test status
Simulation time	170376056169 ps
CPU time	492.7 seconds
Started	Aug 27 06:07:19 AM UTC 24
Finished	Aug 27 06:15:37 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453521977 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.453521977
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2352073260
Short name	T353
Test name
Test status
Simulation time	1234638884 ps
CPU time	5.2 seconds
Started	Aug 27 06:07:12 AM UTC 24
Finished	Aug 27 06:07:18 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2352073260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.adc_ctrl_stress_all_with_rand_reset.2352073260
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.3312608390
Short name	T508
Test name
Test status
Simulation time	518310519 ps
CPU time	1.92 seconds
Started	Aug 27 06:08:56 AM UTC 24
Finished	Aug 27 06:08:59 AM UTC 24
Peak memory	210340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312608390 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3312608390
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.929180645
Short name	T273
Test name
Test status
Simulation time	350402475965 ps
CPU time	224.15 seconds
Started	Aug 27 06:08:24 AM UTC 24
Finished	Aug 27 06:12:11 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929180645 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.929180645
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.3160009077
Short name	T300
Test name
Test status
Simulation time	499007717378 ps
CPU time	1390.75 seconds
Started	Aug 27 06:07:43 AM UTC 24
Finished	Aug 27 06:31:07 AM UTC 24
Peak memory	212496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160009077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3160009077
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2820171653
Short name	T533
Test name
Test status
Simulation time	493898806828 ps
CPU time	384.59 seconds
Started	Aug 27 06:07:44 AM UTC 24
Finished	Aug 27 06:14:13 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820171653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.2820171653
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1140008607
Short name	T512
Test name
Test status
Simulation time	165305576957 ps
CPU time	128.16 seconds
Started	Aug 27 06:07:24 AM UTC 24
Finished	Aug 27 06:09:35 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140008607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1140008607
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.2782594329
Short name	T107
Test name
Test status
Simulation time	492579274749 ps
CPU time	363.43 seconds
Started	Aug 27 06:07:27 AM UTC 24
Finished	Aug 27 06:13:35 AM UTC 24
Peak memory	211392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782594329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.2782594329
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3637575968
Short name	T529
Test name
Test status
Simulation time	388693474924 ps
CPU time	280.18 seconds
Started	Aug 27 06:08:20 AM UTC 24
Finished	Aug 27 06:13:03 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637575968 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.3637575968
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.2489371893
Short name	T518
Test name
Test status
Simulation time	31950448094 ps
CPU time	135.15 seconds
Started	Aug 27 06:08:49 AM UTC 24
Finished	Aug 27 06:11:06 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489371893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2489371893
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.2103520866
Short name	T506
Test name
Test status
Simulation time	4097084733 ps
CPU time	19 seconds
Started	Aug 27 06:08:29 AM UTC 24
Finished	Aug 27 06:08:49 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103520866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2103520866
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.3143770870
Short name	T502
Test name
Test status
Simulation time	5670103195 ps
CPU time	21.81 seconds
Started	Aug 27 06:07:21 AM UTC 24
Finished	Aug 27 06:07:44 AM UTC 24
Peak memory	211292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143770870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3143770870
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.2460980904
Short name	T351
Test name
Test status
Simulation time	335122712240 ps
CPU time	508.02 seconds
Started	Aug 27 06:08:55 AM UTC 24
Finished	Aug 27 06:17:29 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460980904 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.2460980904
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3557602682
Short name	T38
Test name
Test status
Simulation time	7780712441 ps
CPU time	26.25 seconds
Started	Aug 27 06:08:54 AM UTC 24
Finished	Aug 27 06:09:22 AM UTC 24
Peak memory	222000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3557602682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.adc_ctrl_stress_all_with_rand_reset.3557602682
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.3077499114
Short name	T519
Test name
Test status
Simulation time	514519506 ps
CPU time	1.17 seconds
Started	Aug 27 06:11:07 AM UTC 24
Finished	Aug 27 06:11:09 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077499114 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3077499114
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.4007133347
Short name	T366
Test name
Test status
Simulation time	168009835536 ps
CPU time	278.61 seconds
Started	Aug 27 06:10:27 AM UTC 24
Finished	Aug 27 06:15:09 AM UTC 24
Peak memory	211528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007133347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4007133347
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.3838621329
Short name	T371
Test name
Test status
Simulation time	325590139516 ps
CPU time	211.2 seconds
Started	Aug 27 06:09:22 AM UTC 24
Finished	Aug 27 06:12:57 AM UTC 24
Peak memory	211692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838621329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3838621329
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1110963525
Short name	T639
Test name
Test status
Simulation time	327472907155 ps
CPU time	1087.63 seconds
Started	Aug 27 06:09:32 AM UTC 24
Finished	Aug 27 06:27:50 AM UTC 24
Peak memory	212804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110963525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.1110963525
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.725362013
Short name	T167
Test name
Test status
Simulation time	332724214612 ps
CPU time	249.22 seconds
Started	Aug 27 06:09:04 AM UTC 24
Finished	Aug 27 06:13:17 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725362013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.725362013
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.1391592055
Short name	T109
Test name
Test status
Simulation time	496168686466 ps
CPU time	261.47 seconds
Started	Aug 27 06:09:17 AM UTC 24
Finished	Aug 27 06:13:42 AM UTC 24
Peak memory	211520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391592055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.1391592055
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.2159837111
Short name	T540
Test name
Test status
Simulation time	349465689438 ps
CPU time	318.08 seconds
Started	Aug 27 06:09:33 AM UTC 24
Finished	Aug 27 06:14:55 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159837111 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.2159837111
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.4094690885
Short name	T524
Test name
Test status
Simulation time	208431062936 ps
CPU time	190.74 seconds
Started	Aug 27 06:09:36 AM UTC 24
Finished	Aug 27 06:12:49 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094690885 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.4094690885
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.2096756325
Short name	T597
Test name
Test status
Simulation time	125472580572 ps
CPU time	714.1 seconds
Started	Aug 27 06:11:00 AM UTC 24
Finished	Aug 27 06:23:02 AM UTC 24
Peak memory	211708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096756325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2096756325
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.438372760
Short name	T523
Test name
Test status
Simulation time	33639458961 ps
CPU time	88.92 seconds
Started	Aug 27 06:10:53 AM UTC 24
Finished	Aug 27 06:12:24 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438372760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.438372760
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.651446414
Short name	T515
Test name
Test status
Simulation time	3998524384 ps
CPU time	8.75 seconds
Started	Aug 27 06:10:50 AM UTC 24
Finished	Aug 27 06:11:00 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651446414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.651446414
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.3268818203
Short name	T509
Test name
Test status
Simulation time	5841687226 ps
CPU time	2.24 seconds
Started	Aug 27 06:09:00 AM UTC 24
Finished	Aug 27 06:09:03 AM UTC 24
Peak memory	211220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268818203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3268818203
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.2285713588
Short name	T335
Test name
Test status
Simulation time	362452293514 ps
CPU time	1127.66 seconds
Started	Aug 27 06:11:03 AM UTC 24
Finished	Aug 27 06:30:02 AM UTC 24
Peak memory	212484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285713588 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.2285713588
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1631628058
Short name	T520
Test name
Test status
Simulation time	1526912530 ps
CPU time	7.43 seconds
Started	Aug 27 06:11:01 AM UTC 24
Finished	Aug 27 06:11:10 AM UTC 24
Peak memory	211596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1631628058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.adc_ctrl_stress_all_with_rand_reset.1631628058
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.4015452471
Short name	T528
Test name
Test status
Simulation time	349741067 ps
CPU time	1.14 seconds
Started	Aug 27 06:12:57 AM UTC 24
Finished	Aug 27 06:12:59 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015452471 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.4015452471
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.1258487819
Short name	T289
Test name
Test status
Simulation time	164287564180 ps
CPU time	342.44 seconds
Started	Aug 27 06:12:24 AM UTC 24
Finished	Aug 27 06:18:11 AM UTC 24
Peak memory	211604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258487819 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.1258487819
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.1068018634
Short name	T190
Test name
Test status
Simulation time	331487408261 ps
CPU time	220.66 seconds
Started	Aug 27 06:12:27 AM UTC 24
Finished	Aug 27 06:16:11 AM UTC 24
Peak memory	211604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068018634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1068018634
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.3291438857
Short name	T186
Test name
Test status
Simulation time	330381110182 ps
CPU time	232.72 seconds
Started	Aug 27 06:11:35 AM UTC 24
Finished	Aug 27 06:15:31 AM UTC 24
Peak memory	211540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291438857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3291438857
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2922357135
Short name	T545
Test name
Test status
Simulation time	325971299690 ps
CPU time	231.91 seconds
Started	Aug 27 06:11:38 AM UTC 24
Finished	Aug 27 06:15:33 AM UTC 24
Peak memory	211520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922357135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.2922357135
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.221072758
Short name	T294
Test name
Test status
Simulation time	329728374920 ps
CPU time	99.1 seconds
Started	Aug 27 06:11:10 AM UTC 24
Finished	Aug 27 06:12:52 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221072758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.221072758
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.3710748029
Short name	T544
Test name
Test status
Simulation time	337203596035 ps
CPU time	240.51 seconds
Started	Aug 27 06:11:20 AM UTC 24
Finished	Aug 27 06:15:24 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710748029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.3710748029
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.3654892895
Short name	T329
Test name
Test status
Simulation time	192856248652 ps
CPU time	52.21 seconds
Started	Aug 27 06:12:12 AM UTC 24
Finished	Aug 27 06:13:06 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654892895 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.3654892895
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.552168686
Short name	T749
Test name
Test status
Simulation time	615197418858 ps
CPU time	1762.36 seconds
Started	Aug 27 06:12:17 AM UTC 24
Finished	Aug 27 06:41:56 AM UTC 24
Peak memory	212544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552168686 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.552168686
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.2494601531
Short name	T232
Test name
Test status
Simulation time	103869125225 ps
CPU time	361.26 seconds
Started	Aug 27 06:12:51 AM UTC 24
Finished	Aug 27 06:18:56 AM UTC 24
Peak memory	212088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494601531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2494601531
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.2138291720
Short name	T531
Test name
Test status
Simulation time	22489829260 ps
CPU time	23.58 seconds
Started	Aug 27 06:12:50 AM UTC 24
Finished	Aug 27 06:13:15 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138291720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2138291720
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.2022753117
Short name	T527
Test name
Test status
Simulation time	3825820854 ps
CPU time	4.98 seconds
Started	Aug 27 06:12:50 AM UTC 24
Finished	Aug 27 06:12:56 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022753117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2022753117
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.592056229
Short name	T521
Test name
Test status
Simulation time	5845980708 ps
CPU time	7.66 seconds
Started	Aug 27 06:11:10 AM UTC 24
Finished	Aug 27 06:11:19 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592056229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.592056229
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.2086441793
Short name	T537
Test name
Test status
Simulation time	37150639766 ps
CPU time	105.5 seconds
Started	Aug 27 06:12:52 AM UTC 24
Finished	Aug 27 06:14:40 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086441793 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.2086441793
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3265048913
Short name	T88
Test name
Test status
Simulation time	162013035988 ps
CPU time	26.17 seconds
Started	Aug 27 06:12:52 AM UTC 24
Finished	Aug 27 06:13:20 AM UTC 24
Peak memory	221884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3265048913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.adc_ctrl_stress_all_with_rand_reset.3265048913
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.308789770
Short name	T108
Test name
Test status
Simulation time	552502959 ps
CPU time	1.43 seconds
Started	Aug 27 06:13:35 AM UTC 24
Finished	Aug 27 06:13:38 AM UTC 24
Peak memory	210340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308789770 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.308789770
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.2399782830
Short name	T191
Test name
Test status
Simulation time	553957854996 ps
CPU time	205.64 seconds
Started	Aug 27 06:13:16 AM UTC 24
Finished	Aug 27 06:16:45 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399782830 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.2399782830
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.33099671
Short name	T299
Test name
Test status
Simulation time	322599291686 ps
CPU time	269.73 seconds
Started	Aug 27 06:13:04 AM UTC 24
Finished	Aug 27 06:17:37 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33099671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.33099671
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1383628353
Short name	T593
Test name
Test status
Simulation time	163896738903 ps
CPU time	550.95 seconds
Started	Aug 27 06:13:07 AM UTC 24
Finished	Aug 27 06:22:24 AM UTC 24
Peak memory	211592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383628353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.1383628353
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.114609493
Short name	T359
Test name
Test status
Simulation time	321995197853 ps
CPU time	672.02 seconds
Started	Aug 27 06:12:58 AM UTC 24
Finished	Aug 27 06:24:16 AM UTC 24
Peak memory	211692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114609493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.114609493
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.3477679286
Short name	T578
Test name
Test status
Simulation time	326064000719 ps
CPU time	430.19 seconds
Started	Aug 27 06:13:00 AM UTC 24
Finished	Aug 27 06:20:15 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477679286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.3477679286
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.1634553969
Short name	T615
Test name
Test status
Simulation time	533895248237 ps
CPU time	766.94 seconds
Started	Aug 27 06:13:10 AM UTC 24
Finished	Aug 27 06:26:05 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634553969 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.1634553969
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.209671990
Short name	T543
Test name
Test status
Simulation time	596771732823 ps
CPU time	125.41 seconds
Started	Aug 27 06:13:14 AM UTC 24
Finished	Aug 27 06:15:22 AM UTC 24
Peak memory	211444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209671990 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.209671990
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.3516818026
Short name	T563
Test name
Test status
Simulation time	80558047751 ps
CPU time	322.35 seconds
Started	Aug 27 06:13:25 AM UTC 24
Finished	Aug 27 06:18:51 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516818026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3516818026
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.3672874942
Short name	T539
Test name
Test status
Simulation time	29936122625 ps
CPU time	85.04 seconds
Started	Aug 27 06:13:24 AM UTC 24
Finished	Aug 27 06:14:51 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672874942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3672874942
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.4176506175
Short name	T105
Test name
Test status
Simulation time	3012684560 ps
CPU time	4.3 seconds
Started	Aug 27 06:13:21 AM UTC 24
Finished	Aug 27 06:13:26 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176506175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4176506175
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.2924236280
Short name	T103
Test name
Test status
Simulation time	5627492448 ps
CPU time	24.71 seconds
Started	Aug 27 06:12:58 AM UTC 24
Finished	Aug 27 06:13:24 AM UTC 24
Peak memory	211292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924236280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2924236280
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.3416655811
Short name	T565
Test name
Test status
Simulation time	224310502566 ps
CPU time	321.66 seconds
Started	Aug 27 06:13:30 AM UTC 24
Finished	Aug 27 06:18:56 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416655811 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.3416655811
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3780541851
Short name	T39
Test name
Test status
Simulation time	19054362775 ps
CPU time	30.59 seconds
Started	Aug 27 06:13:27 AM UTC 24
Finished	Aug 27 06:13:59 AM UTC 24
Peak memory	221944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3780541851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.adc_ctrl_stress_all_with_rand_reset.3780541851
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.3040575831
Short name	T538
Test name
Test status
Simulation time	432029013 ps
CPU time	2.71 seconds
Started	Aug 27 06:14:47 AM UTC 24
Finished	Aug 27 06:14:51 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040575831 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3040575831
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.2968582809
Short name	T582
Test name
Test status
Simulation time	176295437670 ps
CPU time	375.74 seconds
Started	Aug 27 06:14:10 AM UTC 24
Finished	Aug 27 06:20:30 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968582809 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.2968582809
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.77580377
Short name	T584
Test name
Test status
Simulation time	512444010780 ps
CPU time	383.07 seconds
Started	Aug 27 06:14:14 AM UTC 24
Finished	Aug 27 06:20:41 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77580377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.77580377
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2353122948
Short name	T552
Test name
Test status
Simulation time	329047414653 ps
CPU time	140.31 seconds
Started	Aug 27 06:14:00 AM UTC 24
Finished	Aug 27 06:16:22 AM UTC 24
Peak memory	211396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353122948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.2353122948
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.654747461
Short name	T550
Test name
Test status
Simulation time	163811522084 ps
CPU time	118.71 seconds
Started	Aug 27 06:13:42 AM UTC 24
Finished	Aug 27 06:15:43 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654747461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.654747461
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.3220689523
Short name	T626
Test name
Test status
Simulation time	325795574724 ps
CPU time	779.03 seconds
Started	Aug 27 06:13:47 AM UTC 24
Finished	Aug 27 06:26:53 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220689523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.3220689523
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.324546971
Short name	T307
Test name
Test status
Simulation time	579601410783 ps
CPU time	1566.43 seconds
Started	Aug 27 06:14:03 AM UTC 24
Finished	Aug 27 06:40:25 AM UTC 24
Peak memory	212552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324546971 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.324546971
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1903493499
Short name	T625
Test name
Test status
Simulation time	609315253470 ps
CPU time	756.42 seconds
Started	Aug 27 06:14:08 AM UTC 24
Finished	Aug 27 06:26:52 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903493499 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.1903493499
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.380961429
Short name	T628
Test name
Test status
Simulation time	112892975507 ps
CPU time	747.72 seconds
Started	Aug 27 06:14:24 AM UTC 24
Finished	Aug 27 06:26:59 AM UTC 24
Peak memory	211960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380961429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.380961429
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.2169546142
Short name	T541
Test name
Test status
Simulation time	33460860173 ps
CPU time	34.78 seconds
Started	Aug 27 06:14:23 AM UTC 24
Finished	Aug 27 06:14:59 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169546142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2169546142
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.3750637239
Short name	T536
Test name
Test status
Simulation time	3991635042 ps
CPU time	4.37 seconds
Started	Aug 27 06:14:18 AM UTC 24
Finished	Aug 27 06:14:23 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750637239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3750637239
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.3561989204
Short name	T532
Test name
Test status
Simulation time	5937698980 ps
CPU time	21.9 seconds
Started	Aug 27 06:13:38 AM UTC 24
Finished	Aug 27 06:14:02 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561989204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3561989204
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.4272659173
Short name	T569
Test name
Test status
Simulation time	328110389657 ps
CPU time	273.66 seconds
Started	Aug 27 06:14:40 AM UTC 24
Finished	Aug 27 06:19:18 AM UTC 24
Peak memory	211540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272659173 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.4272659173
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.523192825
Short name	T102
Test name
Test status
Simulation time	5891687787 ps
CPU time	20.83 seconds
Started	Aug 27 06:14:24 AM UTC 24
Finished	Aug 27 06:14:46 AM UTC 24
Peak memory	221628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=523192825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.523192825
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2833781890
Short name	T25
Test name
Test status
Simulation time	422063877 ps
CPU time	1.32 seconds
Started	Aug 27 05:36:58 AM UTC 24
Finished	Aug 27 05:37:02 AM UTC 24
Peak memory	209796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833781890 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2833781890
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.567323873
Short name	T237
Test name
Test status
Simulation time	182458692002 ps
CPU time	247.47 seconds
Started	Aug 27 05:36:53 AM UTC 24
Finished	Aug 27 05:41:05 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567323873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.567323873
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.70718771
Short name	T215
Test name
Test status
Simulation time	497681874672 ps
CPU time	835.76 seconds
Started	Aug 27 05:36:52 AM UTC 24
Finished	Aug 27 05:50:56 AM UTC 24
Peak memory	211528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70718771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.70718771
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.440785500
Short name	T160
Test name
Test status
Simulation time	330280155778 ps
CPU time	189.68 seconds
Started	Aug 27 05:36:49 AM UTC 24
Finished	Aug 27 05:40:01 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440785500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.440785500
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.670981085
Short name	T200
Test name
Test status
Simulation time	320596269367 ps
CPU time	268.38 seconds
Started	Aug 27 05:36:50 AM UTC 24
Finished	Aug 27 05:41:22 AM UTC 24
Peak memory	211656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670981085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.670981085
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.323704603
Short name	T46
Test name
Test status
Simulation time	195326180946 ps
CPU time	395.96 seconds
Started	Aug 27 05:36:52 AM UTC 24
Finished	Aug 27 05:43:32 AM UTC 24
Peak memory	211500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323704603 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.323704603
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2002914767
Short name	T96
Test name
Test status
Simulation time	202003929816 ps
CPU time	153.26 seconds
Started	Aug 27 05:36:52 AM UTC 24
Finished	Aug 27 05:39:28 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002914767 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.2002914767
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2057197665
Short name	T73
Test name
Test status
Simulation time	121565371113 ps
CPU time	467.47 seconds
Started	Aug 27 05:36:55 AM UTC 24
Finished	Aug 27 05:44:46 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057197665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2057197665
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.3724215882
Short name	T27
Test name
Test status
Simulation time	34298057968 ps
CPU time	56.26 seconds
Started	Aug 27 05:36:53 AM UTC 24
Finished	Aug 27 05:37:52 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724215882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3724215882
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.1059889646
Short name	T13
Test name
Test status
Simulation time	5676576314 ps
CPU time	13.03 seconds
Started	Aug 27 05:36:53 AM UTC 24
Finished	Aug 27 05:37:09 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059889646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1059889646
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.3812862807
Short name	T26
Test name
Test status
Simulation time	4515823316 ps
CPU time	4.79 seconds
Started	Aug 27 05:36:58 AM UTC 24
Finished	Aug 27 05:37:05 AM UTC 24
Peak memory	243556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812862807 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3812862807
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.4098127580
Short name	T8
Test name
Test status
Simulation time	6169414344 ps
CPU time	7.21 seconds
Started	Aug 27 05:36:49 AM UTC 24
Finished	Aug 27 05:36:57 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098127580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.4098127580
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.857772911
Short name	T549
Test name
Test status
Simulation time	383918184 ps
CPU time	2.41 seconds
Started	Aug 27 06:15:39 AM UTC 24
Finished	Aug 27 06:15:43 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857772911 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.857772911
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.675046501
Short name	T334
Test name
Test status
Simulation time	321602582855 ps
CPU time	803.11 seconds
Started	Aug 27 06:15:00 AM UTC 24
Finished	Aug 27 06:28:31 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675046501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.675046501
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1755520689
Short name	T553
Test name
Test status
Simulation time	165736869661 ps
CPU time	126.15 seconds
Started	Aug 27 06:15:10 AM UTC 24
Finished	Aug 27 06:17:18 AM UTC 24
Peak memory	211592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755520689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.1755520689
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.4052219997
Short name	T570
Test name
Test status
Simulation time	333362206053 ps
CPU time	263.06 seconds
Started	Aug 27 06:14:52 AM UTC 24
Finished	Aug 27 06:19:19 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052219997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.4052219997
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.1330121722
Short name	T573
Test name
Test status
Simulation time	159959015940 ps
CPU time	274.35 seconds
Started	Aug 27 06:14:56 AM UTC 24
Finished	Aug 27 06:19:34 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330121722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.1330121722
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.2610114314
Short name	T209
Test name
Test status
Simulation time	356750071739 ps
CPU time	205.69 seconds
Started	Aug 27 06:15:21 AM UTC 24
Finished	Aug 27 06:18:49 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610114314 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.2610114314
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.61778151
Short name	T555
Test name
Test status
Simulation time	195613463654 ps
CPU time	118.05 seconds
Started	Aug 27 06:15:23 AM UTC 24
Finished	Aug 27 06:17:23 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61778151 -assert nopostpro c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.61778151
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.2399297820
Short name	T392
Test name
Test status
Simulation time	86294258278 ps
CPU time	476.61 seconds
Started	Aug 27 06:15:36 AM UTC 24
Finished	Aug 27 06:23:38 AM UTC 24
Peak memory	212084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399297820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2399297820
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2211140686
Short name	T558
Test name
Test status
Simulation time	36912853957 ps
CPU time	132.85 seconds
Started	Aug 27 06:15:35 AM UTC 24
Finished	Aug 27 06:17:50 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211140686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2211140686
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.1577132437
Short name	T548
Test name
Test status
Simulation time	3272485648 ps
CPU time	2.93 seconds
Started	Aug 27 06:15:34 AM UTC 24
Finished	Aug 27 06:15:38 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577132437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1577132437
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.160538280
Short name	T542
Test name
Test status
Simulation time	6186892519 ps
CPU time	26.57 seconds
Started	Aug 27 06:14:52 AM UTC 24
Finished	Aug 27 06:15:20 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160538280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.160538280
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.968609898
Short name	T799
Test name
Test status
Simulation time	1679619361670 ps
CPU time	5057.44 seconds
Started	Aug 27 06:15:38 AM UTC 24
Finished	Aug 27 07:40:41 AM UTC 24
Peak memory	222884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968609898 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.968609898
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1349560923
Short name	T40
Test name
Test status
Simulation time	6780813998 ps
CPU time	7.9 seconds
Started	Aug 27 06:15:38 AM UTC 24
Finished	Aug 27 06:15:47 AM UTC 24
Peak memory	211616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1349560923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.adc_ctrl_stress_all_with_rand_reset.1349560923
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.2480877173
Short name	T556
Test name
Test status
Simulation time	473636465 ps
CPU time	2.09 seconds
Started	Aug 27 06:17:34 AM UTC 24
Finished	Aug 27 06:17:38 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480877173 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2480877173
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.799931620
Short name	T325
Test name
Test status
Simulation time	615775823638 ps
CPU time	539.17 seconds
Started	Aug 27 06:16:40 AM UTC 24
Finished	Aug 27 06:25:45 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799931620 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.799931620
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.3340027600
Short name	T350
Test name
Test status
Simulation time	198966159754 ps
CPU time	280.29 seconds
Started	Aug 27 06:16:45 AM UTC 24
Finished	Aug 27 06:21:29 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340027600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3340027600
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3514173052
Short name	T295
Test name
Test status
Simulation time	164574496763 ps
CPU time	121.2 seconds
Started	Aug 27 06:15:55 AM UTC 24
Finished	Aug 27 06:17:58 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514173052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3514173052
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2723231529
Short name	T560
Test name
Test status
Simulation time	163616542142 ps
CPU time	149.62 seconds
Started	Aug 27 06:16:11 AM UTC 24
Finished	Aug 27 06:18:43 AM UTC 24
Peak memory	211512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723231529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.2723231529
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.1852867656
Short name	T561
Test name
Test status
Simulation time	167378900923 ps
CPU time	178.32 seconds
Started	Aug 27 06:15:44 AM UTC 24
Finished	Aug 27 06:18:46 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852867656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1852867656
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.1614544939
Short name	T692
Test name
Test status
Simulation time	491988024828 ps
CPU time	1170.03 seconds
Started	Aug 27 06:15:47 AM UTC 24
Finished	Aug 27 06:35:28 AM UTC 24
Peak memory	212548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614544939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.1614544939
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.4071767464
Short name	T609
Test name
Test status
Simulation time	181183539679 ps
CPU time	504.01 seconds
Started	Aug 27 06:16:12 AM UTC 24
Finished	Aug 27 06:24:41 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071767464 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.4071767464
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3959303436
Short name	T592
Test name
Test status
Simulation time	413287589748 ps
CPU time	328.57 seconds
Started	Aug 27 06:16:23 AM UTC 24
Finished	Aug 27 06:21:56 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959303436 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.3959303436
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.1798476902
Short name	T616
Test name
Test status
Simulation time	124486751930 ps
CPU time	518.63 seconds
Started	Aug 27 06:17:21 AM UTC 24
Finished	Aug 27 06:26:05 AM UTC 24
Peak memory	212084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798476902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1798476902
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.3979593320
Short name	T564
Test name
Test status
Simulation time	24119267438 ps
CPU time	93.03 seconds
Started	Aug 27 06:17:19 AM UTC 24
Finished	Aug 27 06:18:54 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979593320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3979593320
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.1546971953
Short name	T554
Test name
Test status
Simulation time	3399429331 ps
CPU time	3.83 seconds
Started	Aug 27 06:17:15 AM UTC 24
Finished	Aug 27 06:17:20 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546971953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1546971953
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.412272128
Short name	T551
Test name
Test status
Simulation time	6028183120 ps
CPU time	24.95 seconds
Started	Aug 27 06:15:43 AM UTC 24
Finished	Aug 27 06:16:10 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412272128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.412272128
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.1891469923
Short name	T388
Test name
Test status
Simulation time	283271594588 ps
CPU time	574.32 seconds
Started	Aug 27 06:17:29 AM UTC 24
Finished	Aug 27 06:27:10 AM UTC 24
Peak memory	221892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891469923 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.1891469923
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.38746482
Short name	T41
Test name
Test status
Simulation time	11590733782 ps
CPU time	9.24 seconds
Started	Aug 27 06:17:23 AM UTC 24
Finished	Aug 27 06:17:34 AM UTC 24
Peak memory	211332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=38746482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.38746482
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.2931206496
Short name	T566
Test name
Test status
Simulation time	530197287 ps
CPU time	0.99 seconds
Started	Aug 27 06:18:55 AM UTC 24
Finished	Aug 27 06:18:56 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931206496 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2931206496
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.2142567288
Short name	T264
Test name
Test status
Simulation time	173178938720 ps
CPU time	344.09 seconds
Started	Aug 27 06:18:10 AM UTC 24
Finished	Aug 27 06:23:59 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142567288 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.2142567288
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.820450510
Short name	T368
Test name
Test status
Simulation time	163879587633 ps
CPU time	52.01 seconds
Started	Aug 27 06:18:12 AM UTC 24
Finished	Aug 27 06:19:06 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820450510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.820450510
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.233780796
Short name	T360
Test name
Test status
Simulation time	158072066661 ps
CPU time	641.58 seconds
Started	Aug 27 06:17:51 AM UTC 24
Finished	Aug 27 06:28:40 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233780796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.233780796
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.600099989
Short name	T620
Test name
Test status
Simulation time	166652834828 ps
CPU time	489.21 seconds
Started	Aug 27 06:17:59 AM UTC 24
Finished	Aug 27 06:26:14 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600099989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.600099989
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.436037046
Short name	T647
Test name
Test status
Simulation time	494669717983 ps
CPU time	728.76 seconds
Started	Aug 27 06:17:39 AM UTC 24
Finished	Aug 27 06:29:55 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436037046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.436037046
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.1826804299
Short name	T727
Test name
Test status
Simulation time	491967864850 ps
CPU time	1345.75 seconds
Started	Aug 27 06:17:46 AM UTC 24
Finished	Aug 27 06:40:25 AM UTC 24
Peak memory	212620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826804299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.1826804299
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.2834014049
Short name	T192
Test name
Test status
Simulation time	534312602390 ps
CPU time	292.16 seconds
Started	Aug 27 06:18:03 AM UTC 24
Finished	Aug 27 06:22:59 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834014049 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.2834014049
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3190304016
Short name	T604
Test name
Test status
Simulation time	411458834845 ps
CPU time	322.83 seconds
Started	Aug 27 06:18:08 AM UTC 24
Finished	Aug 27 06:23:35 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190304016 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.3190304016
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.1928542509
Short name	T586
Test name
Test status
Simulation time	30463340331 ps
CPU time	114.62 seconds
Started	Aug 27 06:18:46 AM UTC 24
Finished	Aug 27 06:20:43 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928542509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1928542509
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.4215775623
Short name	T562
Test name
Test status
Simulation time	4310654526 ps
CPU time	2.82 seconds
Started	Aug 27 06:18:43 AM UTC 24
Finished	Aug 27 06:18:47 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215775623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4215775623
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.2744275906
Short name	T557
Test name
Test status
Simulation time	5710769213 ps
CPU time	6.38 seconds
Started	Aug 27 06:17:38 AM UTC 24
Finished	Aug 27 06:17:45 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744275906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2744275906
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.1318402397
Short name	T694
Test name
Test status
Simulation time	230994317898 ps
CPU time	1006.35 seconds
Started	Aug 27 06:18:51 AM UTC 24
Finished	Aug 27 06:35:47 AM UTC 24
Peak memory	223060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318402397 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.1318402397
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1505272569
Short name	T571
Test name
Test status
Simulation time	11721540431 ps
CPU time	39.85 seconds
Started	Aug 27 06:18:50 AM UTC 24
Finished	Aug 27 06:19:32 AM UTC 24
Peak memory	221964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1505272569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.adc_ctrl_stress_all_with_rand_reset.1505272569
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.3616460447
Short name	T575
Test name
Test status
Simulation time	393634808 ps
CPU time	1.66 seconds
Started	Aug 27 06:19:41 AM UTC 24
Finished	Aug 27 06:19:44 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616460447 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3616460447
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.1993115951
Short name	T345
Test name
Test status
Simulation time	178280912166 ps
CPU time	488.57 seconds
Started	Aug 27 06:19:19 AM UTC 24
Finished	Aug 27 06:27:33 AM UTC 24
Peak memory	211540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993115951 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.1993115951
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.3809534977
Short name	T313
Test name
Test status
Simulation time	498213649916 ps
CPU time	1304.91 seconds
Started	Aug 27 06:19:20 AM UTC 24
Finished	Aug 27 06:41:18 AM UTC 24
Peak memory	212480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809534977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3809534977
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.4125303433
Short name	T583
Test name
Test status
Simulation time	169315816285 ps
CPU time	83.61 seconds
Started	Aug 27 06:19:06 AM UTC 24
Finished	Aug 27 06:20:31 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125303433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4125303433
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.9251795
Short name	T636
Test name
Test status
Simulation time	167997942827 ps
CPU time	491.51 seconds
Started	Aug 27 06:19:07 AM UTC 24
Finished	Aug 27 06:27:24 AM UTC 24
Peak memory	211604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9251795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base _test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.9251795
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.2914636852
Short name	T724
Test name
Test status
Simulation time	497346500272 ps
CPU time	1183.39 seconds
Started	Aug 27 06:18:57 AM UTC 24
Finished	Aug 27 06:38:51 AM UTC 24
Peak memory	212336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914636852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2914636852
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.2850504418
Short name	T621
Test name
Test status
Simulation time	324554164999 ps
CPU time	435.43 seconds
Started	Aug 27 06:18:58 AM UTC 24
Finished	Aug 27 06:26:18 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850504418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.2850504418
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.600212826
Short name	T370
Test name
Test status
Simulation time	190080530136 ps
CPU time	102.75 seconds
Started	Aug 27 06:19:14 AM UTC 24
Finished	Aug 27 06:20:59 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600212826 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.600212826
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1668842588
Short name	T622
Test name
Test status
Simulation time	634640724414 ps
CPU time	417.48 seconds
Started	Aug 27 06:19:18 AM UTC 24
Finished	Aug 27 06:26:20 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668842588 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.1668842588
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.3379411965
Short name	T666
Test name
Test status
Simulation time	107796093842 ps
CPU time	738.78 seconds
Started	Aug 27 06:19:32 AM UTC 24
Finished	Aug 27 06:31:59 AM UTC 24
Peak memory	211972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379411965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3379411965
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.2050840160
Short name	T585
Test name
Test status
Simulation time	31308133555 ps
CPU time	70.97 seconds
Started	Aug 27 06:19:29 AM UTC 24
Finished	Aug 27 06:20:42 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050840160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2050840160
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.2485854233
Short name	T572
Test name
Test status
Simulation time	3762132584 ps
CPU time	3.23 seconds
Started	Aug 27 06:19:27 AM UTC 24
Finished	Aug 27 06:19:32 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485854233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2485854233
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.1041152363
Short name	T567
Test name
Test status
Simulation time	5809154064 ps
CPU time	7.24 seconds
Started	Aug 27 06:18:57 AM UTC 24
Finished	Aug 27 06:19:05 AM UTC 24
Peak memory	211232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041152363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1041152363
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1662755321
Short name	T576
Test name
Test status
Simulation time	3741169517 ps
CPU time	11.25 seconds
Started	Aug 27 06:19:32 AM UTC 24
Finished	Aug 27 06:19:45 AM UTC 24
Peak memory	211596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1662755321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.adc_ctrl_stress_all_with_rand_reset.1662755321
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.3277014477
Short name	T590
Test name
Test status
Simulation time	574190386 ps
CPU time	1.02 seconds
Started	Aug 27 06:21:08 AM UTC 24
Finished	Aug 27 06:21:10 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277014477 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3277014477
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.1034764284
Short name	T375
Test name
Test status
Simulation time	342060768243 ps
CPU time	182.2 seconds
Started	Aug 27 06:20:31 AM UTC 24
Finished	Aug 27 06:23:36 AM UTC 24
Peak memory	211604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034764284 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.1034764284
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.871244757
Short name	T766
Test name
Test status
Simulation time	553586096126 ps
CPU time	1416.69 seconds
Started	Aug 27 06:20:32 AM UTC 24
Finished	Aug 27 06:44:23 AM UTC 24
Peak memory	212540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871244757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.871244757
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.3145360694
Short name	T753
Test name
Test status
Simulation time	492759987469 ps
CPU time	1341.09 seconds
Started	Aug 27 06:20:16 AM UTC 24
Finished	Aug 27 06:42:51 AM UTC 24
Peak memory	212880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145360694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3145360694
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1418834514
Short name	T667
Test name
Test status
Simulation time	326914167009 ps
CPU time	697.85 seconds
Started	Aug 27 06:20:17 AM UTC 24
Finished	Aug 27 06:32:03 AM UTC 24
Peak memory	211784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418834514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.1418834514
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.3344831749
Short name	T278
Test name
Test status
Simulation time	333572744148 ps
CPU time	222.12 seconds
Started	Aug 27 06:19:46 AM UTC 24
Finished	Aug 27 06:23:31 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344831749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3344831749
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.2454137343
Short name	T618
Test name
Test status
Simulation time	164598928925 ps
CPU time	373.46 seconds
Started	Aug 27 06:19:54 AM UTC 24
Finished	Aug 27 06:26:12 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454137343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.2454137343
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.168915111
Short name	T178
Test name
Test status
Simulation time	544226581629 ps
CPU time	204.32 seconds
Started	Aug 27 06:20:24 AM UTC 24
Finished	Aug 27 06:23:51 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168915111 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.168915111
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1355852315
Short name	T627
Test name
Test status
Simulation time	397784645944 ps
CPU time	387.84 seconds
Started	Aug 27 06:20:25 AM UTC 24
Finished	Aug 27 06:26:58 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355852315 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.1355852315
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.881506527
Short name	T637
Test name
Test status
Simulation time	74146058772 ps
CPU time	397.29 seconds
Started	Aug 27 06:20:44 AM UTC 24
Finished	Aug 27 06:27:26 AM UTC 24
Peak memory	212020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881506527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.881506527
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.1757124926
Short name	T591
Test name
Test status
Simulation time	31119098446 ps
CPU time	58.2 seconds
Started	Aug 27 06:20:43 AM UTC 24
Finished	Aug 27 06:21:43 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757124926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1757124926
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.2065928702
Short name	T587
Test name
Test status
Simulation time	4166641039 ps
CPU time	16.84 seconds
Started	Aug 27 06:20:42 AM UTC 24
Finished	Aug 27 06:21:00 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065928702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2065928702
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.3577109074
Short name	T577
Test name
Test status
Simulation time	6192195366 ps
CPU time	7.24 seconds
Started	Aug 27 06:19:45 AM UTC 24
Finished	Aug 27 06:19:53 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577109074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3577109074
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.2262666418
Short name	T177
Test name
Test status
Simulation time	338089861682 ps
CPU time	83.42 seconds
Started	Aug 27 06:21:01 AM UTC 24
Finished	Aug 27 06:22:26 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262666418 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.2262666418
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.177771959
Short name	T589
Test name
Test status
Simulation time	3781336193 ps
CPU time	8.72 seconds
Started	Aug 27 06:20:59 AM UTC 24
Finished	Aug 27 06:21:09 AM UTC 24
Peak memory	211336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=177771959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.177771959
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.323518921
Short name	T598
Test name
Test status
Simulation time	487986456 ps
CPU time	2.94 seconds
Started	Aug 27 06:23:00 AM UTC 24
Finished	Aug 27 06:23:04 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323518921 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.323518921
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.1528297151
Short name	T619
Test name
Test status
Simulation time	177057889480 ps
CPU time	232.01 seconds
Started	Aug 27 06:22:17 AM UTC 24
Finished	Aug 27 06:26:12 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528297151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1528297151
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.2137691644
Short name	T635
Test name
Test status
Simulation time	498869959187 ps
CPU time	350.05 seconds
Started	Aug 27 06:21:21 AM UTC 24
Finished	Aug 27 06:27:15 AM UTC 24
Peak memory	211428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137691644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2137691644
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1278750062
Short name	T688
Test name
Test status
Simulation time	497290887903 ps
CPU time	811.55 seconds
Started	Aug 27 06:21:30 AM UTC 24
Finished	Aug 27 06:35:10 AM UTC 24
Peak memory	211652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278750062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.1278750062
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.4002118581
Short name	T601
Test name
Test status
Simulation time	160128230230 ps
CPU time	122.91 seconds
Started	Aug 27 06:21:11 AM UTC 24
Finished	Aug 27 06:23:16 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002118581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4002118581
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.1665183000
Short name	T594
Test name
Test status
Simulation time	165142627893 ps
CPU time	79.55 seconds
Started	Aug 27 06:21:13 AM UTC 24
Finished	Aug 27 06:22:34 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665183000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.1665183000
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.2690032319
Short name	T369
Test name
Test status
Simulation time	190877528256 ps
CPU time	524.31 seconds
Started	Aug 27 06:21:41 AM UTC 24
Finished	Aug 27 06:30:31 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690032319 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.2690032319
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1473593579
Short name	T617
Test name
Test status
Simulation time	407021715952 ps
CPU time	263.4 seconds
Started	Aug 27 06:21:44 AM UTC 24
Finished	Aug 27 06:26:11 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473593579 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.1473593579
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.2337572375
Short name	T231
Test name
Test status
Simulation time	130061102298 ps
CPU time	778.92 seconds
Started	Aug 27 06:22:35 AM UTC 24
Finished	Aug 27 06:35:43 AM UTC 24
Peak memory	211784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337572375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2337572375
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.3265703736
Short name	T602
Test name
Test status
Simulation time	27328196885 ps
CPU time	58.15 seconds
Started	Aug 27 06:22:26 AM UTC 24
Finished	Aug 27 06:23:26 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265703736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3265703736
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.814667951
Short name	T595
Test name
Test status
Simulation time	3298109563 ps
CPU time	14.76 seconds
Started	Aug 27 06:22:24 AM UTC 24
Finished	Aug 27 06:22:41 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814667951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.814667951
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.3732246884
Short name	T581
Test name
Test status
Simulation time	5615414543 ps
CPU time	8.84 seconds
Started	Aug 27 06:21:10 AM UTC 24
Finished	Aug 27 06:21:20 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732246884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3732246884
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.3005730775
Short name	T600
Test name
Test status
Simulation time	11116920845 ps
CPU time	21.34 seconds
Started	Aug 27 06:22:53 AM UTC 24
Finished	Aug 27 06:23:15 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005730775 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.3005730775
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.2055960217
Short name	T606
Test name
Test status
Simulation time	447313003 ps
CPU time	1.28 seconds
Started	Aug 27 06:23:58 AM UTC 24
Finished	Aug 27 06:24:00 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055960217 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2055960217
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.3061629595
Short name	T356
Test name
Test status
Simulation time	332149040188 ps
CPU time	560.44 seconds
Started	Aug 27 06:23:31 AM UTC 24
Finished	Aug 27 06:32:58 AM UTC 24
Peak memory	211532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061629595 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.3061629595
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.763915727
Short name	T374
Test name
Test status
Simulation time	323496516326 ps
CPU time	166.06 seconds
Started	Aug 27 06:23:35 AM UTC 24
Finished	Aug 27 06:26:24 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763915727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.763915727
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.3772337906
Short name	T760
Test name
Test status
Simulation time	489319545015 ps
CPU time	1225.45 seconds
Started	Aug 27 06:23:16 AM UTC 24
Finished	Aug 27 06:43:54 AM UTC 24
Peak memory	212496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772337906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3772337906
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.36723460
Short name	T715
Test name
Test status
Simulation time	328467463391 ps
CPU time	864.48 seconds
Started	Aug 27 06:23:17 AM UTC 24
Finished	Aug 27 06:37:50 AM UTC 24
Peak memory	211540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36723460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.36723460
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.4187860848
Short name	T645
Test name
Test status
Simulation time	165753541527 ps
CPU time	394.21 seconds
Started	Aug 27 06:23:05 AM UTC 24
Finished	Aug 27 06:29:44 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187860848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4187860848
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.2289468221
Short name	T780
Test name
Test status
Simulation time	497636929596 ps
CPU time	1507.29 seconds
Started	Aug 27 06:23:12 AM UTC 24
Finished	Aug 27 06:48:35 AM UTC 24
Peak memory	212548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289468221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.2289468221
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.3964833468
Short name	T330
Test name
Test status
Simulation time	375975803024 ps
CPU time	51.78 seconds
Started	Aug 27 06:23:23 AM UTC 24
Finished	Aug 27 06:24:16 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964833468 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.3964833468
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1354168660
Short name	T661
Test name
Test status
Simulation time	599072940365 ps
CPU time	463.71 seconds
Started	Aug 27 06:23:27 AM UTC 24
Finished	Aug 27 06:31:16 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354168660 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.1354168660
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.3568404440
Short name	T658
Test name
Test status
Simulation time	71156879187 ps
CPU time	443.52 seconds
Started	Aug 27 06:23:38 AM UTC 24
Finished	Aug 27 06:31:07 AM UTC 24
Peak memory	212088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568404440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3568404440
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.2029462225
Short name	T608
Test name
Test status
Simulation time	28388326979 ps
CPU time	45 seconds
Started	Aug 27 06:23:37 AM UTC 24
Finished	Aug 27 06:24:24 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029462225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2029462225
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.190276555
Short name	T605
Test name
Test status
Simulation time	3242786092 ps
CPU time	7.27 seconds
Started	Aug 27 06:23:35 AM UTC 24
Finished	Aug 27 06:23:44 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190276555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.190276555
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.1220171938
Short name	T599
Test name
Test status
Simulation time	6028573105 ps
CPU time	7.62 seconds
Started	Aug 27 06:23:03 AM UTC 24
Finished	Aug 27 06:23:11 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220171938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1220171938
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.1105768739
Short name	T663
Test name
Test status
Simulation time	171382148456 ps
CPU time	470.73 seconds
Started	Aug 27 06:23:52 AM UTC 24
Finished	Aug 27 06:31:48 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105768739 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.1105768739
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.61385750
Short name	T358
Test name
Test status
Simulation time	13072541703 ps
CPU time	10.9 seconds
Started	Aug 27 06:23:45 AM UTC 24
Finished	Aug 27 06:23:57 AM UTC 24
Peak memory	211624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=61385750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.61385750
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.3925915387
Short name	T614
Test name
Test status
Simulation time	472051121 ps
CPU time	1.31 seconds
Started	Aug 27 06:26:02 AM UTC 24
Finished	Aug 27 06:26:04 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925915387 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3925915387
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.1151353888
Short name	T678
Test name
Test status
Simulation time	174773160046 ps
CPU time	507.75 seconds
Started	Aug 27 06:24:31 AM UTC 24
Finished	Aug 27 06:33:05 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151353888 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.1151353888
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.952374222
Short name	T736
Test name
Test status
Simulation time	319362759305 ps
CPU time	984.11 seconds
Started	Aug 27 06:24:17 AM UTC 24
Finished	Aug 27 06:40:51 AM UTC 24
Peak memory	212624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952374222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.952374222
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2015535246
Short name	T659
Test name
Test status
Simulation time	491471707511 ps
CPU time	404.82 seconds
Started	Aug 27 06:24:18 AM UTC 24
Finished	Aug 27 06:31:08 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015535246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.2015535246
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.686807799
Short name	T644
Test name
Test status
Simulation time	327840990707 ps
CPU time	310.64 seconds
Started	Aug 27 06:24:01 AM UTC 24
Finished	Aug 27 06:29:15 AM UTC 24
Peak memory	211500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686807799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.686807799
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.1885762911
Short name	T726
Test name
Test status
Simulation time	324216174803 ps
CPU time	961.65 seconds
Started	Aug 27 06:24:05 AM UTC 24
Finished	Aug 27 06:40:16 AM UTC 24
Peak memory	212484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885762911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.1885762911
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1098704117
Short name	T737
Test name
Test status
Simulation time	394919254841 ps
CPU time	971.54 seconds
Started	Aug 27 06:24:31 AM UTC 24
Finished	Aug 27 06:40:52 AM UTC 24
Peak memory	212544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098704117 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.1098704117
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.498274252
Short name	T711
Test name
Test status
Simulation time	97484890972 ps
CPU time	723.81 seconds
Started	Aug 27 06:25:31 AM UTC 24
Finished	Aug 27 06:37:42 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498274252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.498274252
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.225419415
Short name	T632
Test name
Test status
Simulation time	41935057402 ps
CPU time	131.24 seconds
Started	Aug 27 06:24:53 AM UTC 24
Finished	Aug 27 06:27:07 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225419415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.225419415
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.3607558761
Short name	T611
Test name
Test status
Simulation time	5416699550 ps
CPU time	5.65 seconds
Started	Aug 27 06:24:46 AM UTC 24
Finished	Aug 27 06:24:53 AM UTC 24
Peak memory	211540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607558761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3607558761
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.2824774361
Short name	T607
Test name
Test status
Simulation time	6176649554 ps
CPU time	3.28 seconds
Started	Aug 27 06:24:00 AM UTC 24
Finished	Aug 27 06:24:04 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824774361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2824774361
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.3714389209
Short name	T332
Test name
Test status
Simulation time	469780673850 ps
CPU time	1641.86 seconds
Started	Aug 27 06:25:59 AM UTC 24
Finished	Aug 27 06:53:36 AM UTC 24
Peak memory	229360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714389209 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.3714389209
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.562415894
Short name	T629
Test name
Test status
Simulation time	451322818 ps
CPU time	1.75 seconds
Started	Aug 27 06:26:58 AM UTC 24
Finished	Aug 27 06:27:01 AM UTC 24
Peak memory	210340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562415894 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.562415894
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.3440666576
Short name	T791
Test name
Test status
Simulation time	493090113859 ps
CPU time	1673.52 seconds
Started	Aug 27 06:26:18 AM UTC 24
Finished	Aug 27 06:54:29 AM UTC 24
Peak memory	212748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440666576 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.3440666576
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.2130263286
Short name	T344
Test name
Test status
Simulation time	490042116458 ps
CPU time	339.84 seconds
Started	Aug 27 06:26:12 AM UTC 24
Finished	Aug 27 06:31:56 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130263286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2130263286
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2376538864
Short name	T653
Test name
Test status
Simulation time	320718939990 ps
CPU time	247.93 seconds
Started	Aug 27 06:26:12 AM UTC 24
Finished	Aug 27 06:30:23 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376538864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.2376538864
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.4125010028
Short name	T655
Test name
Test status
Simulation time	166325145766 ps
CPU time	275.43 seconds
Started	Aug 27 06:26:06 AM UTC 24
Finished	Aug 27 06:30:45 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125010028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4125010028
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.212883152
Short name	T633
Test name
Test status
Simulation time	165732549168 ps
CPU time	59.48 seconds
Started	Aug 27 06:26:06 AM UTC 24
Finished	Aug 27 06:27:07 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212883152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.212883152
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.3233519645
Short name	T651
Test name
Test status
Simulation time	396642014148 ps
CPU time	236.19 seconds
Started	Aug 27 06:26:13 AM UTC 24
Finished	Aug 27 06:30:13 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233519645 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.3233519645
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1309532245
Short name	T774
Test name
Test status
Simulation time	592717837063 ps
CPU time	1214.58 seconds
Started	Aug 27 06:26:14 AM UTC 24
Finished	Aug 27 06:46:40 AM UTC 24
Peak memory	212516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309532245 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.1309532245
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.3771128754
Short name	T226
Test name
Test status
Simulation time	115441178744 ps
CPU time	704.92 seconds
Started	Aug 27 06:26:34 AM UTC 24
Finished	Aug 27 06:38:26 AM UTC 24
Peak memory	212088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771128754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3771128754
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.558282502
Short name	T634
Test name
Test status
Simulation time	38057499511 ps
CPU time	40.03 seconds
Started	Aug 27 06:26:28 AM UTC 24
Finished	Aug 27 06:27:09 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558282502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.558282502
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.4004399286
Short name	T624
Test name
Test status
Simulation time	3216888299 ps
CPU time	7.77 seconds
Started	Aug 27 06:26:24 AM UTC 24
Finished	Aug 27 06:26:33 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004399286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4004399286
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.2725323349
Short name	T623
Test name
Test status
Simulation time	5664885437 ps
CPU time	20.29 seconds
Started	Aug 27 06:26:05 AM UTC 24
Finished	Aug 27 06:26:27 AM UTC 24
Peak memory	211292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725323349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2725323349
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.600749824
Short name	T716
Test name
Test status
Simulation time	210422452995 ps
CPU time	650 seconds
Started	Aug 27 06:26:54 AM UTC 24
Finished	Aug 27 06:37:51 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600749824 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.600749824
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2652474459
Short name	T631
Test name
Test status
Simulation time	13435625991 ps
CPU time	12.69 seconds
Started	Aug 27 06:26:53 AM UTC 24
Finished	Aug 27 06:27:07 AM UTC 24
Peak memory	221688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2652474459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.adc_ctrl_stress_all_with_rand_reset.2652474459
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.3575500704
Short name	T641
Test name
Test status
Simulation time	301578884 ps
CPU time	1.51 seconds
Started	Aug 27 06:27:58 AM UTC 24
Finished	Aug 27 06:28:01 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575500704 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3575500704
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.301646834
Short name	T333
Test name
Test status
Simulation time	182061529571 ps
CPU time	111.5 seconds
Started	Aug 27 06:27:16 AM UTC 24
Finished	Aug 27 06:29:10 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301646834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.301646834
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.2230677138
Short name	T648
Test name
Test status
Simulation time	161722976626 ps
CPU time	178.46 seconds
Started	Aug 27 06:27:07 AM UTC 24
Finished	Aug 27 06:30:08 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230677138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2230677138
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1818673015
Short name	T701
Test name
Test status
Simulation time	500760109122 ps
CPU time	543.54 seconds
Started	Aug 27 06:27:08 AM UTC 24
Finished	Aug 27 06:36:17 AM UTC 24
Peak memory	211512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818673015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.1818673015
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.686188877
Short name	T252
Test name
Test status
Simulation time	491983567610 ps
CPU time	736.51 seconds
Started	Aug 27 06:27:01 AM UTC 24
Finished	Aug 27 06:39:25 AM UTC 24
Peak memory	211432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686188877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.686188877
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.780926957
Short name	T764
Test name
Test status
Simulation time	505754691671 ps
CPU time	1013.84 seconds
Started	Aug 27 06:27:04 AM UTC 24
Finished	Aug 27 06:44:07 AM UTC 24
Peak memory	212484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780926957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.780926957
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.499288961
Short name	T746
Test name
Test status
Simulation time	598179997727 ps
CPU time	865.73 seconds
Started	Aug 27 06:27:08 AM UTC 24
Finished	Aug 27 06:41:43 AM UTC 24
Peak memory	211556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499288961 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.499288961
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3417272619
Short name	T684
Test name
Test status
Simulation time	596586577353 ps
CPU time	448.74 seconds
Started	Aug 27 06:27:09 AM UTC 24
Finished	Aug 27 06:34:43 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417272619 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.3417272619
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.1251569438
Short name	T79
Test name
Test status
Simulation time	101312352821 ps
CPU time	706.93 seconds
Started	Aug 27 06:27:35 AM UTC 24
Finished	Aug 27 06:39:29 AM UTC 24
Peak memory	211972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251569438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1251569438
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.3117504123
Short name	T643
Test name
Test status
Simulation time	30960189055 ps
CPU time	91.09 seconds
Started	Aug 27 06:27:27 AM UTC 24
Finished	Aug 27 06:29:00 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117504123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3117504123
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.2637029647
Short name	T638
Test name
Test status
Simulation time	5346020189 ps
CPU time	8.91 seconds
Started	Aug 27 06:27:25 AM UTC 24
Finished	Aug 27 06:27:35 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637029647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2637029647
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.3385936750
Short name	T630
Test name
Test status
Simulation time	5945488995 ps
CPU time	2.34 seconds
Started	Aug 27 06:27:00 AM UTC 24
Finished	Aug 27 06:27:03 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385936750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3385936750
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.300201036
Short name	T349
Test name
Test status
Simulation time	332770924321 ps
CPU time	498.42 seconds
Started	Aug 27 06:27:51 AM UTC 24
Finished	Aug 27 06:36:15 AM UTC 24
Peak memory	211428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300201036 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.300201036
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.309870361
Short name	T640
Test name
Test status
Simulation time	4740330503 ps
CPU time	19.92 seconds
Started	Aug 27 06:27:36 AM UTC 24
Finished	Aug 27 06:27:57 AM UTC 24
Peak memory	221732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=309870361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.309870361
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1322138577
Short name	T71
Test name
Test status
Simulation time	409700244 ps
CPU time	1.45 seconds
Started	Aug 27 05:37:13 AM UTC 24
Finished	Aug 27 05:37:16 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322138577 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1322138577
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3369863753
Short name	T18
Test name
Test status
Simulation time	166053568386 ps
CPU time	63.05 seconds
Started	Aug 27 05:37:02 AM UTC 24
Finished	Aug 27 05:38:07 AM UTC 24
Peak memory	211428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369863753 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.3369863753
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.386038690
Short name	T157
Test name
Test status
Simulation time	209413916136 ps
CPU time	551.95 seconds
Started	Aug 27 05:37:02 AM UTC 24
Finished	Aug 27 05:46:21 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386038690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.386038690
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.1308918801
Short name	T16
Test name
Test status
Simulation time	163713185335 ps
CPU time	42.24 seconds
Started	Aug 27 05:37:00 AM UTC 24
Finished	Aug 27 05:37:43 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308918801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1308918801
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2347349035
Short name	T45
Test name
Test status
Simulation time	330191478727 ps
CPU time	386.03 seconds
Started	Aug 27 05:37:00 AM UTC 24
Finished	Aug 27 05:43:30 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347349035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.2347349035
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.3688000944
Short name	T286
Test name
Test status
Simulation time	489848094980 ps
CPU time	1210.82 seconds
Started	Aug 27 05:36:58 AM UTC 24
Finished	Aug 27 05:57:22 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688000944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3688000944
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3052334649
Short name	T217
Test name
Test status
Simulation time	331835892922 ps
CPU time	841.11 seconds
Started	Aug 27 05:36:58 AM UTC 24
Finished	Aug 27 05:51:09 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052334649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.3052334649
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4112633774
Short name	T49
Test name
Test status
Simulation time	610774551250 ps
CPU time	409.19 seconds
Started	Aug 27 05:37:02 AM UTC 24
Finished	Aug 27 05:43:56 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112633774 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.4112633774
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2938207863
Short name	T179
Test name
Test status
Simulation time	36387427288 ps
CPU time	136.46 seconds
Started	Aug 27 05:37:09 AM UTC 24
Finished	Aug 27 05:39:28 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938207863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2938207863
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.2947866826
Short name	T70
Test name
Test status
Simulation time	4681986252 ps
CPU time	2.12 seconds
Started	Aug 27 05:37:08 AM UTC 24
Finished	Aug 27 05:37:11 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947866826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2947866826
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.2522276882
Short name	T72
Test name
Test status
Simulation time	8043420052 ps
CPU time	5.06 seconds
Started	Aug 27 05:37:11 AM UTC 24
Finished	Aug 27 05:37:17 AM UTC 24
Peak memory	243488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522276882 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2522276882
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.131015562
Short name	T69
Test name
Test status
Simulation time	6031032139 ps
CPU time	8.25 seconds
Started	Aug 27 05:36:58 AM UTC 24
Finished	Aug 27 05:37:09 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131015562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.131015562
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.333139948
Short name	T239
Test name
Test status
Simulation time	204664478347 ps
CPU time	493.09 seconds
Started	Aug 27 05:37:11 AM UTC 24
Finished	Aug 27 05:45:29 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333139948 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.333139948
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1077170016
Short name	T60
Test name
Test status
Simulation time	10013376068 ps
CPU time	16.27 seconds
Started	Aug 27 05:37:09 AM UTC 24
Finished	Aug 27 05:37:27 AM UTC 24
Peak memory	221892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1077170016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.adc_ctrl_stress_all_with_rand_reset.1077170016
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.1223186438
Short name	T649
Test name
Test status
Simulation time	304673247 ps
CPU time	1.31 seconds
Started	Aug 27 06:30:09 AM UTC 24
Finished	Aug 27 06:30:12 AM UTC 24
Peak memory	210340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223186438 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1223186438
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.1574352851
Short name	T664
Test name
Test status
Simulation time	177703756759 ps
CPU time	153.32 seconds
Started	Aug 27 06:29:17 AM UTC 24
Finished	Aug 27 06:31:53 AM UTC 24
Peak memory	211524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574352851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1574352851
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.2721644520
Short name	T674
Test name
Test status
Simulation time	323764834046 ps
CPU time	226.13 seconds
Started	Aug 27 06:28:32 AM UTC 24
Finished	Aug 27 06:32:22 AM UTC 24
Peak memory	211556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721644520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2721644520
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1607682195
Short name	T785
Test name
Test status
Simulation time	489316044504 ps
CPU time	1407.12 seconds
Started	Aug 27 06:28:40 AM UTC 24
Finished	Aug 27 06:52:21 AM UTC 24
Peak memory	212664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607682195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.1607682195
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.2036837088
Short name	T682
Test name
Test status
Simulation time	318173777918 ps
CPU time	361.88 seconds
Started	Aug 27 06:28:17 AM UTC 24
Finished	Aug 27 06:34:23 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036837088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2036837088
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.2602851061
Short name	T675
Test name
Test status
Simulation time	321112956207 ps
CPU time	233.66 seconds
Started	Aug 27 06:28:28 AM UTC 24
Finished	Aug 27 06:32:25 AM UTC 24
Peak memory	211392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602851061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.2602851061
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.1789045335
Short name	T763
Test name
Test status
Simulation time	348292511310 ps
CPU time	892.94 seconds
Started	Aug 27 06:29:00 AM UTC 24
Finished	Aug 27 06:44:02 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789045335 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.1789045335
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1670427342
Short name	T656
Test name
Test status
Simulation time	200020903173 ps
CPU time	104.78 seconds
Started	Aug 27 06:29:06 AM UTC 24
Finished	Aug 27 06:30:52 AM UTC 24
Peak memory	211524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670427342 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.1670427342
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.3873197456
Short name	T729
Test name
Test status
Simulation time	98926971371 ps
CPU time	626 seconds
Started	Aug 27 06:29:54 AM UTC 24
Finished	Aug 27 06:40:26 AM UTC 24
Peak memory	211780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873197456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3873197456
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.1998668945
Short name	T654
Test name
Test status
Simulation time	30163939779 ps
CPU time	33.47 seconds
Started	Aug 27 06:29:52 AM UTC 24
Finished	Aug 27 06:30:27 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998668945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1998668945
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.1782358436
Short name	T646
Test name
Test status
Simulation time	3585450096 ps
CPU time	4.78 seconds
Started	Aug 27 06:29:45 AM UTC 24
Finished	Aug 27 06:29:51 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782358436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1782358436
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.1869520741
Short name	T642
Test name
Test status
Simulation time	5791927185 ps
CPU time	12.84 seconds
Started	Aug 27 06:28:02 AM UTC 24
Finished	Aug 27 06:28:16 AM UTC 24
Peak memory	211292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869520741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1869520741
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.1418437562
Short name	T205
Test name
Test status
Simulation time	508023107104 ps
CPU time	588.66 seconds
Started	Aug 27 06:30:03 AM UTC 24
Finished	Aug 27 06:39:58 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418437562 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.1418437562
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3270374682
Short name	T650
Test name
Test status
Simulation time	4291167850 ps
CPU time	15.09 seconds
Started	Aug 27 06:29:56 AM UTC 24
Finished	Aug 27 06:30:12 AM UTC 24
Peak memory	222000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3270374682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.adc_ctrl_stress_all_with_rand_reset.3270374682
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.3801649171
Short name	T660
Test name
Test status
Simulation time	482886526 ps
CPU time	1.34 seconds
Started	Aug 27 06:31:08 AM UTC 24
Finished	Aug 27 06:31:11 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801649171 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3801649171
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.4044807344
Short name	T691
Test name
Test status
Simulation time	496509566892 ps
CPU time	292.15 seconds
Started	Aug 27 06:30:32 AM UTC 24
Finished	Aug 27 06:35:28 AM UTC 24
Peak memory	211604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044807344 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.4044807344
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.4131740941
Short name	T686
Test name
Test status
Simulation time	504988640446 ps
CPU time	246.75 seconds
Started	Aug 27 06:30:46 AM UTC 24
Finished	Aug 27 06:34:56 AM UTC 24
Peak memory	211524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131740941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4131740941
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.2233488627
Short name	T341
Test name
Test status
Simulation time	492024272049 ps
CPU time	474.39 seconds
Started	Aug 27 06:30:14 AM UTC 24
Finished	Aug 27 06:38:14 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233488627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2233488627
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4006021002
Short name	T786
Test name
Test status
Simulation time	487750559288 ps
CPU time	1328.19 seconds
Started	Aug 27 06:30:22 AM UTC 24
Finished	Aug 27 06:52:43 AM UTC 24
Peak memory	212548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006021002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.4006021002
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.1313487881
Short name	T376
Test name
Test status
Simulation time	167896903417 ps
CPU time	414.93 seconds
Started	Aug 27 06:30:13 AM UTC 24
Finished	Aug 27 06:37:13 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313487881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1313487881
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.3523930617
Short name	T668
Test name
Test status
Simulation time	160080942667 ps
CPU time	114.63 seconds
Started	Aug 27 06:30:13 AM UTC 24
Finished	Aug 27 06:32:10 AM UTC 24
Peak memory	211600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523930617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.3523930617
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.513206064
Short name	T665
Test name
Test status
Simulation time	189768083409 ps
CPU time	87.28 seconds
Started	Aug 27 06:30:25 AM UTC 24
Finished	Aug 27 06:31:54 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513206064 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.513206064
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1001364083
Short name	T677
Test name
Test status
Simulation time	620965634285 ps
CPU time	139.72 seconds
Started	Aug 27 06:30:28 AM UTC 24
Finished	Aug 27 06:32:50 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001364083 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.1001364083
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.347431506
Short name	T233
Test name
Test status
Simulation time	87357391753 ps
CPU time	371.95 seconds
Started	Aug 27 06:31:06 AM UTC 24
Finished	Aug 27 06:37:22 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347431506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.347431506
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.2486841162
Short name	T670
Test name
Test status
Simulation time	37070425357 ps
CPU time	74.23 seconds
Started	Aug 27 06:31:01 AM UTC 24
Finished	Aug 27 06:32:17 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486841162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2486841162
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.1013306333
Short name	T657
Test name
Test status
Simulation time	4505780665 ps
CPU time	6.49 seconds
Started	Aug 27 06:30:53 AM UTC 24
Finished	Aug 27 06:31:01 AM UTC 24
Peak memory	211220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013306333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1013306333
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.2060607243
Short name	T652
Test name
Test status
Simulation time	5899094056 ps
CPU time	7.44 seconds
Started	Aug 27 06:30:12 AM UTC 24
Finished	Aug 27 06:30:21 AM UTC 24
Peak memory	211292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060607243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2060607243
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.586703028
Short name	T275
Test name
Test status
Simulation time	699843761824 ps
CPU time	752.02 seconds
Started	Aug 27 06:31:08 AM UTC 24
Finished	Aug 27 06:43:48 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586703028 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.586703028
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2094865927
Short name	T218
Test name
Test status
Simulation time	64869651755 ps
CPU time	53.9 seconds
Started	Aug 27 06:31:07 AM UTC 24
Finished	Aug 27 06:32:03 AM UTC 24
Peak memory	228024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2094865927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.adc_ctrl_stress_all_with_rand_reset.2094865927
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.2443192138
Short name	T673
Test name
Test status
Simulation time	516163843 ps
CPU time	2.83 seconds
Started	Aug 27 06:32:17 AM UTC 24
Finished	Aug 27 06:32:21 AM UTC 24
Peak memory	211216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443192138 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2443192138
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.4278591053
Short name	T702
Test name
Test status
Simulation time	167868744515 ps
CPU time	262.05 seconds
Started	Aug 27 06:31:57 AM UTC 24
Finished	Aug 27 06:36:22 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278591053 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.4278591053
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.2982205754
Short name	T700
Test name
Test status
Simulation time	164805737932 ps
CPU time	280.7 seconds
Started	Aug 27 06:31:27 AM UTC 24
Finished	Aug 27 06:36:11 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982205754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2982205754
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3320047590
Short name	T721
Test name
Test status
Simulation time	163670025921 ps
CPU time	406.59 seconds
Started	Aug 27 06:31:49 AM UTC 24
Finished	Aug 27 06:38:40 AM UTC 24
Peak memory	211592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320047590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.3320047590
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.2976110950
Short name	T703
Test name
Test status
Simulation time	488163756235 ps
CPU time	321.59 seconds
Started	Aug 27 06:31:17 AM UTC 24
Finished	Aug 27 06:36:43 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976110950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2976110950
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.3070590980
Short name	T680
Test name
Test status
Simulation time	166082619130 ps
CPU time	135.74 seconds
Started	Aug 27 06:31:23 AM UTC 24
Finished	Aug 27 06:33:41 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070590980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.3070590980
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.337139905
Short name	T690
Test name
Test status
Simulation time	419747417123 ps
CPU time	201.63 seconds
Started	Aug 27 06:31:53 AM UTC 24
Finished	Aug 27 06:35:17 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337139905 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.337139905
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3606039318
Short name	T679
Test name
Test status
Simulation time	385419593159 ps
CPU time	91.37 seconds
Started	Aug 27 06:31:55 AM UTC 24
Finished	Aug 27 06:33:28 AM UTC 24
Peak memory	211524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606039318 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.3606039318
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.518461196
Short name	T669
Test name
Test status
Simulation time	28088159627 ps
CPU time	9.32 seconds
Started	Aug 27 06:32:03 AM UTC 24
Finished	Aug 27 06:32:14 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518461196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.518461196
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.3712713159
Short name	T671
Test name
Test status
Simulation time	5216885794 ps
CPU time	12.63 seconds
Started	Aug 27 06:32:03 AM UTC 24
Finished	Aug 27 06:32:17 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712713159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3712713159
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.3495378121
Short name	T662
Test name
Test status
Simulation time	5810513136 ps
CPU time	13.36 seconds
Started	Aug 27 06:31:11 AM UTC 24
Finished	Aug 27 06:31:26 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495378121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3495378121
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.1730427734
Short name	T378
Test name
Test status
Simulation time	499946957561 ps
CPU time	410.08 seconds
Started	Aug 27 06:32:17 AM UTC 24
Finished	Aug 27 06:39:13 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730427734 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.1730427734
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2044256797
Short name	T672
Test name
Test status
Simulation time	807209450 ps
CPU time	4.55 seconds
Started	Aug 27 06:32:14 AM UTC 24
Finished	Aug 27 06:32:20 AM UTC 24
Peak memory	211532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2044256797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.adc_ctrl_stress_all_with_rand_reset.2044256797
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.2928338093
Short name	T685
Test name
Test status
Simulation time	438538100 ps
CPU time	2.53 seconds
Started	Aug 27 06:34:45 AM UTC 24
Finished	Aug 27 06:34:49 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928338093 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2928338093
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.288051373
Short name	T687
Test name
Test status
Simulation time	165644245181 ps
CPU time	119.06 seconds
Started	Aug 27 06:33:06 AM UTC 24
Finished	Aug 27 06:35:07 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288051373 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.288051373
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.2287308084
Short name	T357
Test name
Test status
Simulation time	475127165972 ps
CPU time	1367.2 seconds
Started	Aug 27 06:33:29 AM UTC 24
Finished	Aug 27 06:56:30 AM UTC 24
Peak memory	212596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287308084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2287308084
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.1336237280
Short name	T713
Test name
Test status
Simulation time	495968549936 ps
CPU time	316.51 seconds
Started	Aug 27 06:32:26 AM UTC 24
Finished	Aug 27 06:37:46 AM UTC 24
Peak memory	211556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336237280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1336237280
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3413307312
Short name	T707
Test name
Test status
Simulation time	168911005877 ps
CPU time	280.49 seconds
Started	Aug 27 06:32:35 AM UTC 24
Finished	Aug 27 06:37:19 AM UTC 24
Peak memory	211784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413307312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.3413307312
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.3161233956
Short name	T779
Test name
Test status
Simulation time	329083369210 ps
CPU time	959.24 seconds
Started	Aug 27 06:32:23 AM UTC 24
Finished	Aug 27 06:48:31 AM UTC 24
Peak memory	212568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161233956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3161233956
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.1450919718
Short name	T770
Test name
Test status
Simulation time	331466461538 ps
CPU time	786.96 seconds
Started	Aug 27 06:32:23 AM UTC 24
Finished	Aug 27 06:45:38 AM UTC 24
Peak memory	211616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450919718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.1450919718
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.1331235612
Short name	T381
Test name
Test status
Simulation time	185282784298 ps
CPU time	67.81 seconds
Started	Aug 27 06:32:51 AM UTC 24
Finished	Aug 27 06:34:00 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331235612 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.1331235612
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.96462079
Short name	T693
Test name
Test status
Simulation time	589020316457 ps
CPU time	161.72 seconds
Started	Aug 27 06:32:58 AM UTC 24
Finished	Aug 27 06:35:42 AM UTC 24
Peak memory	211388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96462079 -assert nopostpro c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.96462079
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.680298562
Short name	T755
Test name
Test status
Simulation time	98276358422 ps
CPU time	528.71 seconds
Started	Aug 27 06:34:01 AM UTC 24
Finished	Aug 27 06:42:56 AM UTC 24
Peak memory	211968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680298562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.680298562
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.3038555817
Short name	T697
Test name
Test status
Simulation time	30884432194 ps
CPU time	126.62 seconds
Started	Aug 27 06:33:50 AM UTC 24
Finished	Aug 27 06:35:59 AM UTC 24
Peak memory	211216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038555817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3038555817
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.4018378062
Short name	T681
Test name
Test status
Simulation time	3419686562 ps
CPU time	7.54 seconds
Started	Aug 27 06:33:41 AM UTC 24
Finished	Aug 27 06:33:50 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018378062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4018378062
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.2609914079
Short name	T676
Test name
Test status
Simulation time	5727029586 ps
CPU time	12.57 seconds
Started	Aug 27 06:32:20 AM UTC 24
Finished	Aug 27 06:32:34 AM UTC 24
Peak memory	211292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609914079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2609914079
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.337289211
Short name	T762
Test name
Test status
Simulation time	181706636491 ps
CPU time	545.47 seconds
Started	Aug 27 06:34:44 AM UTC 24
Finished	Aug 27 06:43:56 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337289211 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.337289211
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.581756135
Short name	T683
Test name
Test status
Simulation time	3949645012 ps
CPU time	17.84 seconds
Started	Aug 27 06:34:24 AM UTC 24
Finished	Aug 27 06:34:43 AM UTC 24
Peak memory	221804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=581756135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.581756135
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.852472936
Short name	T698
Test name
Test status
Simulation time	334850946 ps
CPU time	1.16 seconds
Started	Aug 27 06:36:00 AM UTC 24
Finished	Aug 27 06:36:02 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852472936 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.852472936
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.565416834
Short name	T712
Test name
Test status
Simulation time	161772333084 ps
CPU time	132.81 seconds
Started	Aug 27 06:35:28 AM UTC 24
Finished	Aug 27 06:37:43 AM UTC 24
Peak memory	211608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565416834 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.565416834
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.4111653354
Short name	T717
Test name
Test status
Simulation time	165792372276 ps
CPU time	168.26 seconds
Started	Aug 27 06:35:29 AM UTC 24
Finished	Aug 27 06:38:20 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111653354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.4111653354
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.3309049870
Short name	T204
Test name
Test status
Simulation time	330137239111 ps
CPU time	104.92 seconds
Started	Aug 27 06:35:08 AM UTC 24
Finished	Aug 27 06:36:55 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309049870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3309049870
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1172680670
Short name	T758
Test name
Test status
Simulation time	161702343032 ps
CPU time	489.97 seconds
Started	Aug 27 06:35:11 AM UTC 24
Finished	Aug 27 06:43:26 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172680670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.1172680670
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.3139458516
Short name	T794
Test name
Test status
Simulation time	490730800856 ps
CPU time	1394.83 seconds
Started	Aug 27 06:34:57 AM UTC 24
Finished	Aug 27 06:58:26 AM UTC 24
Peak memory	212488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139458516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3139458516
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.2782403697
Short name	T695
Test name
Test status
Simulation time	160666614991 ps
CPU time	44.69 seconds
Started	Aug 27 06:35:03 AM UTC 24
Finished	Aug 27 06:35:49 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782403697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.2782403697
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2121882546
Short name	T730
Test name
Test status
Simulation time	588245868840 ps
CPU time	304.86 seconds
Started	Aug 27 06:35:18 AM UTC 24
Finished	Aug 27 06:40:27 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121882546 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.2121882546
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.2860860962
Short name	T735
Test name
Test status
Simulation time	79944250643 ps
CPU time	289.34 seconds
Started	Aug 27 06:35:48 AM UTC 24
Finished	Aug 27 06:40:40 AM UTC 24
Peak memory	211700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860860962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2860860962
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.1641238920
Short name	T705
Test name
Test status
Simulation time	29256693412 ps
CPU time	81.88 seconds
Started	Aug 27 06:35:44 AM UTC 24
Finished	Aug 27 06:37:07 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641238920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1641238920
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.1331398651
Short name	T696
Test name
Test status
Simulation time	3749568759 ps
CPU time	8.1 seconds
Started	Aug 27 06:35:42 AM UTC 24
Finished	Aug 27 06:35:52 AM UTC 24
Peak memory	211348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331398651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1331398651
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.3898449190
Short name	T689
Test name
Test status
Simulation time	6099824035 ps
CPU time	26.05 seconds
Started	Aug 27 06:34:50 AM UTC 24
Finished	Aug 27 06:35:17 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898449190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3898449190
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.1510954754
Short name	T276
Test name
Test status
Simulation time	480511577368 ps
CPU time	1544.5 seconds
Started	Aug 27 06:35:53 AM UTC 24
Finished	Aug 27 07:01:52 AM UTC 24
Peak memory	223024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510954754 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.1510954754
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2033621162
Short name	T704
Test name
Test status
Simulation time	20379068554 ps
CPU time	54.39 seconds
Started	Aug 27 06:35:50 AM UTC 24
Finished	Aug 27 06:36:46 AM UTC 24
Peak memory	228220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2033621162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.adc_ctrl_stress_all_with_rand_reset.2033621162
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.1505739578
Short name	T709
Test name
Test status
Simulation time	395674511 ps
CPU time	1.24 seconds
Started	Aug 27 06:37:30 AM UTC 24
Finished	Aug 27 06:37:32 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505739578 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1505739578
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.996830916
Short name	T788
Test name
Test status
Simulation time	326954903814 ps
CPU time	964.31 seconds
Started	Aug 27 06:36:55 AM UTC 24
Finished	Aug 27 06:53:10 AM UTC 24
Peak memory	212492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996830916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.996830916
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.674007319
Short name	T728
Test name
Test status
Simulation time	162554769474 ps
CPU time	246.67 seconds
Started	Aug 27 06:36:16 AM UTC 24
Finished	Aug 27 06:40:26 AM UTC 24
Peak memory	211504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674007319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.674007319
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3465119968
Short name	T732
Test name
Test status
Simulation time	162866517949 ps
CPU time	247.11 seconds
Started	Aug 27 06:36:18 AM UTC 24
Finished	Aug 27 06:40:29 AM UTC 24
Peak memory	211784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465119968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.3465119968
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.2024894945
Short name	T342
Test name
Test status
Simulation time	488686999921 ps
CPU time	1032.52 seconds
Started	Aug 27 06:36:09 AM UTC 24
Finished	Aug 27 06:53:32 AM UTC 24
Peak memory	212488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024894945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2024894945
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.2886420080
Short name	T759
Test name
Test status
Simulation time	320449698046 ps
CPU time	431.17 seconds
Started	Aug 27 06:36:12 AM UTC 24
Finished	Aug 27 06:43:28 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886420080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.2886420080
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.685411338
Short name	T750
Test name
Test status
Simulation time	187691589193 ps
CPU time	340.41 seconds
Started	Aug 27 06:36:23 AM UTC 24
Finished	Aug 27 06:42:08 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685411338 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.685411338
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4236585876
Short name	T796
Test name
Test status
Simulation time	589400055134 ps
CPU time	1406.52 seconds
Started	Aug 27 06:36:43 AM UTC 24
Finished	Aug 27 07:00:24 AM UTC 24
Peak memory	212540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236585876 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.4236585876
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.1820580410
Short name	T771
Test name
Test status
Simulation time	83780243111 ps
CPU time	530.14 seconds
Started	Aug 27 06:37:14 AM UTC 24
Finished	Aug 27 06:46:09 AM UTC 24
Peak memory	212088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820580410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1820580410
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.1193319367
Short name	T714
Test name
Test status
Simulation time	36756539125 ps
CPU time	34.06 seconds
Started	Aug 27 06:37:13 AM UTC 24
Finished	Aug 27 06:37:48 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193319367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1193319367
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.1620960743
Short name	T706
Test name
Test status
Simulation time	4313625253 ps
CPU time	3.23 seconds
Started	Aug 27 06:37:08 AM UTC 24
Finished	Aug 27 06:37:12 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620960743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1620960743
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.720070281
Short name	T699
Test name
Test status
Simulation time	5665848862 ps
CPU time	4.47 seconds
Started	Aug 27 06:36:03 AM UTC 24
Finished	Aug 27 06:36:08 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720070281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.720070281
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.4213214814
Short name	T765
Test name
Test status
Simulation time	71830870311 ps
CPU time	411.14 seconds
Started	Aug 27 06:37:23 AM UTC 24
Finished	Aug 27 06:44:19 AM UTC 24
Peak memory	211692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213214814 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.4213214814
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1374492203
Short name	T708
Test name
Test status
Simulation time	9143880677 ps
CPU time	7.9 seconds
Started	Aug 27 06:37:20 AM UTC 24
Finished	Aug 27 06:37:29 AM UTC 24
Peak memory	221936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1374492203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.adc_ctrl_stress_all_with_rand_reset.1374492203
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.1643745180
Short name	T720
Test name
Test status
Simulation time	299090773 ps
CPU time	2.03 seconds
Started	Aug 27 06:38:35 AM UTC 24
Finished	Aug 27 06:38:38 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643745180 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1643745180
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.4248061628
Short name	T757
Test name
Test status
Simulation time	338887836073 ps
CPU time	328.43 seconds
Started	Aug 27 06:37:53 AM UTC 24
Finished	Aug 27 06:43:25 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248061628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4248061628
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.870120251
Short name	T790
Test name
Test status
Simulation time	331125248603 ps
CPU time	970.2 seconds
Started	Aug 27 06:37:44 AM UTC 24
Finished	Aug 27 06:54:05 AM UTC 24
Peak memory	212636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870120251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.870120251
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3201120790
Short name	T740
Test name
Test status
Simulation time	333182796194 ps
CPU time	197.36 seconds
Started	Aug 27 06:37:46 AM UTC 24
Finished	Aug 27 06:41:07 AM UTC 24
Peak memory	211520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201120790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.3201120790
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.534093248
Short name	T772
Test name
Test status
Simulation time	332596320354 ps
CPU time	517.27 seconds
Started	Aug 27 06:37:37 AM UTC 24
Finished	Aug 27 06:46:20 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534093248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.534093248
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.4045605940
Short name	T741
Test name
Test status
Simulation time	333998794106 ps
CPU time	219.14 seconds
Started	Aug 27 06:37:43 AM UTC 24
Finished	Aug 27 06:41:26 AM UTC 24
Peak memory	211392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045605940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.4045605940
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.3030831579
Short name	T326
Test name
Test status
Simulation time	391300373115 ps
CPU time	588.05 seconds
Started	Aug 27 06:37:48 AM UTC 24
Finished	Aug 27 06:47:43 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030831579 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.3030831579
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.662649331
Short name	T747
Test name
Test status
Simulation time	190960107515 ps
CPU time	237.14 seconds
Started	Aug 27 06:37:51 AM UTC 24
Finished	Aug 27 06:41:52 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662649331 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.662649331
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.3743004742
Short name	T787
Test name
Test status
Simulation time	111743037225 ps
CPU time	855.82 seconds
Started	Aug 27 06:38:21 AM UTC 24
Finished	Aug 27 06:52:45 AM UTC 24
Peak memory	212088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743004742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3743004742
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.435504372
Short name	T723
Test name
Test status
Simulation time	30745472020 ps
CPU time	25.25 seconds
Started	Aug 27 06:38:20 AM UTC 24
Finished	Aug 27 06:38:46 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435504372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.435504372
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.624953197
Short name	T718
Test name
Test status
Simulation time	3245361316 ps
CPU time	13.79 seconds
Started	Aug 27 06:38:16 AM UTC 24
Finished	Aug 27 06:38:31 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624953197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.624953197
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.31874382
Short name	T710
Test name
Test status
Simulation time	5664270967 ps
CPU time	2.39 seconds
Started	Aug 27 06:37:33 AM UTC 24
Finished	Aug 27 06:37:36 AM UTC 24
Peak memory	211200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31874382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.31874382
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.1059195652
Short name	T744
Test name
Test status
Simulation time	63100891233 ps
CPU time	178.18 seconds
Started	Aug 27 06:38:31 AM UTC 24
Finished	Aug 27 06:41:32 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059195652 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.1059195652
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.728257026
Short name	T719
Test name
Test status
Simulation time	7870083462 ps
CPU time	6.54 seconds
Started	Aug 27 06:38:27 AM UTC 24
Finished	Aug 27 06:38:34 AM UTC 24
Peak memory	211620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=728257026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.728257026
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.3350963744
Short name	T731
Test name
Test status
Simulation time	424287246 ps
CPU time	1.76 seconds
Started	Aug 27 06:40:25 AM UTC 24
Finished	Aug 27 06:40:28 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350963744 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3350963744
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.1980910592
Short name	T756
Test name
Test status
Simulation time	329382936466 ps
CPU time	232.58 seconds
Started	Aug 27 06:39:30 AM UTC 24
Finished	Aug 27 06:43:25 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980910592 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.1980910592
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.540227002
Short name	T346
Test name
Test status
Simulation time	157602152347 ps
CPU time	111.42 seconds
Started	Aug 27 06:39:34 AM UTC 24
Finished	Aug 27 06:41:27 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540227002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.540227002
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.2289666344
Short name	T793
Test name
Test status
Simulation time	494875090500 ps
CPU time	1126.59 seconds
Started	Aug 27 06:38:47 AM UTC 24
Finished	Aug 27 06:57:45 AM UTC 24
Peak memory	212560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289666344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2289666344
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1060393318
Short name	T797
Test name
Test status
Simulation time	499781367444 ps
CPU time	1338.68 seconds
Started	Aug 27 06:38:52 AM UTC 24
Finished	Aug 27 07:01:24 AM UTC 24
Peak memory	212580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060393318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.1060393318
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.3529491911
Short name	T769
Test name
Test status
Simulation time	164309248782 ps
CPU time	395.67 seconds
Started	Aug 27 06:38:40 AM UTC 24
Finished	Aug 27 06:45:20 AM UTC 24
Peak memory	211532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529491911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3529491911
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.3249641734
Short name	T734
Test name
Test status
Simulation time	165159467024 ps
CPU time	108.5 seconds
Started	Aug 27 06:38:44 AM UTC 24
Finished	Aug 27 06:40:35 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249641734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.3249641734
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.2568500285
Short name	T781
Test name
Test status
Simulation time	334245759384 ps
CPU time	603.39 seconds
Started	Aug 27 06:39:13 AM UTC 24
Finished	Aug 27 06:49:23 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568500285 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.2568500285
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3960307280
Short name	T775
Test name
Test status
Simulation time	424807629226 ps
CPU time	486.77 seconds
Started	Aug 27 06:39:26 AM UTC 24
Finished	Aug 27 06:47:38 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960307280 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.3960307280
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.2664573754
Short name	T778
Test name
Test status
Simulation time	92584302817 ps
CPU time	482.2 seconds
Started	Aug 27 06:40:17 AM UTC 24
Finished	Aug 27 06:48:24 AM UTC 24
Peak memory	211972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664573754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2664573754
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.2137379991
Short name	T733
Test name
Test status
Simulation time	29324698267 ps
CPU time	18.61 seconds
Started	Aug 27 06:40:11 AM UTC 24
Finished	Aug 27 06:40:31 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137379991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2137379991
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.411707629
Short name	T725
Test name
Test status
Simulation time	5054451170 ps
CPU time	10.31 seconds
Started	Aug 27 06:39:59 AM UTC 24
Finished	Aug 27 06:40:10 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411707629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.411707629
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.821719111
Short name	T722
Test name
Test status
Simulation time	5752360384 ps
CPU time	2.91 seconds
Started	Aug 27 06:38:39 AM UTC 24
Finished	Aug 27 06:38:43 AM UTC 24
Peak memory	211212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821719111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.821719111
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.1612885563
Short name	T782
Test name
Test status
Simulation time	172460491384 ps
CPU time	556.2 seconds
Started	Aug 27 06:40:25 AM UTC 24
Finished	Aug 27 06:49:48 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612885563 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.1612885563
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.755369432
Short name	T742
Test name
Test status
Simulation time	170912094587 ps
CPU time	65.17 seconds
Started	Aug 27 06:40:20 AM UTC 24
Finished	Aug 27 06:41:27 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=755369432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.755369432
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.1364943587
Short name	T743
Test name
Test status
Simulation time	385906573 ps
CPU time	1.91 seconds
Started	Aug 27 06:41:26 AM UTC 24
Finished	Aug 27 06:41:29 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364943587 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1364943587
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.118662802
Short name	T379
Test name
Test status
Simulation time	498527121725 ps
CPU time	383.16 seconds
Started	Aug 27 06:40:52 AM UTC 24
Finished	Aug 27 06:47:20 AM UTC 24
Peak memory	211612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118662802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.118662802
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.776403502
Short name	T783
Test name
Test status
Simulation time	496378138204 ps
CPU time	628.99 seconds
Started	Aug 27 06:40:29 AM UTC 24
Finished	Aug 27 06:51:05 AM UTC 24
Peak memory	211436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776403502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.776403502
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2210968449
Short name	T751
Test name
Test status
Simulation time	167241726598 ps
CPU time	104.39 seconds
Started	Aug 27 06:40:29 AM UTC 24
Finished	Aug 27 06:42:16 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210968449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.2210968449
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.3168595926
Short name	T777
Test name
Test status
Simulation time	165343882073 ps
CPU time	441.83 seconds
Started	Aug 27 06:40:27 AM UTC 24
Finished	Aug 27 06:47:54 AM UTC 24
Peak memory	211412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168595926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.3168595926
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.1241129657
Short name	T767
Test name
Test status
Simulation time	341127058555 ps
CPU time	234.29 seconds
Started	Aug 27 06:40:32 AM UTC 24
Finished	Aug 27 06:44:29 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241129657 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.1241129657
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3357967067
Short name	T768
Test name
Test status
Simulation time	401689881127 ps
CPU time	243.46 seconds
Started	Aug 27 06:40:36 AM UTC 24
Finished	Aug 27 06:44:42 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357967067 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.3357967067
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.1828985201
Short name	T387
Test name
Test status
Simulation time	118154223764 ps
CPU time	552.85 seconds
Started	Aug 27 06:41:01 AM UTC 24
Finished	Aug 27 06:50:20 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828985201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1828985201
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.2937103299
Short name	T745
Test name
Test status
Simulation time	37475879236 ps
CPU time	37.92 seconds
Started	Aug 27 06:40:53 AM UTC 24
Finished	Aug 27 06:41:32 AM UTC 24
Peak memory	211220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937103299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2937103299
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.328843741
Short name	T739
Test name
Test status
Simulation time	5098989616 ps
CPU time	6.35 seconds
Started	Aug 27 06:40:53 AM UTC 24
Finished	Aug 27 06:41:00 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328843741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.328843741
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.3418684161
Short name	T738
Test name
Test status
Simulation time	5863773400 ps
CPU time	24.6 seconds
Started	Aug 27 06:40:26 AM UTC 24
Finished	Aug 27 06:40:52 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418684161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3418684161
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.2845961193
Short name	T795
Test name
Test status
Simulation time	282754996133 ps
CPU time	1094.8 seconds
Started	Aug 27 06:41:18 AM UTC 24
Finished	Aug 27 06:59:44 AM UTC 24
Peak memory	223192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845961193 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.2845961193
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.3379134601
Short name	T754
Test name
Test status
Simulation time	419345419 ps
CPU time	0.94 seconds
Started	Aug 27 06:42:51 AM UTC 24
Finished	Aug 27 06:42:54 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379134601 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3379134601
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.249381867
Short name	T784
Test name
Test status
Simulation time	170429516796 ps
CPU time	566.06 seconds
Started	Aug 27 06:41:53 AM UTC 24
Finished	Aug 27 06:51:25 AM UTC 24
Peak memory	211608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249381867 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.249381867
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.528914909
Short name	T377
Test name
Test status
Simulation time	481792641643 ps
CPU time	373.55 seconds
Started	Aug 27 06:41:53 AM UTC 24
Finished	Aug 27 06:48:11 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528914909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.528914909
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2731399688
Short name	T789
Test name
Test status
Simulation time	488546685605 ps
CPU time	704.15 seconds
Started	Aug 27 06:41:33 AM UTC 24
Finished	Aug 27 06:53:24 AM UTC 24
Peak memory	211664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731399688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.2731399688
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.2644661890
Short name	T773
Test name
Test status
Simulation time	328901799569 ps
CPU time	296.82 seconds
Started	Aug 27 06:41:28 AM UTC 24
Finished	Aug 27 06:46:29 AM UTC 24
Peak memory	211496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644661890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2644661890
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.3162272069
Short name	T798
Test name
Test status
Simulation time	489358422979 ps
CPU time	1307.96 seconds
Started	Aug 27 06:41:31 AM UTC 24
Finished	Aug 27 07:03:32 AM UTC 24
Peak memory	212476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162272069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.3162272069
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.1719887248
Short name	T318
Test name
Test status
Simulation time	580612313133 ps
CPU time	801.42 seconds
Started	Aug 27 06:41:44 AM UTC 24
Finished	Aug 27 06:55:14 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719887248 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.1719887248
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1701405669
Short name	T776
Test name
Test status
Simulation time	592360849635 ps
CPU time	347.55 seconds
Started	Aug 27 06:41:50 AM UTC 24
Finished	Aug 27 06:47:42 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701405669 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.1701405669
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.2115317050
Short name	T792
Test name
Test status
Simulation time	119535418390 ps
CPU time	768.41 seconds
Started	Aug 27 06:42:16 AM UTC 24
Finished	Aug 27 06:55:12 AM UTC 24
Peak memory	211700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115317050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2115317050
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.3001146636
Short name	T761
Test name
Test status
Simulation time	30392155608 ps
CPU time	103.65 seconds
Started	Aug 27 06:42:09 AM UTC 24
Finished	Aug 27 06:43:55 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001146636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3001146636
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.3475334779
Short name	T752
Test name
Test status
Simulation time	5392385191 ps
CPU time	18.65 seconds
Started	Aug 27 06:41:57 AM UTC 24
Finished	Aug 27 06:42:17 AM UTC 24
Peak memory	211284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475334779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3475334779
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.3844055168
Short name	T748
Test name
Test status
Simulation time	5925905142 ps
CPU time	23.85 seconds
Started	Aug 27 06:41:27 AM UTC 24
Finished	Aug 27 06:41:53 AM UTC 24
Peak memory	211216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844055168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3844055168
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.870265375
Short name	T31
Test name
Test status
Simulation time	313906665 ps
CPU time	1.86 seconds
Started	Aug 27 05:38:08 AM UTC 24
Finished	Aug 27 05:38:11 AM UTC 24
Peak memory	209800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870265375 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.870265375
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.2861474826
Short name	T238
Test name
Test status
Simulation time	166958000164 ps
CPU time	450.52 seconds
Started	Aug 27 05:37:37 AM UTC 24
Finished	Aug 27 05:45:12 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861474826 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.2861474826
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.1452959923
Short name	T156
Test name
Test status
Simulation time	319901656872 ps
CPU time	196.38 seconds
Started	Aug 27 05:37:20 AM UTC 24
Finished	Aug 27 05:40:39 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452959923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1452959923
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.3680050664
Short name	T249
Test name
Test status
Simulation time	164819675002 ps
CPU time	453.14 seconds
Started	Aug 27 05:37:18 AM UTC 24
Finished	Aug 27 05:44:57 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680050664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3680050664
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.4186644019
Short name	T398
Test name
Test status
Simulation time	164143056896 ps
CPU time	480.44 seconds
Started	Aug 27 05:37:18 AM UTC 24
Finished	Aug 27 05:45:24 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186644019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.4186644019
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.3402928803
Short name	T142
Test name
Test status
Simulation time	400323105764 ps
CPU time	854.69 seconds
Started	Aug 27 05:37:32 AM UTC 24
Finished	Aug 27 05:51:55 AM UTC 24
Peak memory	211608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402928803 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.3402928803
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4040330753
Short name	T489
Test name
Test status
Simulation time	609548669624 ps
CPU time	1617.43 seconds
Started	Aug 27 05:37:32 AM UTC 24
Finished	Aug 27 06:04:44 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040330753 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.4040330753
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2983525631
Short name	T219
Test name
Test status
Simulation time	79347840578 ps
CPU time	475.63 seconds
Started	Aug 27 05:37:56 AM UTC 24
Finished	Aug 27 05:45:56 AM UTC 24
Peak memory	211816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983525631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2983525631
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.3121451049
Short name	T181
Test name
Test status
Simulation time	42861419149 ps
CPU time	94.62 seconds
Started	Aug 27 05:37:53 AM UTC 24
Finished	Aug 27 05:39:29 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121451049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3121451049
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2752108455
Short name	T30
Test name
Test status
Simulation time	3065560083 ps
CPU time	13.6 seconds
Started	Aug 27 05:37:53 AM UTC 24
Finished	Aug 27 05:38:08 AM UTC 24
Peak memory	211200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752108455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2752108455
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.3130347011
Short name	T61
Test name
Test status
Simulation time	5635946260 ps
CPU time	15.34 seconds
Started	Aug 27 05:37:13 AM UTC 24
Finished	Aug 27 05:37:30 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130347011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3130347011
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.1727821891
Short name	T182
Test name
Test status
Simulation time	503511567 ps
CPU time	1.45 seconds
Started	Aug 27 05:39:29 AM UTC 24
Finished	Aug 27 05:39:31 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727821891 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1727821891
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.498655698
Short name	T139
Test name
Test status
Simulation time	409821380234 ps
CPU time	558.6 seconds
Started	Aug 27 05:38:42 AM UTC 24
Finished	Aug 27 05:48:07 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498655698 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.498655698
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.267212579
Short name	T136
Test name
Test status
Simulation time	175397119921 ps
CPU time	68.26 seconds
Started	Aug 27 05:39:02 AM UTC 24
Finished	Aug 27 05:40:12 AM UTC 24
Peak memory	211608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267212579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.267212579
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.1410152636
Short name	T152
Test name
Test status
Simulation time	493367702232 ps
CPU time	1361.55 seconds
Started	Aug 27 05:38:23 AM UTC 24
Finished	Aug 27 06:01:18 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410152636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1410152636
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2739487075
Short name	T403
Test name
Test status
Simulation time	165207099292 ps
CPU time	470.42 seconds
Started	Aug 27 05:38:25 AM UTC 24
Finished	Aug 27 05:46:20 AM UTC 24
Peak memory	211524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739487075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.2739487075
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.3983041723
Short name	T148
Test name
Test status
Simulation time	483316453931 ps
CPU time	526.64 seconds
Started	Aug 27 05:38:20 AM UTC 24
Finished	Aug 27 05:47:13 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983041723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3983041723
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1016022628
Short name	T394
Test name
Test status
Simulation time	339560926633 ps
CPU time	350.12 seconds
Started	Aug 27 05:38:21 AM UTC 24
Finished	Aug 27 05:44:15 AM UTC 24
Peak memory	211392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016022628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.1016022628
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.540829395
Short name	T137
Test name
Test status
Simulation time	371853440286 ps
CPU time	366.79 seconds
Started	Aug 27 05:38:33 AM UTC 24
Finished	Aug 27 05:44:44 AM UTC 24
Peak memory	211692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540829395 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.540829395
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1346814144
Short name	T432
Test name
Test status
Simulation time	412295780704 ps
CPU time	1029.91 seconds
Started	Aug 27 05:38:37 AM UTC 24
Finished	Aug 27 05:55:57 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346814144 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.1346814144
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2086761319
Short name	T75
Test name
Test status
Simulation time	89255844212 ps
CPU time	511.11 seconds
Started	Aug 27 05:39:11 AM UTC 24
Finished	Aug 27 05:47:48 AM UTC 24
Peak memory	211836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086761319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2086761319
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.4228407234
Short name	T184
Test name
Test status
Simulation time	24568773559 ps
CPU time	39.71 seconds
Started	Aug 27 05:39:05 AM UTC 24
Finished	Aug 27 05:39:47 AM UTC 24
Peak memory	211208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228407234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4228407234
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.2303601372
Short name	T180
Test name
Test status
Simulation time	4841183758 ps
CPU time	21.26 seconds
Started	Aug 27 05:39:05 AM UTC 24
Finished	Aug 27 05:39:28 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303601372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2303601372
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.1474443595
Short name	T112
Test name
Test status
Simulation time	6110008423 ps
CPU time	7.9 seconds
Started	Aug 27 05:38:12 AM UTC 24
Finished	Aug 27 05:38:21 AM UTC 24
Peak memory	211276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474443595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1474443595
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3491871439
Short name	T62
Test name
Test status
Simulation time	4062943314 ps
CPU time	16.3 seconds
Started	Aug 27 05:39:21 AM UTC 24
Finished	Aug 27 05:39:39 AM UTC 24
Peak memory	221660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3491871439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.adc_ctrl_stress_all_with_rand_reset.3491871439
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.2367594185
Short name	T170
Test name
Test status
Simulation time	511805894 ps
CPU time	1.85 seconds
Started	Aug 27 05:40:33 AM UTC 24
Finished	Aug 27 05:40:36 AM UTC 24
Peak memory	209796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367594185 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2367594185
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.3119515247
Short name	T244
Test name
Test status
Simulation time	333721356791 ps
CPU time	685.13 seconds
Started	Aug 27 05:40:02 AM UTC 24
Finished	Aug 27 05:51:34 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119515247 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.3119515247
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.2512232179
Short name	T250
Test name
Test status
Simulation time	184025717302 ps
CPU time	584.18 seconds
Started	Aug 27 05:40:10 AM UTC 24
Finished	Aug 27 05:50:01 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512232179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2512232179
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.788857458
Short name	T55
Test name
Test status
Simulation time	330254506716 ps
CPU time	131.51 seconds
Started	Aug 27 05:39:42 AM UTC 24
Finished	Aug 27 05:41:56 AM UTC 24
Peak memory	211544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788857458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.788857458
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.3471111606
Short name	T251
Test name
Test status
Simulation time	483423122789 ps
CPU time	1154.77 seconds
Started	Aug 27 05:39:30 AM UTC 24
Finished	Aug 27 05:58:56 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471111606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3471111606
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.3539393079
Short name	T143
Test name
Test status
Simulation time	163083186687 ps
CPU time	45.96 seconds
Started	Aug 27 05:39:32 AM UTC 24
Finished	Aug 27 05:40:19 AM UTC 24
Peak memory	211416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539393079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.3539393079
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.3236285027
Short name	T347
Test name
Test status
Simulation time	535266675466 ps
CPU time	1487.14 seconds
Started	Aug 27 05:39:44 AM UTC 24
Finished	Aug 27 06:04:45 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236285027 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.3236285027
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1069145346
Short name	T401
Test name
Test status
Simulation time	406195610438 ps
CPU time	364.37 seconds
Started	Aug 27 05:39:47 AM UTC 24
Finished	Aug 27 05:45:56 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069145346 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.1069145346
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.3154245777
Short name	T214
Test name
Test status
Simulation time	109409987433 ps
CPU time	613.35 seconds
Started	Aug 27 05:40:21 AM UTC 24
Finished	Aug 27 05:50:42 AM UTC 24
Peak memory	211888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154245777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3154245777
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.451218866
Short name	T57
Test name
Test status
Simulation time	32257353358 ps
CPU time	103.21 seconds
Started	Aug 27 05:40:20 AM UTC 24
Finished	Aug 27 05:42:06 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451218866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.451218866
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.124090502
Short name	T169
Test name
Test status
Simulation time	3738757697 ps
CPU time	15.62 seconds
Started	Aug 27 05:40:13 AM UTC 24
Finished	Aug 27 05:40:30 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124090502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.124090502
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.729597691
Short name	T183
Test name
Test status
Simulation time	5913662366 ps
CPU time	13.17 seconds
Started	Aug 27 05:39:29 AM UTC 24
Finished	Aug 27 05:39:43 AM UTC 24
Peak memory	211480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729597691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.729597691
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3738821589
Short name	T290
Test name
Test status
Simulation time	406565755099 ps
CPU time	1031.71 seconds
Started	Aug 27 05:40:31 AM UTC 24
Finished	Aug 27 05:57:53 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738821589 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.3738821589
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2668518223
Short name	T63
Test name
Test status
Simulation time	1247322879 ps
CPU time	7.81 seconds
Started	Aug 27 05:40:23 AM UTC 24
Finished	Aug 27 05:40:32 AM UTC 24
Peak memory	211272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2668518223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.adc_ctrl_stress_all_with_rand_reset.2668518223
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1299723491
Short name	T43
Test name
Test status
Simulation time	504751903 ps
CPU time	2.98 seconds
Started	Aug 27 05:42:54 AM UTC 24
Finished	Aug 27 05:42:58 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299723491 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1299723491
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.4135259924
Short name	T149
Test name
Test status
Simulation time	335604269627 ps
CPU time	437.65 seconds
Started	Aug 27 05:41:56 AM UTC 24
Finished	Aug 27 05:49:19 AM UTC 24
Peak memory	211528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135259924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4135259924
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.842585803
Short name	T243
Test name
Test status
Simulation time	167639760903 ps
CPU time	465.12 seconds
Started	Aug 27 05:41:06 AM UTC 24
Finished	Aug 27 05:48:56 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842585803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.842585803
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1997396509
Short name	T424
Test name
Test status
Simulation time	325082903352 ps
CPU time	748.62 seconds
Started	Aug 27 05:41:23 AM UTC 24
Finished	Aug 27 05:53:59 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997396509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.1997396509
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.1486944221
Short name	T47
Test name
Test status
Simulation time	162891010932 ps
CPU time	177.81 seconds
Started	Aug 27 05:40:40 AM UTC 24
Finished	Aug 27 05:43:41 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486944221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1486944221
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.2247367339
Short name	T59
Test name
Test status
Simulation time	328992568289 ps
CPU time	80.09 seconds
Started	Aug 27 05:41:03 AM UTC 24
Finished	Aug 27 05:42:25 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247367339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.2247367339
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3309218838
Short name	T141
Test name
Test status
Simulation time	621197854090 ps
CPU time	539.63 seconds
Started	Aug 27 05:41:27 AM UTC 24
Finished	Aug 27 05:50:32 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309218838 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.3309218838
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1711745007
Short name	T511
Test name
Test status
Simulation time	602041154352 ps
CPU time	1653.72 seconds
Started	Aug 27 05:41:42 AM UTC 24
Finished	Aug 27 06:09:32 AM UTC 24
Peak memory	211472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711745007 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.1711745007
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.433068757
Short name	T223
Test name
Test status
Simulation time	97431608945 ps
CPU time	461.41 seconds
Started	Aug 27 05:42:09 AM UTC 24
Finished	Aug 27 05:49:55 AM UTC 24
Peak memory	211696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433068757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.433068757
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.2021913653
Short name	T48
Test name
Test status
Simulation time	28641184725 ps
CPU time	102.37 seconds
Started	Aug 27 05:42:07 AM UTC 24
Finished	Aug 27 05:43:51 AM UTC 24
Peak memory	211280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021913653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2021913653
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.101710775
Short name	T58
Test name
Test status
Simulation time	3797829264 ps
CPU time	7.85 seconds
Started	Aug 27 05:41:59 AM UTC 24
Finished	Aug 27 05:42:07 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101710775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.101710775
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.2335450412
Short name	T393
Test name
Test status
Simulation time	5800116823 ps
CPU time	23.94 seconds
Started	Aug 27 05:40:37 AM UTC 24
Finished	Aug 27 05:41:02 AM UTC 24
Peak memory	211204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335450412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2335450412
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1418241706
Short name	T32
Test name
Test status
Simulation time	5229423240 ps
CPU time	22.94 seconds
Started	Aug 27 05:42:26 AM UTC 24
Finished	Aug 27 05:42:50 AM UTC 24
Peak memory	221676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1418241706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.adc_ctrl_stress_all_with_rand_reset.1418241706
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.733681576
Short name	T396
Test name
Test status
Simulation time	487571208 ps
CPU time	2.71 seconds
Started	Aug 27 05:44:57 AM UTC 24
Finished	Aug 27 05:45:01 AM UTC 24
Peak memory	211148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733681576 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.733681576
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2555555719
Short name	T277
Test name
Test status
Simulation time	340218391350 ps
CPU time	1042.95 seconds
Started	Aug 27 05:44:12 AM UTC 24
Finished	Aug 27 06:01:46 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555555719 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.2555555719
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.1732312316
Short name	T261
Test name
Test status
Simulation time	170593170146 ps
CPU time	341.58 seconds
Started	Aug 27 05:44:16 AM UTC 24
Finished	Aug 27 05:50:02 AM UTC 24
Peak memory	211868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732312316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1732312316
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.908318661
Short name	T266
Test name
Test status
Simulation time	162426599093 ps
CPU time	537.34 seconds
Started	Aug 27 05:43:33 AM UTC 24
Finished	Aug 27 05:52:37 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908318661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.908318661
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2829220229
Short name	T474
Test name
Test status
Simulation time	329190530436 ps
CPU time	1130.05 seconds
Started	Aug 27 05:43:41 AM UTC 24
Finished	Aug 27 06:02:43 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829220229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.2829220229
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.3345074547
Short name	T138
Test name
Test status
Simulation time	485779708934 ps
CPU time	218.19 seconds
Started	Aug 27 05:43:28 AM UTC 24
Finished	Aug 27 05:47:10 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345074547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3345074547
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2754758695
Short name	T408
Test name
Test status
Simulation time	162777597267 ps
CPU time	351.4 seconds
Started	Aug 27 05:43:31 AM UTC 24
Finished	Aug 27 05:49:27 AM UTC 24
Peak memory	211616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754758695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.2754758695
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.3269931999
Short name	T265
Test name
Test status
Simulation time	403753635416 ps
CPU time	688.91 seconds
Started	Aug 27 05:43:52 AM UTC 24
Finished	Aug 27 05:55:28 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269931999 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.3269931999
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1774645512
Short name	T409
Test name
Test status
Simulation time	605546474420 ps
CPU time	334.96 seconds
Started	Aug 27 05:43:57 AM UTC 24
Finished	Aug 27 05:49:36 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774645512 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.1774645512
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.285858692
Short name	T228
Test name
Test status
Simulation time	96876749663 ps
CPU time	582.79 seconds
Started	Aug 27 05:44:45 AM UTC 24
Finished	Aug 27 05:54:34 AM UTC 24
Peak memory	211756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285858692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.285858692
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.928762002
Short name	T400
Test name
Test status
Simulation time	39186431317 ps
CPU time	39.05 seconds
Started	Aug 27 05:44:45 AM UTC 24
Finished	Aug 27 05:45:25 AM UTC 24
Peak memory	211476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928762002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.928762002
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.1689510806
Short name	T395
Test name
Test status
Simulation time	4753514439 ps
CPU time	19.27 seconds
Started	Aug 27 05:44:24 AM UTC 24
Finished	Aug 27 05:44:44 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689510806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1689510806
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.873456658
Short name	T44
Test name
Test status
Simulation time	6152126456 ps
CPU time	27.44 seconds
Started	Aug 27 05:42:59 AM UTC 24
Finished	Aug 27 05:43:28 AM UTC 24
Peak memory	211288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873456658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.873456658
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.2099670202
Short name	T256
Test name
Test status
Simulation time	279300381879 ps
CPU time	1329.57 seconds
Started	Aug 27 05:44:49 AM UTC 24
Finished	Aug 27 06:07:11 AM UTC 24
Peak memory	221772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099670202 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.2099670202
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.414102688
Short name	T64
Test name
Test status
Simulation time	11752268892 ps
CPU time	31.34 seconds
Started	Aug 27 05:44:47 AM UTC 24
Finished	Aug 27 05:45:20 AM UTC 24
Peak memory	222264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=414102688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.414102688
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest