Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1150635	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1125652

1

T1

3

T2

32

T3

132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2004106	1			T1	1		T3	162		T5	81
values[0x0]	135251	1			T1	1		T2	25		T3	40
values[0x1]	136930	1			T1	5		T2	36		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	921774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1354513

1

T1

3

T2

36

T3

150

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7298	1			T3	2		T6	1		T9	1
valid_sources[0x01]	7978	1			T3	1		T5	87		T9	1
valid_sources[0x02]	11178	1			T6	4		T12	73		T13	8
valid_sources[0x03]	7776	1			T6	2		T11	1		T12	27
valid_sources[0x04]	6732	1			T3	3		T9	1		T12	80
valid_sources[0x05]	7942	1			T21	3		T9	2		T11	3
valid_sources[0x06]	11577	1			T3	2		T12	49		T13	18
valid_sources[0x07]	6837	1			T11	2		T12	36		T13	17
valid_sources[0x08]	6947	1			T3	1		T11	5		T12	34
valid_sources[0x09]	7663	1			T3	1		T7	1		T9	3
valid_sources[0x0a]	15279	1			T3	1		T6	3		T9	1
valid_sources[0x0b]	18106	1			T3	3		T9	2		T12	44
valid_sources[0x0c]	7648	1			T12	60		T13	18		T42	4
valid_sources[0x0d]	6769	1			T9	2		T12	46		T13	15
valid_sources[0x0e]	11075	1			T12	11		T13	14		T42	1
valid_sources[0x0f]	9291	1			T9	1		T11	1		T12	30
valid_sources[0x10]	7641	1			T12	48		T13	18		T14	9
valid_sources[0x11]	12159	1			T9	1		T10	1		T11	1
valid_sources[0x12]	10875	1			T9	1		T12	98		T13	27
valid_sources[0x13]	6696	1			T3	1		T6	1		T12	24
valid_sources[0x14]	7220	1			T12	56		T13	16		T14	15
valid_sources[0x15]	6586	1			T6	1		T10	1		T12	63
valid_sources[0x16]	9581	1			T11	2		T12	32		T13	8
valid_sources[0x17]	8736	1			T3	1		T12	59		T13	22
valid_sources[0x18]	7117	1			T3	2		T9	1		T10	1
valid_sources[0x19]	7676	1			T12	16		T13	19		T15	8
valid_sources[0x1a]	6828	1			T3	1		T12	22		T13	13
valid_sources[0x1b]	6421	1			T3	2		T6	2		T8	13
valid_sources[0x1c]	8098	1			T3	3		T10	1		T12	52
valid_sources[0x1d]	6564	1			T3	1		T12	12		T13	17
valid_sources[0x1e]	6803	1			T3	1		T6	1		T11	2
valid_sources[0x1f]	11229	1			T3	1		T6	2		T12	26
valid_sources[0x20]	11216	1			T3	2		T6	1		T7	1
valid_sources[0x21]	6786	1			T3	2		T9	1		T10	1
valid_sources[0x22]	6826	1			T6	1		T12	26		T13	17
valid_sources[0x23]	12177	1			T7	1		T10	2		T24	5
valid_sources[0x24]	11758	1			T7	2		T12	64		T13	15
valid_sources[0x25]	6720	1			T3	1		T6	1		T9	3
valid_sources[0x26]	7060	1			T6	1		T8	48		T11	1
valid_sources[0x27]	6788	1			T9	1		T12	47		T13	36
valid_sources[0x28]	7403	1			T6	1		T10	2		T12	35
valid_sources[0x29]	6682	1			T3	1		T12	44		T13	10
valid_sources[0x2a]	7018	1			T9	2		T13	16		T38	1
valid_sources[0x2b]	11325	1			T1	7		T3	1		T12	35
valid_sources[0x2c]	6769	1			T3	1		T6	1		T12	51
valid_sources[0x2d]	8339	1			T11	2		T12	8		T13	21
valid_sources[0x2e]	8768	1			T6	3		T12	80		T13	26
valid_sources[0x2f]	6592	1			T3	2		T8	1		T12	53
valid_sources[0x30]	7743	1			T3	4		T12	65		T13	20
valid_sources[0x31]	16786	1			T3	3		T8	12		T9	1
valid_sources[0x32]	6643	1			T3	2		T6	1		T8	7
valid_sources[0x33]	6771	1			T3	1		T9	2		T10	2
valid_sources[0x34]	8929	1			T12	37		T13	25		T38	1
valid_sources[0x35]	11110	1			T6	2		T9	1		T12	53
valid_sources[0x36]	7256	1			T6	1		T7	1		T11	1
valid_sources[0x37]	12255	1			T9	1		T11	2		T12	84
valid_sources[0x38]	7069	1			T3	1		T9	1		T12	30
valid_sources[0x39]	12394	1			T3	2		T12	79		T13	19
valid_sources[0x3a]	6433	1			T6	2		T9	1		T12	70
valid_sources[0x3b]	9172	1			T3	2		T6	1		T11	1
valid_sources[0x3c]	6920	1			T3	1		T11	2		T12	83
valid_sources[0x3d]	7125	1			T3	1		T11	2		T12	73
valid_sources[0x3e]	12069	1			T3	1		T5	43		T7	2
valid_sources[0x3f]	6611	1			T3	6		T12	42		T13	17
valid_sources[0x40]	7141	1			T7	1		T8	8		T12	15
valid_sources[0x41]	6883	1			T12	79		T13	21		T40	1
valid_sources[0x42]	20695	1			T7	2		T11	1		T12	6
valid_sources[0x43]	7891	1			T11	1		T12	31		T13	13
valid_sources[0x44]	7676	1			T3	2		T9	1		T12	66
valid_sources[0x45]	8020	1			T6	2		T8	152		T11	1
valid_sources[0x46]	11888	1			T12	42		T13	17		T15	10
valid_sources[0x47]	10858	1			T11	1		T12	34		T13	12
valid_sources[0x48]	10636	1			T3	1		T9	2		T11	1
valid_sources[0x49]	15344	1			T6	1		T11	1		T12	29
valid_sources[0x4a]	8371	1			T3	1		T6	3		T24	1
valid_sources[0x4b]	7166	1			T3	2		T12	29		T13	12
valid_sources[0x4c]	7032	1			T3	1		T23	3		T12	23
valid_sources[0x4d]	7843	1			T9	1		T11	2		T12	39
valid_sources[0x4e]	7618	1			T8	2		T11	2		T12	36
valid_sources[0x4f]	7764	1			T9	3		T11	4		T12	65
valid_sources[0x50]	6745	1			T3	3		T6	1		T9	2
valid_sources[0x51]	11226	1			T3	1		T9	1		T12	111
valid_sources[0x52]	6551	1			T3	1		T9	1		T12	86
valid_sources[0x53]	6739	1			T8	15		T12	34		T13	16
valid_sources[0x54]	6779	1			T3	3		T6	1		T12	48
valid_sources[0x55]	7002	1			T9	2		T12	77		T13	16
valid_sources[0x56]	6719	1			T3	1		T10	1		T11	1
valid_sources[0x57]	7439	1			T6	1		T12	10		T13	16
valid_sources[0x58]	10575	1			T10	2		T11	1		T12	34
valid_sources[0x59]	13919	1			T3	2		T6	1		T11	1
valid_sources[0x5a]	7596	1			T9	3		T11	1		T12	84
valid_sources[0x5b]	6665	1			T3	2		T6	1		T9	2
valid_sources[0x5c]	6787	1			T6	1		T9	2		T12	44
valid_sources[0x5d]	10117	1			T9	1		T12	51		T13	15
valid_sources[0x5e]	10990	1			T12	69		T13	27		T40	1
valid_sources[0x5f]	9347	1			T3	3		T6	1		T7	1
valid_sources[0x60]	15571	1			T7	2		T12	50		T13	19
valid_sources[0x61]	9593	1			T7	2		T10	1		T11	3
valid_sources[0x62]	15397	1			T3	2		T9	3		T12	154
valid_sources[0x63]	12151	1			T3	2		T12	63		T13	13
valid_sources[0x64]	6955	1			T6	1		T12	41		T13	19
valid_sources[0x65]	6806	1			T3	3		T12	78		T13	14
valid_sources[0x66]	8579	1			T9	1		T12	32		T13	23
valid_sources[0x67]	9403	1			T6	2		T8	55		T9	1
valid_sources[0x68]	6867	1			T3	1		T11	2		T26	144
valid_sources[0x69]	8063	1			T3	5		T9	1		T12	64
valid_sources[0x6a]	24273	1			T24	3		T12	87		T13	17
valid_sources[0x6b]	6938	1			T3	2		T7	2		T8	19
valid_sources[0x6c]	8445	1			T11	1		T12	64		T13	29
valid_sources[0x6d]	6883	1			T3	1		T11	2		T12	37
valid_sources[0x6e]	7351	1			T12	35		T13	21		T15	3
valid_sources[0x6f]	6840	1			T9	1		T12	61		T13	24
valid_sources[0x70]	6720	1			T3	1		T12	32		T13	16
valid_sources[0x71]	7668	1			T6	1		T11	2		T12	52
valid_sources[0x72]	11039	1			T9	3		T11	4		T12	40
valid_sources[0x73]	6698	1			T12	43		T13	12		T15	2
valid_sources[0x74]	7399	1			T3	3		T12	61		T13	17
valid_sources[0x75]	6768	1			T3	1		T9	1		T11	2
valid_sources[0x76]	6725	1			T6	1		T9	2		T12	45
valid_sources[0x77]	7754	1			T3	1		T7	1		T11	1
valid_sources[0x78]	11380	1			T11	1		T12	74		T13	22
valid_sources[0x79]	11155	1			T3	1		T6	1		T12	58
valid_sources[0x7a]	11433	1			T6	1		T9	4		T11	1
valid_sources[0x7b]	7345	1			T3	2		T12	77		T13	16
valid_sources[0x7c]	9047	1			T3	1		T6	1		T12	30
valid_sources[0x7d]	7624	1			T3	1		T12	76		T13	9
valid_sources[0x7e]	7199	1			T9	1		T10	1		T12	67
valid_sources[0x7f]	15321	1			T6	1		T11	1		T12	142
valid_sources[0x80]	7332	1			T6	1		T12	52		T13	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

999493

1

T3

81

T5

38

T6

42

values[0x0]

all_enables

biggest_size

73050

1

T1

1

T2

16

T3

27

values[0x1]

all_enables

biggest_size

53109

1

T1

2

T2

16

T3

24