Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	25042	1			T12	24		T13	7		T15	8
auto[PWRUP]	102	1			T56	2		T57	2		T59	2
auto[ONEST_0]	58	1			T55	3		T58	2		T373	4
auto[ONEST_021]	17	1			T60	1		T55	1		T374	1
auto[ONEST_1]	90	1			T55	1		T56	1		T57	1
auto[ONEST_DONE]	2	1			T375	1		T376	1		-	-
auto[LP_0]	93	1			T60	2		T55	1		T57	2
auto[LP_021]	24	1			T55	2		T57	1		T58	1
auto[LP_1]	94	1			T56	1		T57	2		T59	2
auto[LP_EVAL]	62	1			T60	1		T55	1		T56	1
auto[LP_SLP]	484	1			T60	5		T55	4		T56	5
auto[LP_PWRUP]	24	1			T60	1		T377	1		T378	1
auto[NP_0]	127	1			T18	1		T60	2		T55	3
auto[NP_021]	34	1			T58	1		T379	1		T380	3
auto[NP_1]	150	1			T60	3		T55	2		T57	2
auto[NP_EVAL]	28	1			T55	1		T59	1		T377	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T60

1

T373

1

T380

1

min

24524

1

T12

24

T13

7

T15

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24530	1			T12	24		T13	7		T15	8
pow[0x1]	10	1			T380	1		T108	1		T265	1
pow[0x2]	19	1			T57	1		T59	1		T61	2
pow[0x3]	28	1			T60	2		T57	1		T61	1
pow[0x4]	76	1			T55	1		T59	1		T61	1
pow[0x5]	114	1			T56	2		T57	2		T61	1
pow[0x6]	241	1			T60	5		T55	1		T56	2
pow[0x7]	462	1			T60	7		T55	4		T56	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

194

1

T60

1

T55

1

T56

1

min

24067

1

T12

24

T13

7

T15

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24067	1			T12	24		T13	7		T15	8
pow[0x1]	1	1			T57	1		-	-		-	-
pow[0x2]	1	1			T381	1		-	-		-	-
pow[0x3]	1	1			T55	1		-	-		-	-
pow[0x6]	2	1			T244	1		T382	1		-	-
pow[0x7]	3	1			T59	1		T383	1		T384	1
pow[0x8]	3	1			T374	1		T385	1		T320	1
pow[0x9]	6	1			T60	1		T61	1		T386	1
pow[0xa]	20	1			T60	1		T373	1		T377	2
pow[0xb]	32	1			T56	3		T58	1		T380	1
pow[0xc]	68	1			T60	2		T55	1		T56	1
pow[0xd]	146	1			T60	2		T55	3		T56	1
pow[0xe]	277	1			T60	2		T56	2		T57	3
pow[0xf]	563	1			T60	10		T55	9		T56	4