Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2124	1			T3	5		T21	10		T8	5
auto[PWRUP]	132	1			T48	1		T60	1		T55	1
auto[ONEST_0]	70	1			T14	1		T40	1		T18	1
auto[ONEST_021]	22	1			T40	1		T60	2		T59	1
auto[ONEST_1]	82	1			T59	1		T61	1		T373	2
auto[ONEST_DONE]	5	1			T49	1		T56	1		T348	1
auto[LP_0]	127	1			T8	1		T14	2		T18	1
auto[LP_021]	35	1			T55	1		T57	1		T58	1
auto[LP_1]	135	1			T56	1		T57	1		T61	1
auto[LP_EVAL]	46	1			T14	1		T55	1		T57	1
auto[LP_SLP]	490	1			T18	1		T49	1		T50	1
auto[LP_PWRUP]	21	1			T14	1		T20	1		T55	1
auto[NP_0]	158	1			T14	2		T18	2		T20	2
auto[NP_021]	41	1			T49	2		T60	2		T56	1
auto[NP_1]	194	1			T3	1		T8	3		T49	1
auto[NP_EVAL]	26	1			T3	1		T28	1		T61	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T59

1

T374

1

T244

1

min

1741

1

T3

7

T21

10

T8

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1760	1			T3	7		T21	10		T8	9
pow[0x1]	8	1			T238	1		T387	1		T348	1
pow[0x2]	20	1			T216	1		T59	1		T379	1
pow[0x3]	41	1			T14	1		T57	1		T377	1
pow[0x4]	58	1			T56	1		T61	1		T58	1
pow[0x5]	116	1			T60	3		T57	1		T59	1
pow[0x6]	240	1			T60	3		T56	5		T28	1
pow[0x7]	504	1			T14	1		T18	1		T60	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

197

1

T60

1

T56

2

T57

2

min

1228

1

T3

5

T21

10

T8

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1239	1			T3	5		T21	10		T8	6
pow[0x1]	24	1			T3	1		T18	1		T48	1
pow[0x2]	14	1			T14	1		T49	1		T50	1
pow[0x3]	24	1			T3	1		T18	1		T28	2
pow[0x4]	10	1			T8	3		T14	1		T20	2
pow[0x5]	3	1			T388	1		T375	1		T389	1
pow[0x6]	2	1			T60	1		T58	1		-	-
pow[0x7]	4	1			T70	1		T390	1		T386	1
pow[0x8]	5	1			T61	1		T380	1		T283	1
pow[0x9]	10	1			T56	1		T390	1		T95	1
pow[0xa]	16	1			T61	1		T373	2		T388	1
pow[0xb]	34	1			T57	1		T59	1		T377	2
pow[0xc]	68	1			T60	2		T57	2		T59	1
pow[0xd]	131	1			T60	2		T55	1		T56	2
pow[0xe]	288	1			T60	4		T55	4		T56	4
pow[0xf]	517	1			T18	1		T60	7		T55	5