Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1189826	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1168731

1

T1

5

T2

59

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2080974	1			T1	1		T2	81		T4	81
values[0x0]	138108	1			T1	9		T2	28		T3	20
values[0x1]	139475	1			T1	7		T2	35		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	952608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1405949

1

T1

5

T2

68

T3

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8051	1			T2	4		T12	3		T13	1
valid_sources[0x01]	6941	1			T1	3		T5	4		T11	1
valid_sources[0x02]	12891	1			T1	2		T5	2		T12	3
valid_sources[0x03]	7520	1			T5	3		T9	13		T11	1
valid_sources[0x04]	7294	1			T9	5		T12	4		T13	3
valid_sources[0x05]	7483	1			T2	1		T5	4		T8	2
valid_sources[0x06]	7022	1			T5	1		T10	1		T12	3
valid_sources[0x07]	7017	1			T1	1		T12	6		T13	2
valid_sources[0x08]	8079	1			T5	6		T12	3		T14	15
valid_sources[0x09]	7199	1			T2	1		T5	11		T12	4
valid_sources[0x0a]	7034	1			T5	5		T10	1		T12	2
valid_sources[0x0b]	12244	1			T12	2		T13	6		T15	50
valid_sources[0x0c]	11126	1			T2	2		T5	2		T11	1
valid_sources[0x0d]	6853	1			T12	1		T14	14		T15	41
valid_sources[0x0e]	9773	1			T11	1		T12	4		T13	2
valid_sources[0x0f]	6958	1			T5	11		T11	1		T12	5
valid_sources[0x10]	20806	1			T11	1		T12	2		T14	22
valid_sources[0x11]	8350	1			T5	1		T12	1		T14	5
valid_sources[0x12]	17397	1			T5	3		T11	1		T12	4
valid_sources[0x13]	8562	1			T5	4		T12	5		T14	9
valid_sources[0x14]	6868	1			T2	2		T5	3		T12	8
valid_sources[0x15]	7304	1			T11	1		T12	4		T13	10
valid_sources[0x16]	15664	1			T2	4		T10	5		T11	1
valid_sources[0x17]	7351	1			T5	6		T8	1		T11	1
valid_sources[0x18]	11431	1			T10	1		T12	2		T13	2
valid_sources[0x19]	7276	1			T9	15		T12	3		T14	4
valid_sources[0x1a]	7704	1			T2	1		T5	1		T8	3
valid_sources[0x1b]	11562	1			T9	12		T12	9		T13	3
valid_sources[0x1c]	7151	1			T12	5		T14	20		T15	39
valid_sources[0x1d]	6854	1			T5	2		T12	2		T13	1
valid_sources[0x1e]	8276	1			T5	8		T12	3		T13	2
valid_sources[0x1f]	7195	1			T2	1		T5	13		T9	8
valid_sources[0x20]	19659	1			T23	1		T12	3		T13	5
valid_sources[0x21]	7016	1			T5	4		T12	3		T13	2
valid_sources[0x22]	21073	1			T12	2		T14	1		T15	25
valid_sources[0x23]	15732	1			T2	7		T12	4		T13	7
valid_sources[0x24]	11632	1			T5	6		T12	3		T13	2
valid_sources[0x25]	7727	1			T1	1		T2	6		T5	5
valid_sources[0x26]	11391	1			T5	4		T12	7		T14	9
valid_sources[0x27]	7048	1			T5	11		T12	1		T14	22
valid_sources[0x28]	9849	1			T1	1		T2	4		T12	6
valid_sources[0x29]	7060	1			T2	2		T12	3		T13	3
valid_sources[0x2a]	9588	1			T2	5		T5	4		T10	1
valid_sources[0x2b]	7040	1			T2	1		T5	7		T12	1
valid_sources[0x2c]	8886	1			T5	2		T12	1		T13	1
valid_sources[0x2d]	7927	1			T5	2		T10	1		T12	6
valid_sources[0x2e]	8362	1			T11	1		T12	4		T13	2
valid_sources[0x2f]	7293	1			T12	3		T13	2		T14	2
valid_sources[0x30]	8239	1			T12	6		T13	2		T14	2
valid_sources[0x31]	12597	1			T2	1		T12	4		T14	19
valid_sources[0x32]	11562	1			T22	3		T5	1		T11	1
valid_sources[0x33]	12938	1			T9	17		T11	1		T12	5
valid_sources[0x34]	7510	1			T5	9		T12	3		T13	2
valid_sources[0x35]	8148	1			T5	4		T12	4		T13	2
valid_sources[0x36]	6756	1			T11	1		T12	3		T13	5
valid_sources[0x37]	11488	1			T5	1		T12	1		T14	9
valid_sources[0x38]	11390	1			T2	4		T12	2		T13	6
valid_sources[0x39]	9671	1			T2	3		T12	5		T14	11
valid_sources[0x3a]	12377	1			T12	1		T14	16		T34	1
valid_sources[0x3b]	12849	1			T5	4		T8	1		T9	6
valid_sources[0x3c]	11951	1			T8	2		T12	5		T14	7
valid_sources[0x3d]	7290	1			T5	6		T10	2		T12	5
valid_sources[0x3e]	6898	1			T2	1		T5	14		T12	2
valid_sources[0x3f]	19929	1			T5	2		T11	1		T12	2
valid_sources[0x40]	7847	1			T2	3		T5	4		T12	5
valid_sources[0x41]	10934	1			T9	11		T10	4		T12	3
valid_sources[0x42]	8280	1			T8	1		T9	28		T12	3
valid_sources[0x43]	7306	1			T2	4		T5	4		T12	5
valid_sources[0x44]	7141	1			T12	8		T14	8		T34	2
valid_sources[0x45]	7948	1			T2	1		T12	2		T13	10
valid_sources[0x46]	7263	1			T5	2		T9	1		T12	4
valid_sources[0x47]	9629	1			T2	1		T5	2		T12	3
valid_sources[0x48]	8294	1			T5	1		T10	1		T12	4
valid_sources[0x49]	8698	1			T5	1		T12	3		T13	6
valid_sources[0x4a]	7069	1			T12	2		T14	3		T15	41
valid_sources[0x4b]	7325	1			T5	1		T12	5		T14	14
valid_sources[0x4c]	6857	1			T5	1		T9	7		T12	5
valid_sources[0x4d]	11378	1			T12	2		T14	11		T15	50
valid_sources[0x4e]	7836	1			T5	6		T12	4		T14	14
valid_sources[0x4f]	17371	1			T11	1		T12	5		T13	5
valid_sources[0x50]	12991	1			T2	3		T5	4		T10	1
valid_sources[0x51]	7155	1			T10	2		T12	3		T14	22
valid_sources[0x52]	6760	1			T12	8		T13	3		T14	43
valid_sources[0x53]	18713	1			T10	1		T12	4		T14	15
valid_sources[0x54]	8307	1			T12	1		T14	22		T15	34
valid_sources[0x55]	7001	1			T5	5		T12	3		T14	5
valid_sources[0x56]	7900	1			T12	3		T14	4		T34	1
valid_sources[0x57]	7054	1			T8	1		T10	1		T12	9
valid_sources[0x58]	7222	1			T2	1		T4	144		T5	4
valid_sources[0x59]	9489	1			T2	1		T8	1		T12	6
valid_sources[0x5a]	16540	1			T5	2		T8	1		T9	2
valid_sources[0x5b]	7071	1			T1	1		T11	1		T12	2
valid_sources[0x5c]	8094	1			T9	4		T12	2		T34	1
valid_sources[0x5d]	11480	1			T5	6		T10	1		T13	7
valid_sources[0x5e]	7092	1			T5	2		T9	6		T12	6
valid_sources[0x5f]	13370	1			T5	3		T12	5		T13	4
valid_sources[0x60]	8412	1			T2	3		T8	3		T12	4
valid_sources[0x61]	11059	1			T12	4		T14	36		T34	2
valid_sources[0x62]	7223	1			T5	1		T9	2		T12	5
valid_sources[0x63]	6842	1			T12	1		T13	7		T14	12
valid_sources[0x64]	8162	1			T5	1		T12	5		T13	4
valid_sources[0x65]	8106	1			T2	2		T12	3		T13	1
valid_sources[0x66]	6974	1			T7	144		T11	1		T12	13
valid_sources[0x67]	6948	1			T8	1		T12	3		T13	7
valid_sources[0x68]	7006	1			T8	1		T12	2		T14	16
valid_sources[0x69]	10899	1			T2	2		T5	1		T12	4
valid_sources[0x6a]	12537	1			T21	3		T5	4		T12	4
valid_sources[0x6b]	8285	1			T2	1		T5	2		T12	2
valid_sources[0x6c]	7303	1			T5	9		T12	5		T13	2
valid_sources[0x6d]	9506	1			T2	1		T11	1		T12	2
valid_sources[0x6e]	7005	1			T5	4		T8	3		T11	1
valid_sources[0x6f]	7027	1			T5	4		T12	3		T13	6
valid_sources[0x70]	6900	1			T12	1		T13	1		T14	31
valid_sources[0x71]	6940	1			T2	3		T8	1		T11	1
valid_sources[0x72]	6921	1			T5	6		T12	4		T15	20
valid_sources[0x73]	12135	1			T12	3		T14	8		T15	20
valid_sources[0x74]	13510	1			T1	2		T5	2		T12	1
valid_sources[0x75]	7326	1			T12	3		T13	5		T14	20
valid_sources[0x76]	7508	1			T5	3		T12	4		T13	1
valid_sources[0x77]	6637	1			T5	10		T12	4		T13	2
valid_sources[0x78]	19440	1			T10	3		T12	4		T13	2
valid_sources[0x79]	7847	1			T2	1		T5	11		T8	2
valid_sources[0x7a]	8095	1			T12	3		T13	4		T14	1
valid_sources[0x7b]	11148	1			T5	4		T9	8		T12	3
valid_sources[0x7c]	8185	1			T2	1		T5	1		T8	3
valid_sources[0x7d]	11321	1			T5	9		T9	19		T11	1
valid_sources[0x7e]	8594	1			T12	5		T13	1		T14	2
valid_sources[0x7f]	11332	1			T5	1		T9	9		T12	5
valid_sources[0x80]	8128	1			T8	1		T12	3		T13	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1036195

1

T1

1

T2

35

T4

40

values[0x0]

all_enables

biggest_size

76661

1

T1

3

T2

16

T3

13

values[0x1]

all_enables

biggest_size

55875

1

T1

1

T2

8

T3

13