Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	25146	1			T12	9		T14	8		T15	18
auto[PWRUP]	86	1			T49	3		T50	2		T51	1
auto[ONEST_0]	56	1			T48	3		T49	1		T50	3
auto[ONEST_021]	15	1			T50	2		T207	1		T208	1
auto[ONEST_1]	68	1			T49	3		T51	4		T52	1
auto[ONEST_DONE]	3	1			T209	1		T210	1		T211	1
auto[LP_0]	102	1			T48	1		T54	3		T212	2
auto[LP_021]	26	1			T50	2		T51	1		T52	1
auto[LP_1]	104	1			T48	1		T49	1		T54	1
auto[LP_EVAL]	64	1			T49	1		T42	4		T50	2
auto[LP_SLP]	418	1			T48	3		T49	5		T54	5
auto[LP_PWRUP]	21	1			T54	1		T50	1		T213	1
auto[NP_0]	117	1			T48	3		T49	4		T54	1
auto[NP_021]	30	1			T54	2		T207	1		T214	1
auto[NP_1]	124	1			T48	1		T50	1		T215	5
auto[NP_EVAL]	23	1			T50	2		T212	1		T213	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

2

1

T215

1

T57

1

-

-

min

24741

1

T12

9

T14

8

T15

18

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24749	1			T12	9		T14	8		T15	18
pow[0x1]	10	1			T207	1		T209	1		T208	1
pow[0x2]	18	1			T212	1		T215	1		T44	1
pow[0x3]	24	1			T49	1		T50	1		T212	1
pow[0x4]	52	1			T51	1		T52	2		T213	3
pow[0x5]	95	1			T49	2		T42	1		T54	2
pow[0x6]	212	1			T48	1		T49	1		T42	1
pow[0x7]	412	1			T48	6		T49	8		T54	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

185

1

T48

1

T49

4

T42

1

min

24333

1

T12

9

T14

8

T15

18

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24333	1			T12	9		T14	8		T15	18
pow[0x6]	2	1			T52	1		T216	1		-	-
pow[0x7]	2	1			T217	1		T218	1		-	-
pow[0x8]	3	1			T49	1		T219	1		T220	1
pow[0x9]	10	1			T213	1		T156	1		T216	1
pow[0xa]	11	1			T54	1		T50	1		T51	1
pow[0xb]	33	1			T54	2		T50	1		T52	1
pow[0xc]	54	1			T48	2		T49	2		T54	1
pow[0xd]	123	1			T49	1		T54	2		T50	2
pow[0xe]	208	1			T48	2		T49	1		T42	1
pow[0xf]	464	1			T48	4		T49	8		T42	1