Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2054	1			T21	20		T23	20		T5	10
auto[PWRUP]	115	1			T48	1		T42	1		T43	2
auto[ONEST_0]	70	1			T13	1		T19	1		T41	1
auto[ONEST_021]	16	1			T49	1		T44	1		T357	1
auto[ONEST_1]	85	1			T19	1		T41	1		T48	2
auto[ONEST_DONE]	3	1			T50	1		T358	1		T359	1
auto[LP_0]	117	1			T5	1		T13	1		T48	1
auto[LP_021]	23	1			T50	1		T52	1		T156	1
auto[LP_1]	105	1			T5	1		T48	1		T49	1
auto[LP_EVAL]	42	1			T48	1		T49	1		T42	2
auto[LP_SLP]	388	1			T5	2		T9	2		T48	2
auto[LP_PWRUP]	27	1			T54	1		T212	1		T156	1
auto[NP_0]	163	1			T9	1		T13	1		T19	2
auto[NP_021]	43	1			T48	1		T49	1		T42	1
auto[NP_1]	166	1			T5	1		T40	3		T49	2
auto[NP_EVAL]	20	1			T5	1		T48	2		T26	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T42

1

T50

1

T51

1

min

1685

1

T21

20

T23

20

T5

14

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1696	1			T21	20		T23	20		T5	15
pow[0x1]	10	1			T5	1		T13	1		T31	1
pow[0x2]	17	1			T49	2		T50	1		T215	1
pow[0x3]	33	1			T48	1		T50	1		T215	1
pow[0x4]	59	1			T48	2		T49	1		T42	1
pow[0x5]	112	1			T48	2		T42	1		T54	1
pow[0x6]	247	1			T48	2		T49	3		T43	1
pow[0x7]	413	1			T41	1		T48	4		T49	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

163

1

T48

2

T54

2

T50

1

min

1285

1

T21

20

T23

20

T5

14

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1293	1			T21	20		T23	20		T5	14
pow[0x1]	15	1			T5	2		T43	1		T32	1
pow[0x2]	8	1			T19	2		T27	1		T360	1
pow[0x3]	19	1			T13	1		T25	1		T26	1
pow[0x4]	21	1			T40	3		T42	1		T26	2
pow[0x6]	3	1			T361	1		T362	1		T57	1
pow[0x7]	2	1			T363	1		T364	1		-	-
pow[0x8]	5	1			T213	1		T360	1		T365	1
pow[0x9]	6	1			T366	1		T55	1		T361	1
pow[0xa]	12	1			T216	1		T209	1		T358	1
pow[0xb]	27	1			T48	1		T49	1		T52	1
pow[0xc]	61	1			T48	1		T49	1		T50	1
pow[0xd]	117	1			T49	4		T50	1		T215	2
pow[0xe]	234	1			T48	2		T49	2		T42	1
pow[0xf]	494	1			T41	1		T48	5		T49	3