Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	31127697	31054257	0	0
FsmStateHwReset_A	1048	1048	0	0
FsmStateSwReset_A	31127697	6615	0	0
LpSampleCntHwReset_A	1048	1048	0	0
LpSampleCntSwReset_A	31127697	6615	0	0
NpSampleCntHwReset_A	1048	1048	0	0
NpSampleCntSwReset_A	31127697	6615	0	0
PwrupTimerCntHwReset_A	1048	1048	0	0
PwrupTimerCntSwReset_A	31127697	6615	0	0
WakeupTimerCntHwReset_A	1048	1048	0	0
WakeupTimerCntSwReset_A	31127697	6615	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31127697	31054257	0	0
T1	79	1	0	0
T2	1206	1117	0	0
T3	773	680	0	0
T4	1173	1079	0	0
T5	87	1	0	0
T6	5949	5860	0	0
T7	1191	1125	0	0
T21	63	1	0	0
T22	80	1	0	0
T23	88	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31127697	6615	0	0
T12	39534	9	0	0
T13	407	0	0	0
T14	36511	8	0	0
T15	65734	18	0	0
T16	33761	8	0	0
T17	34965	5	0	0
T18	0	14	0	0
T20	0	14	0	0
T24	53	0	0	0
T33	78	0	0	0
T34	1175	0	0	0
T35	787	0	0	0
T38	0	11	0	0
T39	0	15	0	0
T45	0	7	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31127697	6615	0	0
T12	39534	9	0	0
T13	407	0	0	0
T14	36511	8	0	0
T15	65734	18	0	0
T16	33761	8	0	0
T17	34965	5	0	0
T18	0	14	0	0
T20	0	14	0	0
T24	53	0	0	0
T33	78	0	0	0
T34	1175	0	0	0
T35	787	0	0	0
T38	0	11	0	0
T39	0	15	0	0
T45	0	7	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31127697	6615	0	0
T12	39534	9	0	0
T13	407	0	0	0
T14	36511	8	0	0
T15	65734	18	0	0
T16	33761	8	0	0
T17	34965	5	0	0
T18	0	14	0	0
T20	0	14	0	0
T24	53	0	0	0
T33	78	0	0	0
T34	1175	0	0	0
T35	787	0	0	0
T38	0	11	0	0
T39	0	15	0	0
T45	0	7	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31127697	6615	0	0
T12	39534	9	0	0
T13	407	0	0	0
T14	36511	8	0	0
T15	65734	18	0	0
T16	33761	8	0	0
T17	34965	5	0	0
T18	0	14	0	0
T20	0	14	0	0
T24	53	0	0	0
T33	78	0	0	0
T34	1175	0	0	0
T35	787	0	0	0
T38	0	11	0	0
T39	0	15	0	0
T45	0	7	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31127697	6615	0	0
T12	39534	9	0	0
T13	407	0	0	0
T14	36511	8	0	0
T15	65734	18	0	0
T16	33761	8	0	0
T17	34965	5	0	0
T18	0	14	0	0
T20	0	14	0	0
T24	53	0	0	0
T33	78	0	0	0
T34	1175	0	0	0
T35	787	0	0	0
T38	0	11	0	0
T39	0	15	0	0
T45	0	7	0	0