Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2413	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2105	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2586	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2494	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2290	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2521	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2303	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2458	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2302	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2456	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2285	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2257	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2378	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2335	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2395	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2593	0	0
adc_en_ctl_rd_A	2147483647	1808	0	0
adc_fsm_rst_rd_A	2147483647	1739	0	0
adc_intr_ctl_rd_A	2147483647	2456	0	0
adc_lp_sample_ctl_rd_A	2147483647	1888	0	0
adc_pd_ctl_rd_A	2147483647	2296	0	0
adc_sample_ctl_rd_A	2147483647	1696	0	0
adc_wakeup_ctl_rd_A	2147483647	1801	0	0
intr_enable_rd_A	2147483647	2410	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2413	0	0
T13	274137	43	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	43	0	0
T24	180077	0	0	0
T25	0	9	0	0
T26	0	45	0	0
T27	0	53	0	0
T28	0	17	0	0
T29	0	38	0	0
T30	0	23	0	0
T31	0	23	0	0
T32	0	16	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T13	274137	47	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	37	0	0
T24	180077	0	0	0
T25	0	22	0	0
T26	0	31	0	0
T27	0	34	0	0
T28	0	28	0	0
T29	0	20	0	0
T30	0	18	0	0
T31	0	11	0	0
T32	0	27	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2586	0	0
T13	274137	31	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	33	0	0
T24	180077	0	0	0
T25	0	1	0	0
T26	0	51	0	0
T27	0	33	0	0
T28	0	17	0	0
T29	0	26	0	0
T30	0	23	0	0
T31	0	22	0	0
T32	0	14	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2494	0	0
T13	274137	35	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	27	0	0
T24	180077	0	0	0
T25	0	46	0	0
T26	0	43	0	0
T27	0	34	0	0
T28	0	10	0	0
T29	0	34	0	0
T30	0	15	0	0
T31	0	20	0	0
T32	0	14	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2290	0	0
T13	274137	37	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	36	0	0
T24	180077	0	0	0
T25	0	15	0	0
T26	0	44	0	0
T27	0	49	0	0
T28	0	21	0	0
T29	0	29	0	0
T30	0	22	0	0
T31	0	10	0	0
T32	0	17	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2521	0	0
T13	274137	45	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	33	0	0
T24	180077	0	0	0
T25	0	17	0	0
T26	0	31	0	0
T27	0	53	0	0
T28	0	22	0	0
T29	0	31	0	0
T30	0	31	0	0
T31	0	13	0	0
T32	0	15	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2303	0	0
T13	274137	39	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	36	0	0
T24	180077	0	0	0
T25	0	20	0	0
T26	0	32	0	0
T27	0	41	0	0
T28	0	17	0	0
T29	0	44	0	0
T30	0	18	0	0
T31	0	19	0	0
T32	0	26	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2458	0	0
T13	274137	43	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	31	0	0
T24	180077	0	0	0
T25	0	20	0	0
T26	0	39	0	0
T27	0	56	0	0
T28	0	29	0	0
T29	0	23	0	0
T30	0	14	0	0
T31	0	11	0	0
T32	0	22	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2302	0	0
T13	274137	35	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	31	0	0
T24	180077	0	0	0
T25	0	28	0	0
T26	0	53	0	0
T27	0	36	0	0
T28	0	10	0	0
T29	0	41	0	0
T30	0	12	0	0
T31	0	15	0	0
T32	0	12	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T13	274137	36	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	25	0	0
T24	180077	0	0	0
T25	0	25	0	0
T26	0	32	0	0
T27	0	28	0	0
T28	0	15	0	0
T29	0	27	0	0
T30	0	17	0	0
T31	0	12	0	0
T32	0	13	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2285	0	0
T13	274137	45	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	43	0	0
T24	180077	0	0	0
T25	0	15	0	0
T26	0	46	0	0
T27	0	40	0	0
T28	0	18	0	0
T29	0	26	0	0
T30	0	20	0	0
T31	0	16	0	0
T32	0	14	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2257	0	0
T13	274137	40	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	34	0	0
T24	180077	0	0	0
T25	0	7	0	0
T26	0	48	0	0
T27	0	49	0	0
T28	0	8	0	0
T29	0	29	0	0
T30	0	22	0	0
T31	0	22	0	0
T32	0	11	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2378	0	0
T13	274137	32	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	41	0	0
T24	180077	0	0	0
T25	0	16	0	0
T26	0	40	0	0
T27	0	56	0	0
T28	0	11	0	0
T29	0	28	0	0
T30	0	16	0	0
T31	0	18	0	0
T32	0	21	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2335	0	0
T13	274137	28	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	37	0	0
T24	180077	0	0	0
T25	0	15	0	0
T26	0	22	0	0
T27	0	24	0	0
T28	0	12	0	0
T29	0	33	0	0
T30	0	18	0	0
T31	0	19	0	0
T32	0	24	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2395	0	0
T13	274137	31	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	36	0	0
T24	180077	0	0	0
T25	0	28	0	0
T26	0	27	0	0
T27	0	48	0	0
T28	0	24	0	0
T29	0	23	0	0
T30	0	40	0	0
T31	0	12	0	0
T32	0	22	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2593	0	0
T13	274137	29	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	50	0	0
T24	180077	0	0	0
T25	0	10	0	0
T26	0	40	0	0
T27	0	39	0	0
T28	0	16	0	0
T29	0	44	0	0
T30	0	7	0	0
T31	0	17	0	0
T32	0	21	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1808	0	0
T13	274137	38	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	32	0	0
T24	180077	0	0	0
T25	0	17	0	0
T26	0	30	0	0
T27	0	34	0	0
T28	0	14	0	0
T29	0	7	0	0
T30	0	28	0	0
T31	0	6	0	0
T32	0	23	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T13	274137	43	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	49	0	0
T24	180077	0	0	0
T25	0	44	0	0
T26	0	31	0	0
T27	0	35	0	0
T28	0	22	0	0
T29	0	18	0	0
T30	0	28	0	0
T31	0	9	0	0
T32	0	26	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T13	274137	41	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	27	0	0
T24	180077	0	0	0
T25	0	4	0	0
T26	0	30	0	0
T27	0	51	0	0
T28	0	19	0	0
T29	0	39	0	0
T30	0	23	0	0
T31	0	22	0	0
T32	0	19	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T13	274137	61	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	26	0	0
T24	180077	0	0	0
T25	0	39	0	0
T26	0	43	0	0
T27	0	36	0	0
T28	0	9	0	0
T29	0	32	0	0
T30	0	10	0	0
T31	0	19	0	0
T32	0	8	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2296	0	0
T13	274137	35	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	46	0	0
T24	180077	0	0	0
T25	0	8	0	0
T26	0	52	0	0
T27	0	36	0	0
T28	0	21	0	0
T29	0	35	0	0
T30	0	25	0	0
T31	0	26	0	0
T32	0	9	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1696	0	0
T13	274137	45	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	39	0	0
T24	180077	0	0	0
T25	0	15	0	0
T26	0	42	0	0
T27	0	53	0	0
T28	0	18	0	0
T29	0	13	0	0
T30	0	26	0	0
T31	0	16	0	0
T32	0	19	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1801	0	0
T13	274137	34	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	30	0	0
T24	180077	0	0	0
T25	0	7	0	0
T26	0	48	0	0
T27	0	27	0	0
T28	0	33	0	0
T29	0	22	0	0
T30	0	11	0	0
T31	0	9	0	0
T32	0	13	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2410	0	0
T13	274137	58	0	0
T14	894507	0	0	0
T15	197204	0	0	0
T16	371376	0	0	0
T17	297210	0	0	0
T19	0	37	0	0
T24	180077	0	0	0
T25	0	22	0	0
T26	0	38	0	0
T27	0	54	0	0
T28	0	7	0	0
T29	0	42	0	0
T30	0	66	0	0
T31	0	22	0	0
T33	40542	0	0	0
T34	41181	0	0	0
T35	193236	0	0	0
T36	211375	0	0	0
T37	0	12	0	0