Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1227662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1197778

1

T1

65

T2

5

T3

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2147917	1			T1	81		T2	1		T21	1
values[0x0]	137775	1			T1	22		T2	4		T3	21
values[0x1]	139748	1			T1	41		T2	3		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	982385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1443055

1

T1

82

T2

5

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7043	1			T26	7		T13	13		T14	33
valid_sources[0x01]	8429	1			T4	1		T11	4		T13	21
valid_sources[0x02]	9619	1			T1	1		T4	1		T13	21
valid_sources[0x03]	10841	1			T1	1		T4	1		T13	16
valid_sources[0x04]	7021	1			T1	8		T26	12		T13	9
valid_sources[0x05]	7612	1			T4	1		T8	1		T13	12
valid_sources[0x06]	6934	1			T12	2		T13	9		T14	6
valid_sources[0x07]	7040	1			T4	1		T11	2		T13	14
valid_sources[0x08]	7213	1			T11	2		T13	13		T14	40
valid_sources[0x09]	7314	1			T13	21		T14	32		T15	48
valid_sources[0x0a]	11595	1			T1	1		T13	10		T14	19
valid_sources[0x0b]	7962	1			T4	2		T12	1		T13	8
valid_sources[0x0c]	7846	1			T1	3		T12	4		T13	13
valid_sources[0x0d]	8632	1			T4	1		T11	3		T12	3
valid_sources[0x0e]	7356	1			T11	2		T12	3		T13	10
valid_sources[0x0f]	7249	1			T8	1		T11	4		T26	3
valid_sources[0x10]	7791	1			T11	1		T13	18		T14	6
valid_sources[0x11]	6893	1			T4	1		T13	11		T14	17
valid_sources[0x12]	19984	1			T1	1		T4	1		T11	3
valid_sources[0x13]	6741	1			T1	2		T12	1		T13	18
valid_sources[0x14]	7228	1			T1	1		T13	15		T14	12
valid_sources[0x15]	6609	1			T5	8		T13	7		T14	16
valid_sources[0x16]	17535	1			T8	1		T12	2		T13	13
valid_sources[0x17]	6729	1			T4	1		T12	1		T13	8
valid_sources[0x18]	9508	1			T1	1		T11	2		T12	1
valid_sources[0x19]	6736	1			T4	1		T13	9		T14	10
valid_sources[0x1a]	7169	1			T1	1		T4	1		T6	30
valid_sources[0x1b]	6912	1			T11	3		T13	15		T14	27
valid_sources[0x1c]	6911	1			T11	1		T13	9		T14	22
valid_sources[0x1d]	12264	1			T1	1		T11	3		T13	9
valid_sources[0x1e]	11476	1			T1	2		T4	1		T13	14
valid_sources[0x1f]	12016	1			T4	1		T8	1		T13	9
valid_sources[0x20]	8901	1			T1	1		T11	1		T13	9
valid_sources[0x21]	6725	1			T1	1		T4	2		T12	2
valid_sources[0x22]	7032	1			T1	1		T11	1		T13	14
valid_sources[0x23]	7683	1			T11	7		T12	5		T13	10
valid_sources[0x24]	11135	1			T12	8		T13	17		T14	6
valid_sources[0x25]	6990	1			T13	1		T14	14		T15	3
valid_sources[0x26]	6810	1			T1	1		T4	1		T5	7
valid_sources[0x27]	7233	1			T1	1		T4	1		T12	3
valid_sources[0x28]	11440	1			T23	1		T8	1		T13	7
valid_sources[0x29]	20517	1			T11	6		T13	8		T14	1
valid_sources[0x2a]	7223	1			T13	11		T14	24		T16	19
valid_sources[0x2b]	8048	1			T4	1		T8	1		T11	3
valid_sources[0x2c]	6928	1			T13	11		T14	15		T15	8
valid_sources[0x2d]	6946	1			T4	1		T13	14		T14	29
valid_sources[0x2e]	19316	1			T11	1		T13	6		T27	1
valid_sources[0x2f]	7231	1			T13	14		T14	6		T15	23
valid_sources[0x30]	8190	1			T4	1		T13	1		T14	12
valid_sources[0x31]	7925	1			T8	1		T13	7		T14	10
valid_sources[0x32]	6631	1			T4	1		T8	1		T11	12
valid_sources[0x33]	11143	1			T13	21		T14	8		T15	5
valid_sources[0x34]	19645	1			T8	1		T12	2		T13	17
valid_sources[0x35]	13845	1			T1	1		T4	1		T11	4
valid_sources[0x36]	11713	1			T1	3		T11	2		T13	11
valid_sources[0x37]	9921	1			T4	2		T8	1		T13	16
valid_sources[0x38]	16266	1			T4	1		T13	16		T14	41
valid_sources[0x39]	6967	1			T11	1		T13	16		T14	17
valid_sources[0x3a]	7226	1			T4	2		T8	1		T13	9
valid_sources[0x3b]	6694	1			T11	4		T12	3		T13	9
valid_sources[0x3c]	6700	1			T1	1		T11	1		T12	1
valid_sources[0x3d]	7591	1			T11	3		T13	14		T14	6
valid_sources[0x3e]	7210	1			T8	1		T12	2		T13	15
valid_sources[0x3f]	11346	1			T1	1		T4	1		T13	13
valid_sources[0x40]	6747	1			T3	43		T4	1		T12	1
valid_sources[0x41]	15546	1			T1	8		T4	1		T11	4
valid_sources[0x42]	6571	1			T8	1		T26	4		T13	16
valid_sources[0x43]	6539	1			T12	2		T13	11		T14	14
valid_sources[0x44]	10896	1			T8	2		T11	7		T12	5
valid_sources[0x45]	7068	1			T12	1		T13	11		T14	15
valid_sources[0x46]	7763	1			T11	3		T13	15		T14	15
valid_sources[0x47]	12104	1			T4	2		T8	1		T11	3
valid_sources[0x48]	11853	1			T1	1		T8	1		T13	9
valid_sources[0x49]	11005	1			T5	8		T13	23		T14	21
valid_sources[0x4a]	6859	1			T1	1		T13	11		T14	10
valid_sources[0x4b]	6797	1			T1	1		T13	7		T14	22
valid_sources[0x4c]	6653	1			T1	1		T4	1		T11	4
valid_sources[0x4d]	6936	1			T1	1		T4	2		T11	2
valid_sources[0x4e]	10117	1			T4	1		T8	1		T13	18
valid_sources[0x4f]	6730	1			T1	1		T4	1		T5	15
valid_sources[0x50]	21708	1			T1	2		T11	2		T13	8
valid_sources[0x51]	6701	1			T4	2		T13	11		T14	31
valid_sources[0x52]	6720	1			T23	1		T8	1		T13	12
valid_sources[0x53]	23930	1			T4	3		T8	1		T11	1
valid_sources[0x54]	9263	1			T1	2		T4	1		T13	8
valid_sources[0x55]	7047	1			T1	2		T4	1		T8	1
valid_sources[0x56]	8483	1			T11	2		T12	4		T13	15
valid_sources[0x57]	6535	1			T2	3		T4	1		T13	11
valid_sources[0x58]	11094	1			T11	5		T26	5		T13	12
valid_sources[0x59]	10176	1			T13	11		T14	51		T15	4
valid_sources[0x5a]	7650	1			T11	13		T12	5		T13	13
valid_sources[0x5b]	6676	1			T1	2		T13	19		T14	21
valid_sources[0x5c]	6711	1			T1	2		T13	11		T14	6
valid_sources[0x5d]	7172	1			T1	1		T4	1		T5	6
valid_sources[0x5e]	11131	1			T4	1		T12	1		T13	15
valid_sources[0x5f]	8731	1			T4	1		T11	11		T12	1
valid_sources[0x60]	7265	1			T2	1		T4	1		T13	9
valid_sources[0x61]	6822	1			T1	1		T13	16		T14	12
valid_sources[0x62]	11940	1			T1	1		T4	1		T12	1
valid_sources[0x63]	9953	1			T1	3		T4	2		T8	2
valid_sources[0x64]	12322	1			T4	1		T12	1		T13	14
valid_sources[0x65]	6758	1			T6	1		T11	3		T13	14
valid_sources[0x66]	14816	1			T4	2		T13	11		T14	9
valid_sources[0x67]	6836	1			T12	7		T13	9		T14	9
valid_sources[0x68]	7945	1			T1	2		T13	8		T14	13
valid_sources[0x69]	6884	1			T11	2		T13	9		T14	11
valid_sources[0x6a]	7693	1			T4	1		T11	3		T26	3
valid_sources[0x6b]	8445	1			T12	7		T13	7		T15	26
valid_sources[0x6c]	14098	1			T1	3		T13	16		T14	4
valid_sources[0x6d]	12866	1			T4	1		T8	1		T11	2
valid_sources[0x6e]	11189	1			T4	1		T11	2		T12	5
valid_sources[0x6f]	7946	1			T1	1		T4	1		T13	16
valid_sources[0x70]	7011	1			T11	1		T12	1		T13	16
valid_sources[0x71]	7105	1			T1	1		T11	8		T12	2
valid_sources[0x72]	7075	1			T1	1		T4	1		T11	1
valid_sources[0x73]	6750	1			T1	1		T4	1		T12	2
valid_sources[0x74]	7415	1			T1	2		T4	2		T11	1
valid_sources[0x75]	7496	1			T1	1		T12	2		T13	8
valid_sources[0x76]	6990	1			T13	13		T47	1		T15	10
valid_sources[0x77]	6885	1			T21	3		T4	2		T12	2
valid_sources[0x78]	9618	1			T4	1		T13	12		T14	19
valid_sources[0x79]	6147	1			T12	2		T13	11		T14	13
valid_sources[0x7a]	7808	1			T1	1		T4	2		T13	10
valid_sources[0x7b]	13896	1			T4	1		T12	1		T26	16
valid_sources[0x7c]	7755	1			T4	1		T11	3		T12	1
valid_sources[0x7d]	7806	1			T1	2		T11	6		T13	10
valid_sources[0x7e]	11085	1			T11	3		T26	8		T13	10
valid_sources[0x7f]	8939	1			T13	14		T14	5		T27	2
valid_sources[0x80]	7025	1			T2	1		T11	2		T13	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1068188

1

T1

46

T2

1

T21

1

values[0x0]

all_enables

biggest_size

75300

1

T1

8

T2

3

T3

15

values[0x1]

all_enables

biggest_size

54290

1

T1

11

T2

1

T3

14