Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	25214	1			T13	18		T14	6		T15	8
auto[PWRUP]	92	1			T48	1		T52	1		T58	2
auto[ONEST_0]	54	1			T48	1		T58	2		T53	1
auto[ONEST_021]	13	1			T58	1		T59	2		T219	1
auto[ONEST_1]	71	1			T52	3		T58	2		T53	3
auto[ONEST_DONE]	5	1			T48	1		T220	1		T221	1
auto[LP_0]	95	1			T52	2		T53	1		T54	2
auto[LP_021]	26	1			T50	1		T51	1		T222	1
auto[LP_1]	100	1			T48	1		T52	2		T53	1
auto[LP_EVAL]	43	1			T48	1		T52	1		T53	1
auto[LP_SLP]	374	1			T48	3		T52	8		T58	6
auto[LP_PWRUP]	21	1			T53	1		T54	1		T50	1
auto[NP_0]	139	1			T19	1		T52	2		T58	3
auto[NP_021]	30	1			T54	2		T223	1		T59	1
auto[NP_1]	134	1			T48	2		T52	1		T58	2
auto[NP_EVAL]	14	1			T52	1		T223	1		T222	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

3

1

T224

1

T225

1

T226

1

min

24805

1

T13

18

T14

6

T15

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24812	1			T13	18		T14	6		T15	8
pow[0x1]	7	1			T227	1		T228	1		T229	1
pow[0x2]	12	1			T52	2		T53	1		T230	1
pow[0x3]	16	1			T50	1		T231	2		T232	1
pow[0x4]	55	1			T58	2		T54	1		T50	1
pow[0x5]	115	1			T48	2		T52	2		T58	3
pow[0x6]	194	1			T48	4		T52	3		T58	5
pow[0x7]	400	1			T48	9		T52	10		T58	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

134

1

T48

3

T52

1

T58

3

min

24462

1

T13

18

T14

6

T15

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24462	1			T13	18		T14	6		T15	8
pow[0x5]	1	1			T233	1		-	-		-	-
pow[0x7]	5	1			T222	1		T234	1		T229	1
pow[0x8]	2	1			T57	1		T235	1		-	-
pow[0x9]	7	1			T53	1		T236	1		T89	1
pow[0xa]	9	1			T223	1		T59	1		T222	1
pow[0xb]	26	1			T48	2		T52	2		T53	1
pow[0xc]	54	1			T48	1		T52	1		T58	1
pow[0xd]	117	1			T52	4		T58	3		T53	1
pow[0xe]	226	1			T48	3		T52	6		T58	3
pow[0xf]	458	1			T19	1		T48	5		T52	8