Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	1975	1			T21	10		T5	6		T23	10
auto[PWRUP]	89	1			T5	1		T48	1		T52	2
auto[ONEST_0]	78	1			T19	1		T40	1		T48	2
auto[ONEST_021]	12	1			T51	1		T375	1		T228	1
auto[ONEST_1]	86	1			T19	1		T48	1		T52	2
auto[ONEST_DONE]	6	1			T296	1		T228	1		T376	1
auto[LP_0]	115	1			T48	1		T52	1		T53	3
auto[LP_021]	24	1			T31	1		T50	1		T222	1
auto[LP_1]	112	1			T19	1		T48	1		T52	1
auto[LP_EVAL]	41	1			T40	1		T48	1		T58	1
auto[LP_SLP]	421	1			T5	1		T19	1		T41	1
auto[LP_PWRUP]	24	1			T48	1		T223	1		T51	1
auto[NP_0]	165	1			T5	1		T11	1		T19	5
auto[NP_021]	34	1			T12	1		T42	1		T223	1
auto[NP_1]	150	1			T11	1		T40	2		T41	3
auto[NP_EVAL]	19	1			T12	1		T30	1		T53	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T219

1

T227

1

T221

1

min

1625

1

T21

10

T5

8

T23

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1636	1			T21	10		T5	8		T23	10
pow[0x1]	9	1			T55	1		T222	1		T227	1
pow[0x2]	8	1			T58	1		T223	1		T232	1
pow[0x3]	26	1			T52	2		T55	1		T222	1
pow[0x4]	52	1			T48	1		T52	1		T58	1
pow[0x5]	108	1			T48	3		T52	1		T58	1
pow[0x6]	237	1			T19	1		T52	4		T58	3
pow[0x7]	431	1			T40	1		T48	3		T52	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

159

1

T48

1

T52

3

T58

1

min

1169

1

T21

10

T5

8

T23

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1171	1			T21	10		T5	8		T23	10
pow[0x1]	12	1			T43	2		T31	1		T377	1
pow[0x2]	16	1			T42	1		T30	1		T331	1
pow[0x3]	19	1			T11	1		T12	1		T19	1
pow[0x4]	19	1			T11	1		T19	2		T48	1
pow[0x6]	1	1			T228	1		-	-		-	-
pow[0x7]	2	1			T378	1		T327	1		-	-
pow[0x8]	4	1			T52	1		T232	1		T229	1
pow[0x9]	9	1			T52	1		T379	1		T376	1
pow[0xa]	12	1			T50	1		T51	1		T224	1
pow[0xb]	29	1			T48	2		T53	1		T54	1
pow[0xc]	51	1			T12	1		T48	1		T58	1
pow[0xd]	135	1			T48	1		T52	2		T58	2
pow[0xe]	227	1			T48	3		T52	1		T58	1
pow[0xf]	473	1			T48	4		T52	5		T58	6