Unified Coverage Report :: Module

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00



55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_subreg ( parameter DW=4,SwAccess=0,RESVAL=7,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_pwrup_time

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_lp_sample_ctl

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_wakeup_ctl_match_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_match_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_filter_status_match

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_match

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T21

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_en_ctl_adc_enable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_en_ctl_oneshot_mode

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_lp_mode

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_fsm_rst

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_wakeup_ctl_trans_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_trans_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_oneshot_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_filter_status_trans

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_trans

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_oneshot

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=155,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_sample_ctl

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T21,T5

Cond Coverage for Module : prim_subreg ( parameter DW=24,SwAccess=0,RESVAL=1600,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_wakeup_time

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
94.44	100.00

tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_ext_0

SCORE	COND
94.44	100.00

tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_ext_0

SCORE	COND
94.44	100.00

tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_ext_1

SCORE	COND
94.44	100.00

tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_ext_1

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	92.86			100.00

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_ext_0	94.44	83.33	100.00			100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_ext_0	94.44	83.33	100.00			100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_ext_1	94.44	83.33	100.00			100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_ext_1	94.44	83.33	100.00			100.00
tb.dut.u_reg.u_intr_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_en_ctl_adc_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_en_ctl_oneshot_mode	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_pd_ctl_lp_mode	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_pd_ctl_pwrup_time	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_pd_ctl_wakeup_time	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_lp_sample_ctl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_sample_ctl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_fsm_rst	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_wakeup_ctl_match_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_wakeup_ctl_trans_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_filter_status_match	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_filter_status_trans	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_ctl_match_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_ctl_trans_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_ctl_oneshot_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_status_match	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_status_trans	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_status_oneshot	100.00	100.00	100.00			100.00