Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	3012	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2964	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2825	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	3022	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2806	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2762	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2926	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2909	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2848	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2852	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	3063	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2849	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2771	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2897	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2982	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2851	0	0
adc_en_ctl_rd_A	2147483647	2232	0	0
adc_fsm_rst_rd_A	2147483647	2088	0	0
adc_intr_ctl_rd_A	2147483647	2937	0	0
adc_lp_sample_ctl_rd_A	2147483647	2143	0	0
adc_pd_ctl_rd_A	2147483647	2393	0	0
adc_sample_ctl_rd_A	2147483647	2138	0	0
adc_wakeup_ctl_rd_A	2147483647	2460	0	0
intr_enable_rd_A	2147483647	2859	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3012	0	0
T5	308670	14	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	10	0	0
T12	0	21	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	13	0	0
T31	0	20	0	0
T32	0	46	0	0
T33	0	25	0	0
T34	0	31	0	0
T35	0	13	0	0
T36	0	41	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2964	0	0
T5	308670	11	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	4	0	0
T12	0	13	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	30	0	0
T31	0	23	0	0
T32	0	40	0	0
T33	0	30	0	0
T34	0	6	0	0
T35	0	21	0	0
T36	0	30	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2825	0	0
T5	308670	15	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	6	0	0
T12	0	13	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	37	0	0
T31	0	20	0	0
T32	0	42	0	0
T33	0	14	0	0
T34	0	9	0	0
T35	0	12	0	0
T36	0	36	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3022	0	0
T5	308670	12	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	15	0	0
T12	0	25	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	36	0	0
T31	0	17	0	0
T32	0	26	0	0
T33	0	16	0	0
T34	0	17	0	0
T35	0	9	0	0
T36	0	38	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2806	0	0
T5	308670	13	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	1	0	0
T12	0	33	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	26	0	0
T31	0	19	0	0
T32	0	37	0	0
T33	0	7	0	0
T34	0	23	0	0
T35	0	15	0	0
T36	0	24	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2762	0	0
T5	308670	9	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	0	0	0
T12	0	19	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	20	0	0
T31	0	32	0	0
T32	0	38	0	0
T33	0	28	0	0
T34	0	30	0	0
T35	0	21	0	0
T36	0	30	0	0
T37	0	48	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2926	0	0
T5	308670	29	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	7	0	0
T12	0	25	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	36	0	0
T31	0	10	0	0
T32	0	29	0	0
T33	0	20	0	0
T34	0	24	0	0
T35	0	17	0	0
T36	0	31	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2909	0	0
T5	308670	24	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	4	0	0
T12	0	16	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	31	0	0
T31	0	34	0	0
T32	0	39	0	0
T33	0	11	0	0
T34	0	4	0	0
T35	0	15	0	0
T36	0	36	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2848	0	0
T5	308670	25	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	10	0	0
T12	0	22	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	28	0	0
T31	0	20	0	0
T32	0	28	0	0
T33	0	13	0	0
T34	0	15	0	0
T35	0	24	0	0
T36	0	34	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2852	0	0
T5	308670	14	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	11	0	0
T12	0	21	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	32	0	0
T31	0	22	0	0
T32	0	23	0	0
T33	0	24	0	0
T34	0	20	0	0
T35	0	12	0	0
T36	0	41	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3063	0	0
T5	308670	23	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	4	0	0
T12	0	17	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	30	0	0
T31	0	25	0	0
T32	0	33	0	0
T33	0	17	0	0
T34	0	26	0	0
T35	0	14	0	0
T36	0	41	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2849	0	0
T5	308670	28	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	7	0	0
T12	0	24	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	27	0	0
T31	0	21	0	0
T32	0	34	0	0
T33	0	17	0	0
T34	0	18	0	0
T35	0	22	0	0
T36	0	43	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2771	0	0
T5	308670	11	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	15	0	0
T12	0	15	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	20	0	0
T31	0	17	0	0
T32	0	28	0	0
T33	0	16	0	0
T34	0	14	0	0
T35	0	19	0	0
T36	0	37	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2897	0	0
T5	308670	24	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	5	0	0
T12	0	17	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	44	0	0
T31	0	24	0	0
T32	0	53	0	0
T33	0	14	0	0
T34	0	32	0	0
T35	0	27	0	0
T36	0	40	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2982	0	0
T5	308670	18	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	11	0	0
T12	0	19	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	40	0	0
T31	0	22	0	0
T32	0	41	0	0
T33	0	31	0	0
T34	0	16	0	0
T35	0	8	0	0
T36	0	35	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2851	0	0
T5	308670	11	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	11	0	0
T12	0	23	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	24	0	0
T31	0	9	0	0
T32	0	32	0	0
T33	0	27	0	0
T34	0	12	0	0
T35	0	20	0	0
T36	0	43	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2232	0	0
T5	308670	27	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	6	0	0
T12	0	21	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	32	0	0
T31	0	9	0	0
T32	0	34	0	0
T33	0	15	0	0
T34	0	28	0	0
T35	0	28	0	0
T36	0	46	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2088	0	0
T5	308670	17	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	7	0	0
T12	0	29	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	34	0	0
T31	0	26	0	0
T32	0	31	0	0
T33	0	19	0	0
T34	0	22	0	0
T35	0	12	0	0
T36	0	29	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2937	0	0
T5	308670	10	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	1	0	0
T12	0	22	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	37	0	0
T31	0	22	0	0
T32	0	42	0	0
T33	0	24	0	0
T34	0	27	0	0
T35	0	19	0	0
T36	0	29	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2143	0	0
T5	308670	10	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	16	0	0
T12	0	15	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	20	0	0
T31	0	22	0	0
T32	0	41	0	0
T33	0	20	0	0
T34	0	13	0	0
T35	0	15	0	0
T36	0	25	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2393	0	0
T5	308670	15	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	0	0	0
T12	0	19	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	27	0	0
T31	0	27	0	0
T32	0	54	0	0
T33	0	13	0	0
T34	0	21	0	0
T35	0	16	0	0
T36	0	26	0	0
T37	0	31	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2138	0	0
T5	308670	31	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	4	0	0
T12	0	20	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	33	0	0
T31	0	15	0	0
T32	0	40	0	0
T33	0	22	0	0
T34	0	21	0	0
T35	0	32	0	0
T36	0	39	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2460	0	0
T5	308670	18	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	8	0	0
T12	0	38	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	52	0	0
T31	0	11	0	0
T32	0	40	0	0
T33	0	32	0	0
T34	0	18	0	0
T35	0	17	0	0
T36	0	43	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2859	0	0
T5	308670	44	0	0
T6	327577	0	0	0
T7	144286	0	0	0
T8	355717	0	0	0
T9	235626	0	0	0
T10	372228	0	0	0
T11	112949	18	0	0
T12	0	18	0	0
T22	9439	0	0	0
T23	71080	0	0	0
T24	12738	0	0	0
T30	0	33	0	0
T31	0	29	0	0
T32	0	23	0	0
T33	0	19	0	0
T34	0	20	0	0
T38	0	14	0	0
T39	0	43	0	0