Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1193971	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1171027

1

T1

6

T2

1

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2082442	1			T1	1		T2	1		T21	1
values[0x0]	140849	1			T1	12		T2	1		T3	31
values[0x1]	141707	1			T1	5		T2	1		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	955713	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1409285

1

T1

7

T2

2

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15261	1			T5	2		T6	2		T13	1
valid_sources[0x01]	11156	1			T6	3		T9	2		T140	1
valid_sources[0x02]	7180	1			T4	5		T5	1		T6	1
valid_sources[0x03]	8066	1			T4	1		T5	2		T6	4
valid_sources[0x04]	7531	1			T3	1		T5	2		T6	3
valid_sources[0x05]	8544	1			T6	3		T9	1		T13	3
valid_sources[0x06]	11961	1			T4	4		T6	4		T9	3
valid_sources[0x07]	6864	1			T5	3		T6	4		T13	5
valid_sources[0x08]	6496	1			T4	3		T5	1		T6	4
valid_sources[0x09]	7717	1			T5	2		T6	1		T8	6
valid_sources[0x0a]	15205	1			T5	1		T6	5		T9	4
valid_sources[0x0b]	6889	1			T5	4		T6	7		T9	1
valid_sources[0x0c]	7038	1			T5	4		T6	8		T9	2
valid_sources[0x0d]	6901	1			T4	2		T5	3		T6	6
valid_sources[0x0e]	6883	1			T3	1		T5	1		T6	1
valid_sources[0x0f]	6745	1			T5	3		T6	3		T12	1
valid_sources[0x10]	6657	1			T6	5		T7	4		T12	1
valid_sources[0x11]	6646	1			T6	2		T9	1		T12	1
valid_sources[0x12]	7058	1			T5	4		T6	2		T9	3
valid_sources[0x13]	7418	1			T3	1		T5	2		T6	4
valid_sources[0x14]	11817	1			T3	2		T6	3		T8	2
valid_sources[0x15]	14256	1			T4	5		T6	1		T12	1
valid_sources[0x16]	7760	1			T5	3		T6	5		T9	3
valid_sources[0x17]	11260	1			T6	7		T9	1		T40	4
valid_sources[0x18]	13479	1			T6	3		T12	1		T140	1
valid_sources[0x19]	12194	1			T4	4		T6	1		T56	2
valid_sources[0x1a]	7887	1			T5	1		T6	1		T9	2
valid_sources[0x1b]	6895	1			T5	1		T9	1		T140	2
valid_sources[0x1c]	9010	1			T5	1		T6	6		T9	1
valid_sources[0x1d]	6892	1			T4	2		T6	3		T9	2
valid_sources[0x1e]	6821	1			T5	1		T6	6		T9	2
valid_sources[0x1f]	6404	1			T5	1		T6	5		T9	1
valid_sources[0x20]	6555	1			T5	2		T6	5		T9	2
valid_sources[0x21]	13627	1			T5	2		T6	5		T9	2
valid_sources[0x22]	6535	1			T6	4		T56	1		T140	1
valid_sources[0x23]	10945	1			T6	2		T9	2		T12	1
valid_sources[0x24]	6372	1			T4	2		T6	1		T7	2
valid_sources[0x25]	6603	1			T6	5		T11	1		T12	2
valid_sources[0x26]	7070	1			T3	1		T6	1		T40	4
valid_sources[0x27]	6447	1			T5	1		T9	2		T12	1
valid_sources[0x28]	6488	1			T5	3		T6	4		T140	1
valid_sources[0x29]	8245	1			T6	1		T11	1		T12	1
valid_sources[0x2a]	6518	1			T5	2		T6	2		T13	15
valid_sources[0x2b]	21719	1			T3	1		T6	2		T9	1
valid_sources[0x2c]	7075	1			T6	1		T12	2		T40	3
valid_sources[0x2d]	6534	1			T4	3		T5	1		T6	3
valid_sources[0x2e]	8505	1			T5	1		T6	1		T9	1
valid_sources[0x2f]	6635	1			T5	1		T8	8		T9	1
valid_sources[0x30]	7102	1			T5	1		T9	2		T12	1
valid_sources[0x31]	11089	1			T5	1		T6	4		T9	2
valid_sources[0x32]	6435	1			T5	1		T6	5		T9	1
valid_sources[0x33]	6752	1			T5	2		T6	7		T7	6
valid_sources[0x34]	6703	1			T6	6		T12	2		T22	1
valid_sources[0x35]	6500	1			T3	1		T5	3		T6	7
valid_sources[0x36]	6430	1			T3	1		T4	4		T5	1
valid_sources[0x37]	6599	1			T5	1		T6	6		T13	18
valid_sources[0x38]	14436	1			T5	2		T6	3		T9	3
valid_sources[0x39]	10431	1			T6	3		T9	2		T11	1
valid_sources[0x3a]	11207	1			T6	3		T9	1		T12	2
valid_sources[0x3b]	14892	1			T5	1		T6	3		T9	3
valid_sources[0x3c]	6708	1			T5	1		T6	4		T9	3
valid_sources[0x3d]	8780	1			T5	1		T6	4		T9	1
valid_sources[0x3e]	7356	1			T5	2		T6	1		T9	2
valid_sources[0x3f]	6465	1			T4	2		T6	1		T9	1
valid_sources[0x40]	6648	1			T5	2		T6	3		T9	1
valid_sources[0x41]	9638	1			T4	3		T6	2		T56	1
valid_sources[0x42]	11406	1			T5	4		T6	8		T8	6
valid_sources[0x43]	10770	1			T3	1		T4	2		T6	5
valid_sources[0x44]	6812	1			T6	2		T9	2		T13	16
valid_sources[0x45]	7847	1			T5	1		T6	2		T9	4
valid_sources[0x46]	7349	1			T5	1		T6	2		T7	1
valid_sources[0x47]	16827	1			T4	6		T6	3		T9	1
valid_sources[0x48]	15951	1			T5	1		T6	7		T11	1
valid_sources[0x49]	7647	1			T3	1		T5	1		T6	1
valid_sources[0x4a]	6754	1			T5	2		T6	4		T9	1
valid_sources[0x4b]	9009	1			T5	1		T6	4		T11	1
valid_sources[0x4c]	6402	1			T3	1		T4	1		T6	4
valid_sources[0x4d]	11058	1			T5	2		T6	4		T9	1
valid_sources[0x4e]	6333	1			T5	1		T6	3		T40	1
valid_sources[0x4f]	6539	1			T6	7		T9	1		T11	1
valid_sources[0x50]	6314	1			T4	5		T5	1		T6	4
valid_sources[0x51]	6507	1			T6	8		T9	2		T22	2
valid_sources[0x52]	6636	1			T4	1		T6	2		T9	1
valid_sources[0x53]	6630	1			T5	2		T6	5		T9	1
valid_sources[0x54]	10726	1			T3	1		T5	2		T6	3
valid_sources[0x55]	6762	1			T2	3		T5	4		T6	3
valid_sources[0x56]	7693	1			T5	1		T6	2		T9	2
valid_sources[0x57]	18378	1			T6	3		T9	2		T12	1
valid_sources[0x58]	10016	1			T5	5		T6	4		T11	1
valid_sources[0x59]	7029	1			T5	2		T6	7		T9	1
valid_sources[0x5a]	13942	1			T4	2		T6	5		T11	1
valid_sources[0x5b]	11317	1			T5	1		T6	5		T56	1
valid_sources[0x5c]	7535	1			T1	18		T5	1		T6	7
valid_sources[0x5d]	6509	1			T5	1		T6	8		T40	1
valid_sources[0x5e]	8187	1			T6	8		T9	1		T12	2
valid_sources[0x5f]	6706	1			T3	2		T6	1		T56	1
valid_sources[0x60]	11249	1			T6	2		T9	1		T40	1
valid_sources[0x61]	8258	1			T5	2		T6	3		T9	2
valid_sources[0x62]	6710	1			T5	1		T6	4		T7	10
valid_sources[0x63]	9505	1			T5	2		T6	1		T9	1
valid_sources[0x64]	7373	1			T4	5		T5	2		T6	9
valid_sources[0x65]	7568	1			T5	1		T6	5		T12	1
valid_sources[0x66]	10815	1			T4	1		T5	2		T6	3
valid_sources[0x67]	10879	1			T3	1		T5	2		T6	9
valid_sources[0x68]	6362	1			T5	1		T6	2		T9	1
valid_sources[0x69]	6895	1			T5	2		T6	3		T9	2
valid_sources[0x6a]	9635	1			T4	1		T5	1		T6	4
valid_sources[0x6b]	16325	1			T5	1		T6	7		T9	3
valid_sources[0x6c]	6669	1			T5	2		T6	2		T9	2
valid_sources[0x6d]	19908	1			T5	2		T12	1		T13	11
valid_sources[0x6e]	6672	1			T4	8		T5	2		T6	1
valid_sources[0x6f]	11692	1			T6	2		T9	1		T12	1
valid_sources[0x70]	7402	1			T6	5		T9	1		T56	1
valid_sources[0x71]	6910	1			T5	3		T6	5		T9	1
valid_sources[0x72]	9656	1			T5	3		T6	4		T8	2
valid_sources[0x73]	9321	1			T5	1		T6	1		T22	1
valid_sources[0x74]	9453	1			T5	2		T6	2		T9	1
valid_sources[0x75]	6737	1			T6	1		T9	2		T12	1
valid_sources[0x76]	6249	1			T5	3		T6	4		T9	1
valid_sources[0x77]	13311	1			T5	4		T6	3		T61	1
valid_sources[0x78]	11803	1			T3	1		T5	2		T6	5
valid_sources[0x79]	7863	1			T5	5		T6	9		T40	2
valid_sources[0x7a]	10495	1			T4	2		T5	7		T6	3
valid_sources[0x7b]	9425	1			T6	7		T9	1		T12	1
valid_sources[0x7c]	7045	1			T5	2		T6	1		T22	1
valid_sources[0x7d]	20613	1			T3	1		T5	1		T9	3
valid_sources[0x7e]	10878	1			T5	2		T6	7		T9	1
valid_sources[0x7f]	11018	1			T3	2		T5	2		T6	5
valid_sources[0x80]	6787	1			T5	2		T6	7		T9	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1037764

1

T1

1

T4

46

T5

122

values[0x0]

all_enables

biggest_size

77505

1

T1

4

T2

1

T3

21

values[0x1]

all_enables

biggest_size

55758

1

T1

1

T3

15

T21

2