Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26740	1			T6	5		T13	19		T14	9
auto[PWRUP]	96	1			T51	1		T54	1		T53	1
auto[ONEST_0]	57	1			T54	2		T53	2		T207	1
auto[ONEST_021]	16	1			T208	2		T209	1		T210	1
auto[ONEST_1]	66	1			T55	1		T52	1		T54	2
auto[ONEST_DONE]	6	1			T207	1		T211	1		T212	1
auto[LP_0]	117	1			T51	1		T52	1		T54	1
auto[LP_021]	25	1			T60	1		T58	2		T207	1
auto[LP_1]	102	1			T51	1		T55	1		T52	1
auto[LP_EVAL]	53	1			T51	2		T52	1		T207	1
auto[LP_SLP]	444	1			T51	2		T55	10		T52	6
auto[LP_PWRUP]	30	1			T51	1		T55	1		T58	2
auto[NP_0]	131	1			T51	4		T55	1		T52	1
auto[NP_021]	32	1			T54	1		T58	2		T207	1
auto[NP_1]	156	1			T51	3		T55	1		T54	3
auto[NP_EVAL]	27	1			T51	1		T55	1		T208	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T207

1

T213

1

T214

1

min

26245

1

T6

5

T13

19

T14

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26250	1			T6	5		T13	19		T14	9
pow[0x1]	3	1			T215	1		T216	1		T217	1
pow[0x2]	18	1			T55	1		T218	1		T219	1
pow[0x3]	30	1			T51	1		T54	1		T58	1
pow[0x4]	57	1			T55	1		T54	1		T60	1
pow[0x5]	131	1			T51	2		T55	2		T52	1
pow[0x6]	233	1			T51	2		T52	1		T54	7
pow[0x7]	462	1			T51	5		T55	2		T52	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

161

1

T51

2

T55

2

T52

1

min

25830

1

T6

5

T13

19

T14

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25830	1			T6	5		T13	19		T14	9
pow[0x5]	1	1			T220	1		-	-		-	-
pow[0x7]	4	1			T218	1		T221	1		T222	1
pow[0x8]	4	1			T52	1		T60	1		T223	1
pow[0x9]	7	1			T207	1		T215	1		T224	1
pow[0xa]	21	1			T55	1		T59	2		T221	1
pow[0xb]	28	1			T55	1		T225	1		T211	2
pow[0xc]	75	1			T51	1		T55	1		T54	3
pow[0xd]	132	1			T55	2		T53	1		T60	3
pow[0xe]	247	1			T51	4		T55	2		T52	3
pow[0xf]	535	1			T51	5		T55	3		T52	5