Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2066	1			T2	20		T5	6		T9	5
auto[PWRUP]	134	1			T9	1		T24	1		T25	1
auto[ONEST_0]	74	1			T40	1		T43	1		T55	1
auto[ONEST_021]	11	1			T60	1		T58	2		T90	1
auto[ONEST_1]	100	1			T5	1		T16	1		T51	2
auto[ONEST_DONE]	4	1			T210	1		T221	1		T90	1
auto[LP_0]	133	1			T24	1		T43	1		T51	2
auto[LP_021]	30	1			T51	2		T54	1		T53	2
auto[LP_1]	125	1			T9	1		T51	1		T55	3
auto[LP_EVAL]	34	1			T53	1		T58	1		T211	1
auto[LP_SLP]	485	1			T5	1		T9	2		T51	3
auto[LP_PWRUP]	36	1			T45	1		T53	1		T58	1
auto[NP_0]	170	1			T40	1		T51	1		T45	3
auto[NP_021]	45	1			T40	1		T43	1		T51	1
auto[NP_1]	178	1			T5	2		T24	2		T16	2
auto[NP_EVAL]	26	1			T55	1		T52	1		T375	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T53

1

T59

1

T376

1

min

1728

1

T2

20

T5

9

T9

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1742	1			T2	20		T5	9		T9	9
pow[0x1]	9	1			T5	1		T52	1		T213	1
pow[0x2]	12	1			T215	2		T377	2		T376	1
pow[0x3]	33	1			T207	2		T225	1		T218	1
pow[0x4]	49	1			T52	1		T60	1		T207	2
pow[0x5]	121	1			T51	1		T55	1		T52	3
pow[0x6]	248	1			T51	2		T55	1		T52	5
pow[0x7]	443	1			T51	11		T55	4		T52	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

197

1

T51

2

T55

1

T52

1

min

1213

1

T2

20

T5

8

T9

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1225	1			T2	20		T5	8		T9	9
pow[0x1]	9	1			T16	1		T44	2		T206	1
pow[0x2]	6	1			T16	1		T25	1		T237	1
pow[0x3]	28	1			T43	2		T45	1		T26	2
pow[0x4]	15	1			T5	2		T375	1		T237	1
pow[0x5]	2	1			T218	1		T224	1		-	-
pow[0x7]	1	1			T378	1		-	-		-	-
pow[0x8]	7	1			T172	1		T379	1		T380	1
pow[0x9]	9	1			T225	1		T59	1		T352	1
pow[0xa]	11	1			T53	1		T210	1		T379	1
pow[0xb]	26	1			T55	1		T207	1		T225	1
pow[0xc]	79	1			T51	2		T52	1		T53	1
pow[0xd]	127	1			T51	1		T55	2		T52	1
pow[0xe]	261	1			T51	1		T55	4		T52	1
pow[0xf]	587	1			T51	13		T55	5		T52	4