Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.37	100.00	89.49			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_adc_chn_val_0_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_adc_chn_val_1_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_filter_status_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_adc_fsm_state_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_adc_en_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.01	95.31	67.24			89.47	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.67	94.90	67.39			88.37	100.00
u_src_to_dst_req	60.00	100.00	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.01	95.31	67.24			89.47	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.67	94.90	67.39			88.37	100.00
u_src_to_dst_req	60.00	100.00	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.74	100.00	92.65			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.79	100.00	93.48			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.72	98.44	79.69			94.74	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	86.03	97.87	78.57			92.68	75.00
u_src_to_dst_req	93.75	100.00	75.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T2 T3 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T2 T3 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T2 T3 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T2 T3 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T2 T3 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T2 T3 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=4,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal=155,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_en_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_pd_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_sample_ctl_cdc

SCORE	COND
78.29	85.71

tb.dut.u_reg.u_adc_chn_val_0_cdc

SCORE	COND
78.29	85.71

tb.dut.u_reg.u_adc_chn_val_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_wakeup_ctl_cdc

SCORE	COND
96.43	85.71

tb.dut.u_reg.u_filter_status_cdc

SCORE	COND
96.43	85.71

tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T40
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T13,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T13,T24
1	1	Covered	T6,T13,T24

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T6,T13,T24
1	-	Covered	T6,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T13,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T13,T24
1	1	Covered	T6,T13,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	168261879	0	0
DstReqKnown_A	865247552	856951966	0	0
SrcAckBusyChk_A	2147483647	194538	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	168261879	0	0
T1	16710	0	0	0
T2	131586	0	0	0
T3	972360	33427	0	0
T4	1861380	58202	0	0
T5	7894244	55846	0	0
T6	21535392	14998	0	0
T7	1346424	7778	0	0
T8	3403440	17979	0	0
T9	6142464	10055	0	0
T10	16226980	12121	0	0
T11	8760884	54293	0	0
T12	11542560	69930	0	0
T13	0	3328	0	0
T14	0	2585	0	0
T15	0	5920	0	0
T16	0	27776	0	0
T17	0	8008	0	0
T18	0	841	0	0
T19	0	1111	0	0
T20	0	1159	0	0
T21	28588	0	0	0
T22	1652860	0	0	0
T23	9102260	0	0	0
T24	0	65874	0	0
T40	0	53634	0	0
T41	0	1110	0	0
T42	31396	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865247552	856951966	0	0
T1	1768	234	0	0
T2	42718	2314	0	0
T3	25740	23894	0	0
T4	29120	27742	0	0
T5	91416	78624	0	0
T6	914862	912314	0	0
T7	26468	25012	0	0
T8	29458	27534	0	0
T9	88686	79430	0	0
T21	2288	286	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	194538	0	0
T1	16710	0	0	0
T2	131586	0	0	0
T3	972360	39	0	0
T4	1861380	41	0	0
T5	7894244	68	0	0
T6	21535392	21	0	0
T7	1346424	41	0	0
T8	3403440	41	0	0
T9	6142464	42	0	0
T10	16226980	27	0	0
T11	8760884	33	0	0
T12	11542560	41	0	0
T13	0	36	0	0
T14	0	18	0	0
T15	0	18	0	0
T16	0	32	0	0
T17	0	18	0	0
T18	0	2	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	28588	0	0	0
T22	1652860	0	0	0
T23	9102260	0	0	0
T24	0	35	0	0
T40	0	32	0	0
T41	0	2	0	0
T42	31396	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	217230	214994	0	0
T2	1710618	1669798	0	0
T3	6320340	6318052	0	0
T4	12098970	12097176	0	0
T5	8923928	8878818	0	0
T6	23330008	23329774	0	0
T7	1458626	1456962	0	0
T8	3687060	3685760	0	0
T9	6654336	6633302	0	0
T21	185822	184366	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	7	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         unreachable    assign src_req = src_we_i | src_re_i;
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         unreachable        src_busy_q <= 1'b1;
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         0/1     ==>        src_busy_q <= 1'b0;
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        unreachable        src_q <= src_wd_i & BitMask;
124        unreachable        txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T3 T4 T5 
135        1/1                txn_bits_q <= '0;
           Tests:       T3 T4 T5 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        unreachable    assign unused_wd = ^src_wd_i;
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	71	3	2	66.67
IF	115	3	3	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==> (Unreachable)
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==> (Unreachable)
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	0	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	0	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	7	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         unreachable    assign src_req = src_we_i | src_re_i;
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         unreachable        src_busy_q <= 1'b1;
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         0/1     ==>        src_busy_q <= 1'b0;
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        unreachable        src_q <= src_wd_i & BitMask;
124        unreachable        txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T3 T4 T5 
135        1/1                txn_bits_q <= '0;
           Tests:       T3 T4 T5 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        unreachable    assign unused_wd = ^src_wd_i;
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	71	3	2	66.67
IF	115	3	3	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==> (Unreachable)
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==> (Unreachable)
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	0	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	0	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T13 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T13 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T13 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T13 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T13 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T13 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T13 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T13
1	1	Covered	T5,T6,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T13
1	0	Covered	T5,T6,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T13
1	1	Covered	T5,T6,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T13
0	0	1	Covered	T5,T6,T13
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T13
0	0	1	Covered	T5,T6,T13
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	60988770	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	67859	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	60988770	0	0
T5	343228	1665	0	0
T6	897308	53072	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	0	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	17276	0	0
T14	0	11273	0	0
T15	0	29235	0	0
T17	0	30738	0	0
T18	0	27575	0	0
T19	0	37675	0	0
T20	0	45839	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T41	0	48814	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67859	0	0
T5	343228	2	0	0
T6	897308	62	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	0	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	154	0	0
T14	0	86	0	0
T15	0	72	0	0
T17	0	76	0	0
T18	0	67	0	0
T19	0	211	0	0
T20	0	70	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T41	0	77	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T9 T40 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T9 T40 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T9 T40 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T9 T40 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T9 T40 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T3 T4 T5 
135        1/1                txn_bits_q <= '0;
           Tests:       T3 T4 T5 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        unreachable    assign unused_wd = ^src_wd_i;
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T40
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T40
1	1	Covered	T5,T9,T40

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T5,T9,T40

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T9,T40
1	1	Covered	T5,T9,T40

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T9,T40
0	0	1	Covered	T5,T9,T40
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T9,T40
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	103419	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	89	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	103419	0	0
T5	343228	727	0	0
T6	897308	0	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	367	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T16	0	1177	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2954	0	0
T25	0	266	0	0
T26	0	485	0	0
T40	0	2330	0	0
T43	0	2031	0	0
T44	0	1336	0	0
T45	0	1539	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	89	0	0
T5	343228	1	0	0
T6	897308	0	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T16	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T3 T4 T5 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T3 T4 T5 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T3 T4 T5 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T3 T4 T5 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T3 T4 T5 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T3 T4 T5 
135        1/1                txn_bits_q <= '0;
           Tests:       T3 T4 T5 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	29166760	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	32958	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	29166760	0	0
T3	243090	33427	0	0
T4	465345	58202	0	0
T5	343228	14390	0	0
T6	897308	2271	0	0
T7	56101	7778	0	0
T8	141810	17979	0	0
T9	255936	6727	0	0
T10	737590	12121	0	0
T11	398222	54293	0	0
T12	0	69930	0	0
T21	7147	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32958	0	0
T3	243090	39	0	0
T4	465345	41	0	0
T5	343228	20	0	0
T6	897308	3	0	0
T7	56101	41	0	0
T8	141810	41	0	0
T9	255936	26	0	0
T10	737590	27	0	0
T11	398222	33	0	0
T12	0	41	0	0
T21	7147	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T3 T4 T5 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T3 T4 T5 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T3 T4 T5 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T3 T4 T5 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T3 T4 T5 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T3 T4 T5 
135        1/1                txn_bits_q <= '0;
           Tests:       T3 T4 T5 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	13565934	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	16045	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13565934	0	0
T3	243090	16484	0	0
T4	465345	1633	0	0
T5	343228	8522	0	0
T6	897308	1398	0	0
T7	56101	3652	0	0
T8	141810	497	0	0
T9	255936	3542	0	0
T10	737590	5607	0	0
T11	398222	26165	0	0
T12	0	1436	0	0
T21	7147	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16045	0	0
T3	243090	19	0	0
T4	465345	1	0	0
T5	343228	13	0	0
T6	897308	2	0	0
T7	56101	20	0	0
T8	141810	1	0	0
T9	255936	14	0	0
T10	737590	13	0	0
T11	398222	16	0	0
T12	0	1	0	0
T21	7147	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T2 T21 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T2 T21 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T2 T21 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T2 T21 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T2 T21 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T2 T21 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T21 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T21
0	0	1	Covered	T1,T2,T21
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T21
0	0	1	Covered	T1,T2,T21
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	11154825	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	13098	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11154825	0	0
T1	8355	469	0	0
T2	65793	153	0	0
T3	243090	0	0	0
T4	465345	0	0	0
T5	343228	3731	0	0
T6	897308	644	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	478	0	0
T21	7147	262	0	0
T23	0	1998	0	0
T40	0	4577	0	0
T42	0	1259	0	0
T47	0	147	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13098	0	0
T1	8355	1	0	0
T2	65793	1	0	0
T3	243090	0	0	0
T4	465345	0	0	0
T5	343228	5	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	2	0	0
T21	7147	1	0	0
T23	0	1	0	0
T40	0	3	0	0
T42	0	1	0	0
T47	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T2 T21 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T2 T21 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T2 T21 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T2 T21 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T2 T21 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T2 T21 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T21 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T21
0	0	1	Covered	T1,T2,T21
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T21
0	0	1	Covered	T1,T2,T21
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	11197368	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	13082	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11197368	0	0
T1	8355	475	0	0
T2	65793	160	0	0
T3	243090	0	0	0
T4	465345	0	0	0
T5	343228	3741	0	0
T6	897308	647	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	482	0	0
T21	7147	272	0	0
T23	0	2001	0	0
T40	0	4597	0	0
T42	0	1267	0	0
T47	0	160	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13082	0	0
T1	8355	1	0	0
T2	65793	1	0	0
T3	243090	0	0	0
T4	465345	0	0	0
T5	343228	5	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	2	0	0
T21	7147	1	0	0
T23	0	1	0	0
T40	0	3	0	0
T42	0	1	0	0
T47	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1635807	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	2047	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1635807	0	0
T5	343228	2636	0	0
T6	897308	754	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	223	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	179	0	0
T14	0	159	0	0
T15	0	362	0	0
T16	0	1766	0	0
T17	0	486	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	5401	0	0
T40	0	3476	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2047	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1597715	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1981	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1597715	0	0
T5	343228	2630	0	0
T6	897308	743	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	221	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	167	0	0
T14	0	157	0	0
T15	0	354	0	0
T16	0	1762	0	0
T17	0	473	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3913	0	0
T40	0	3452	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1981	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1602822	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1974	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1602822	0	0
T5	343228	2624	0	0
T6	897308	741	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	219	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	189	0	0
T14	0	155	0	0
T15	0	351	0	0
T16	0	1758	0	0
T17	0	462	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3891	0	0
T40	0	3436	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1974	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1565702	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1959	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565702	0	0
T5	343228	2618	0	0
T6	897308	733	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	217	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	172	0	0
T14	0	153	0	0
T15	0	346	0	0
T16	0	1754	0	0
T17	0	445	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3869	0	0
T40	0	3418	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1959	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1568869	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1963	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1568869	0	0
T5	343228	2612	0	0
T6	897308	721	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	215	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	160	0	0
T14	0	151	0	0
T15	0	340	0	0
T16	0	1750	0	0
T17	0	428	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3858	0	0
T40	0	3400	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1963	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1557316	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1969	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1557316	0	0
T5	343228	2606	0	0
T6	897308	710	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	213	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	181	0	0
T14	0	149	0	0
T15	0	332	0	0
T16	0	1746	0	0
T17	0	416	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3851	0	0
T40	0	3387	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1969	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1576955	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1971	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1576955	0	0
T5	343228	2600	0	0
T6	897308	700	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	211	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	198	0	0
T14	0	147	0	0
T15	0	323	0	0
T16	0	1742	0	0
T17	0	411	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3831	0	0
T40	0	3366	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1971	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1512708	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1932	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1512708	0	0
T5	343228	2594	0	0
T6	897308	694	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	209	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	182	0	0
T14	0	145	0	0
T15	0	314	0	0
T16	0	1738	0	0
T17	0	405	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3812	0	0
T40	0	3352	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1932	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1673851	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	2085	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1673851	0	0
T5	343228	2588	0	0
T6	897308	691	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	207	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	176	0	0
T14	0	143	0	0
T15	0	307	0	0
T16	0	1734	0	0
T17	0	401	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	5265	0	0
T40	0	3338	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2085	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1523238	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1948	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523238	0	0
T5	343228	2582	0	0
T6	897308	686	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	205	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	165	0	0
T14	0	141	0	0
T15	0	295	0	0
T16	0	1730	0	0
T17	0	397	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3789	0	0
T40	0	3319	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1948	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1527363	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1946	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1527363	0	0
T5	343228	2576	0	0
T6	897308	684	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	203	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	182	0	0
T14	0	139	0	0
T15	0	290	0	0
T16	0	1726	0	0
T17	0	385	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3779	0	0
T40	0	3311	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1946	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1508541	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1934	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1508541	0	0
T5	343228	2570	0	0
T6	897308	680	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	201	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	199	0	0
T14	0	137	0	0
T15	0	281	0	0
T16	0	1722	0	0
T17	0	382	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3763	0	0
T40	0	3307	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1934	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1577945	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1983	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1577945	0	0
T5	343228	2564	0	0
T6	897308	678	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	199	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	183	0	0
T14	0	135	0	0
T15	0	271	0	0
T16	0	1718	0	0
T17	0	502	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3748	0	0
T40	0	3290	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1983	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1522037	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1949	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1522037	0	0
T5	343228	2558	0	0
T6	897308	671	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	197	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	164	0	0
T14	0	133	0	0
T15	0	263	0	0
T16	0	1714	0	0
T17	0	484	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3730	0	0
T40	0	3275	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1949	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1505224	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1943	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1505224	0	0
T5	343228	2552	0	0
T6	897308	668	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	195	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	190	0	0
T14	0	131	0	0
T15	0	376	0	0
T16	0	1710	0	0
T17	0	474	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3705	0	0
T40	0	3260	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1525092	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1964	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1525092	0	0
T5	343228	2546	0	0
T6	897308	658	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	193	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	171	0	0
T14	0	129	0	0
T15	0	372	0	0
T16	0	1706	0	0
T17	0	470	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	3693	0	0
T40	0	3247	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1964	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	2	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T5 T6 T9 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T5 T6 T9 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T5 T6 T9 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T5 T6 T9 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T5 T6 T9 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T5 T6 T9 
135        1/1                txn_bits_q <= '0;
           Tests:       T5 T6 T9 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1130181	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	1482	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1130181	0	0
T5	343228	2522	0	0
T6	897308	631	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	185	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T18	0	320	0	0
T20	0	429	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T25	0	1757	0	0
T43	0	2187	0	0
T48	0	584	0	0
T49	0	651	0	0
T50	0	617	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1482	0	0
T5	343228	3	0	0
T6	897308	1	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	1	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T25	0	1	0	0
T43	0	3	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T6 T13 T24 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T6 T13 T24 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T6 T13 T24 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T2 T3 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T2 T3 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T6 T13 T24 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T6 T13 T24 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T6 T13 T24 
135        1/1                txn_bits_q <= '0;
           Tests:       T6 T13 T24 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T2 T3 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T2 T3 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T13,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T13,T24
1	1	Covered	T6,T13,T24

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T6,T13,T24
1	-	Covered	T6,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T13,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T13,T24
1	1	Covered	T6,T13,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T13,T24
0	0	1	Covered	T6,T13,T24
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T13,T24
0	0	1	Covered	T6,T13,T24
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	15973437	0	0
DstReqKnown_A	33278752	32959691	0	0
SrcAckBusyChk_A	2147483647	18377	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15973437	0	0
T6	897308	1515	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	0	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	470	0	0
T14	0	281	0	0
T15	0	743	0	0
T17	0	987	0	0
T18	0	841	0	0
T19	0	1111	0	0
T20	0	1159	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	1976	0	0
T41	0	1110	0	0
T42	31396	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33278752	32959691	0	0
T1	68	9	0	0
T2	1643	89	0	0
T3	990	919	0	0
T4	1120	1067	0	0
T5	3516	3024	0	0
T6	35187	35089	0	0
T7	1018	962	0	0
T8	1133	1059	0	0
T9	3411	3055	0	0
T21	88	11	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18377	0	0
T6	897308	2	0	0
T7	56101	0	0	0
T8	141810	0	0	0
T9	255936	0	0	0
T10	737590	0	0	0
T11	398222	0	0	0
T12	577128	0	0	0
T13	0	4	0	0
T14	0	2	0	0
T15	0	2	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	6	0	0
T20	0	2	0	0
T22	82643	0	0	0
T23	455113	0	0	0
T24	0	1	0	0
T41	0	2	0	0
T42	31396	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8355	8269	0	0
T2	65793	64223	0	0
T3	243090	243002	0	0
T4	465345	465276	0	0
T5	343228	341493	0	0
T6	897308	897299	0	0
T7	56101	56037	0	0
T8	141810	141760	0	0
T9	255936	255127	0	0
T21	7147	7091	0	0