Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1823	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1691	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1857	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1763	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1805	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1806	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1806	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1786	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1885	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1950	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1668	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1814	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1889	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2061	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1932	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1802	0	0
adc_en_ctl_rd_A	2147483647	1558	0	0
adc_fsm_rst_rd_A	2147483647	1280	0	0
adc_intr_ctl_rd_A	2147483647	1856	0	0
adc_lp_sample_ctl_rd_A	2147483647	1396	0	0
adc_pd_ctl_rd_A	2147483647	1769	0	0
adc_sample_ctl_rd_A	2147483647	1395	0	0
adc_wakeup_ctl_rd_A	2147483647	1521	0	0
intr_enable_rd_A	2147483647	1955	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1823	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	34	0	0
T25	0	19	0	0
T26	0	6	0	0
T27	0	28	0	0
T28	0	26	0	0
T29	0	22	0	0
T30	0	30	0	0
T31	0	20	0	0
T32	0	14	0	0
T33	0	16	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	21	0	0
T25	0	19	0	0
T26	0	3	0	0
T27	0	26	0	0
T28	0	33	0	0
T29	0	15	0	0
T30	0	19	0	0
T31	0	16	0	0
T32	0	23	0	0
T33	0	22	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1857	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	25	0	0
T25	0	32	0	0
T26	0	1	0	0
T27	0	35	0	0
T28	0	32	0	0
T29	0	17	0	0
T30	0	20	0	0
T31	0	12	0	0
T32	0	18	0	0
T33	0	13	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1763	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	30	0	0
T25	0	7	0	0
T26	0	6	0	0
T27	0	36	0	0
T28	0	22	0	0
T29	0	13	0	0
T30	0	29	0	0
T31	0	20	0	0
T32	0	25	0	0
T33	0	14	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1805	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	13	0	0
T25	0	23	0	0
T26	0	4	0	0
T27	0	31	0	0
T28	0	13	0	0
T29	0	25	0	0
T30	0	24	0	0
T31	0	12	0	0
T32	0	21	0	0
T33	0	20	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1806	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	34	0	0
T25	0	5	0	0
T26	0	7	0	0
T27	0	37	0	0
T28	0	16	0	0
T29	0	22	0	0
T30	0	32	0	0
T31	0	16	0	0
T32	0	7	0	0
T33	0	24	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1806	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	21	0	0
T25	0	21	0	0
T26	0	11	0	0
T27	0	40	0	0
T28	0	16	0	0
T29	0	18	0	0
T30	0	24	0	0
T31	0	17	0	0
T32	0	26	0	0
T33	0	26	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1786	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	22	0	0
T25	0	15	0	0
T26	0	17	0	0
T27	0	45	0	0
T28	0	16	0	0
T29	0	26	0	0
T30	0	24	0	0
T31	0	21	0	0
T32	0	12	0	0
T33	0	15	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1885	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	10	0	0
T25	0	18	0	0
T26	0	9	0	0
T27	0	53	0	0
T28	0	12	0	0
T29	0	22	0	0
T30	0	23	0	0
T31	0	18	0	0
T32	0	18	0	0
T33	0	9	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1950	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	4	0	0
T25	0	16	0	0
T26	0	14	0	0
T27	0	35	0	0
T28	0	13	0	0
T29	0	13	0	0
T30	0	7	0	0
T31	0	15	0	0
T32	0	26	0	0
T33	0	23	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1668	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	28	0	0
T25	0	12	0	0
T27	0	52	0	0
T28	0	20	0	0
T29	0	22	0	0
T30	0	15	0	0
T31	0	20	0	0
T32	0	15	0	0
T33	0	22	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0
T39	0	3	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1814	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	27	0	0
T25	0	16	0	0
T26	0	3	0	0
T27	0	39	0	0
T28	0	15	0	0
T29	0	25	0	0
T30	0	16	0	0
T31	0	22	0	0
T32	0	23	0	0
T33	0	24	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1889	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	27	0	0
T25	0	22	0	0
T26	0	3	0	0
T27	0	30	0	0
T28	0	47	0	0
T29	0	23	0	0
T30	0	29	0	0
T31	0	15	0	0
T32	0	16	0	0
T33	0	14	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	26	0	0
T25	0	27	0	0
T26	0	1	0	0
T27	0	23	0	0
T28	0	18	0	0
T29	0	25	0	0
T30	0	20	0	0
T31	0	21	0	0
T32	0	20	0	0
T33	0	20	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1932	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	25	0	0
T25	0	18	0	0
T26	0	15	0	0
T27	0	32	0	0
T28	0	15	0	0
T29	0	12	0	0
T30	0	15	0	0
T31	0	19	0	0
T32	0	20	0	0
T33	0	5	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1802	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	10	0	0
T25	0	23	0	0
T26	0	12	0	0
T27	0	36	0	0
T28	0	28	0	0
T29	0	15	0	0
T30	0	14	0	0
T31	0	11	0	0
T32	0	14	0	0
T33	0	18	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1558	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	29	0	0
T25	0	11	0	0
T26	0	9	0	0
T27	0	32	0	0
T28	0	18	0	0
T29	0	17	0	0
T30	0	11	0	0
T31	0	21	0	0
T32	0	6	0	0
T33	0	21	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1280	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	15	0	0
T25	0	32	0	0
T26	0	12	0	0
T27	0	28	0	0
T28	0	27	0	0
T29	0	17	0	0
T30	0	7	0	0
T31	0	15	0	0
T32	0	13	0	0
T33	0	32	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1856	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	37	0	0
T25	0	19	0	0
T26	0	6	0	0
T27	0	31	0	0
T28	0	17	0	0
T29	0	30	0	0
T30	0	16	0	0
T31	0	22	0	0
T32	0	12	0	0
T33	0	9	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1396	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	7	0	0
T25	0	22	0	0
T26	0	2	0	0
T27	0	28	0	0
T28	0	15	0	0
T29	0	13	0	0
T30	0	15	0	0
T31	0	30	0	0
T32	0	15	0	0
T33	0	32	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1769	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	22	0	0
T25	0	14	0	0
T26	0	16	0	0
T27	0	34	0	0
T28	0	16	0	0
T29	0	21	0	0
T30	0	23	0	0
T31	0	19	0	0
T32	0	30	0	0
T33	0	33	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1395	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	24	0	0
T25	0	23	0	0
T26	0	4	0	0
T27	0	25	0	0
T28	0	15	0	0
T29	0	15	0	0
T30	0	24	0	0
T31	0	13	0	0
T32	0	23	0	0
T33	0	16	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1521	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	19	0	0
T25	0	18	0	0
T27	0	47	0	0
T28	0	29	0	0
T29	0	22	0	0
T30	0	12	0	0
T31	0	10	0	0
T32	0	22	0	0
T33	0	22	0	0
T34	230445	0	0	0
T35	558249	0	0	0
T36	36923	0	0	0
T37	40509	0	0	0
T38	804870	0	0	0
T39	0	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1955	0	0
T14	132352	0	0	0
T15	421452	0	0	0
T16	245341	0	0	0
T17	417876	0	0	0
T24	329531	37	0	0
T25	0	21	0	0
T26	0	33	0	0
T27	0	47	0	0
T28	0	31	0	0
T29	0	22	0	0
T30	0	65	0	0
T31	0	13	0	0
T32	0	46	0	0
T33	0	19	0	0
T34	230445	0	0	0
T35	558249	0	0	0
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