Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.14


Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T797 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1754338856 Sep 09 06:19:54 AM UTC 24 Sep 09 06:48:53 AM UTC 24 596466428071 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2908945457 Sep 09 06:22:20 AM UTC 24 Sep 09 06:49:14 AM UTC 24 590695187863 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.1263564482 Sep 09 06:23:37 AM UTC 24 Sep 09 06:49:52 AM UTC 24 549970852615 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.2149137660 Sep 09 06:24:50 AM UTC 24 Sep 09 06:50:41 AM UTC 24 502149467268 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.2852703317 Sep 09 06:24:20 AM UTC 24 Sep 09 07:12:05 AM UTC 24 718488531452 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1102746653 Sep 09 05:07:19 AM UTC 24 Sep 09 05:07:24 AM UTC 24 575087860 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.3256097004 Sep 09 05:07:26 AM UTC 24 Sep 09 05:07:29 AM UTC 24 513702735 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1604949847 Sep 09 05:07:28 AM UTC 24 Sep 09 05:07:32 AM UTC 24 1208599384 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1699255480 Sep 09 05:07:30 AM UTC 24 Sep 09 05:07:33 AM UTC 24 531169476 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1801321086 Sep 09 05:07:25 AM UTC 24 Sep 09 05:07:35 AM UTC 24 4668494306 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.462948686 Sep 09 05:07:36 AM UTC 24 Sep 09 05:07:39 AM UTC 24 663943639 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1823144513 Sep 09 05:07:34 AM UTC 24 Sep 09 05:07:41 AM UTC 24 820536159 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3327773655 Sep 09 05:07:42 AM UTC 24 Sep 09 05:07:44 AM UTC 24 554740126 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3386027842 Sep 09 05:07:40 AM UTC 24 Sep 09 05:07:45 AM UTC 24 501510067 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3832281137 Sep 09 05:07:42 AM UTC 24 Sep 09 05:07:45 AM UTC 24 603762077 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4251424803 Sep 09 05:07:41 AM UTC 24 Sep 09 05:07:48 AM UTC 24 4786882949 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.974245772 Sep 09 05:07:45 AM UTC 24 Sep 09 05:07:49 AM UTC 24 426054180 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3132495426 Sep 09 05:07:47 AM UTC 24 Sep 09 05:07:52 AM UTC 24 511917961 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4220244099 Sep 09 05:07:46 AM UTC 24 Sep 09 05:07:52 AM UTC 24 2429981244 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2461632022 Sep 09 05:07:46 AM UTC 24 Sep 09 05:07:53 AM UTC 24 1179459343 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2281148887 Sep 09 05:07:48 AM UTC 24 Sep 09 05:07:54 AM UTC 24 372697285 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2354732941 Sep 09 05:07:53 AM UTC 24 Sep 09 05:07:56 AM UTC 24 416771078 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1006360065 Sep 09 05:07:52 AM UTC 24 Sep 09 05:07:56 AM UTC 24 360501115 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.849544023 Sep 09 05:07:35 AM UTC 24 Sep 09 05:07:56 AM UTC 24 4389415304 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2069317842 Sep 09 05:07:53 AM UTC 24 Sep 09 05:07:57 AM UTC 24 709535069 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1587517377 Sep 09 05:07:57 AM UTC 24 Sep 09 05:08:00 AM UTC 24 464406367 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4140224719 Sep 09 05:07:57 AM UTC 24 Sep 09 05:08:01 AM UTC 24 497538475 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.4004061135 Sep 09 05:08:00 AM UTC 24 Sep 09 05:08:03 AM UTC 24 305784702 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2414552580 Sep 09 05:07:55 AM UTC 24 Sep 09 05:08:05 AM UTC 24 1220679230 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2705408863 Sep 09 05:08:02 AM UTC 24 Sep 09 05:08:06 AM UTC 24 342092352 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1903928705 Sep 09 05:08:00 AM UTC 24 Sep 09 05:08:06 AM UTC 24 752182485 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1732600530 Sep 09 05:07:58 AM UTC 24 Sep 09 05:08:06 AM UTC 24 4246264777 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2065496135 Sep 09 05:08:06 AM UTC 24 Sep 09 05:08:09 AM UTC 24 519103542 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.27877984 Sep 09 05:08:07 AM UTC 24 Sep 09 05:08:11 AM UTC 24 505214864 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2140982547 Sep 09 05:07:32 AM UTC 24 Sep 09 05:08:12 AM UTC 24 28816797422 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1640873681 Sep 09 05:08:10 AM UTC 24 Sep 09 05:08:13 AM UTC 24 382719016 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.265950086 Sep 09 05:08:05 AM UTC 24 Sep 09 05:08:13 AM UTC 24 971777024 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1229087836 Sep 09 05:07:57 AM UTC 24 Sep 09 05:08:16 AM UTC 24 2431274215 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1474044736 Sep 09 05:08:14 AM UTC 24 Sep 09 05:08:17 AM UTC 24 329195922 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.159808330 Sep 09 05:07:50 AM UTC 24 Sep 09 05:08:18 AM UTC 24 5001639836 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1534246538 Sep 09 05:08:11 AM UTC 24 Sep 09 05:08:20 AM UTC 24 1266333901 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4264663880 Sep 09 05:08:14 AM UTC 24 Sep 09 05:08:21 AM UTC 24 1089916397 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2968755207 Sep 09 05:08:18 AM UTC 24 Sep 09 05:08:22 AM UTC 24 366734031 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1946568186 Sep 09 05:08:10 AM UTC 24 Sep 09 05:08:23 AM UTC 24 8013820640 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4229458427 Sep 09 05:08:19 AM UTC 24 Sep 09 05:08:23 AM UTC 24 1028371022 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2451679320 Sep 09 05:08:21 AM UTC 24 Sep 09 05:08:24 AM UTC 24 373816817 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2932577989 Sep 09 05:08:21 AM UTC 24 Sep 09 05:08:25 AM UTC 24 482362857 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3217094232 Sep 09 05:08:24 AM UTC 24 Sep 09 05:08:28 AM UTC 24 323751906 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3719257077 Sep 09 05:08:24 AM UTC 24 Sep 09 05:08:28 AM UTC 24 626402349 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1596898116 Sep 09 05:08:19 AM UTC 24 Sep 09 05:08:29 AM UTC 24 8531433919 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.954193779 Sep 09 05:08:06 AM UTC 24 Sep 09 05:08:30 AM UTC 24 4595771735 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.1884151193 Sep 09 05:08:26 AM UTC 24 Sep 09 05:08:30 AM UTC 24 432318537 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1425612840 Sep 09 05:08:14 AM UTC 24 Sep 09 05:08:31 AM UTC 24 27078055628 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3788711610 Sep 09 05:07:55 AM UTC 24 Sep 09 05:08:32 AM UTC 24 26271447980 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1259812170 Sep 09 05:08:17 AM UTC 24 Sep 09 05:08:33 AM UTC 24 1958644163 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2805396243 Sep 09 05:08:28 AM UTC 24 Sep 09 05:08:33 AM UTC 24 508772149 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1125838261 Sep 09 05:08:31 AM UTC 24 Sep 09 05:08:35 AM UTC 24 511982838 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.38542544 Sep 09 05:08:23 AM UTC 24 Sep 09 05:08:35 AM UTC 24 2365127130 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3116659324 Sep 09 05:08:24 AM UTC 24 Sep 09 05:08:35 AM UTC 24 8834518380 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3257448306 Sep 09 05:08:31 AM UTC 24 Sep 09 05:08:35 AM UTC 24 386845496 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1914466384 Sep 09 05:08:32 AM UTC 24 Sep 09 05:08:35 AM UTC 24 520419822 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2354778127 Sep 09 05:08:33 AM UTC 24 Sep 09 05:08:35 AM UTC 24 337764593 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.219358762 Sep 09 05:08:34 AM UTC 24 Sep 09 05:08:37 AM UTC 24 485034676 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3402768031 Sep 09 05:08:36 AM UTC 24 Sep 09 05:08:39 AM UTC 24 502273257 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.933926375 Sep 09 05:08:31 AM UTC 24 Sep 09 05:08:40 AM UTC 24 9155944545 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3214928198 Sep 09 05:08:35 AM UTC 24 Sep 09 05:08:40 AM UTC 24 822983977 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2068045925 Sep 09 05:08:36 AM UTC 24 Sep 09 05:08:41 AM UTC 24 494734654 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.816583068 Sep 09 05:08:36 AM UTC 24 Sep 09 05:08:41 AM UTC 24 514849387 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.215880408 Sep 09 05:08:37 AM UTC 24 Sep 09 05:08:41 AM UTC 24 708014216 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2665194440 Sep 09 05:08:34 AM UTC 24 Sep 09 05:08:42 AM UTC 24 4157212118 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3196885514 Sep 09 05:08:41 AM UTC 24 Sep 09 05:08:43 AM UTC 24 387332694 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2528499672 Sep 09 05:07:46 AM UTC 24 Sep 09 05:08:44 AM UTC 24 52725263086 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2193823364 Sep 09 05:08:40 AM UTC 24 Sep 09 05:08:44 AM UTC 24 438962733 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1596287510 Sep 09 05:08:42 AM UTC 24 Sep 09 05:08:45 AM UTC 24 597172832 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4019016216 Sep 09 05:08:36 AM UTC 24 Sep 09 05:08:45 AM UTC 24 4909920997 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3859328636 Sep 09 05:08:42 AM UTC 24 Sep 09 05:08:45 AM UTC 24 507722467 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3598973287 Sep 09 05:08:29 AM UTC 24 Sep 09 05:08:46 AM UTC 24 3014834645 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3160235682 Sep 09 05:08:44 AM UTC 24 Sep 09 05:08:48 AM UTC 24 410326261 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2393805861 Sep 09 05:08:39 AM UTC 24 Sep 09 05:08:48 AM UTC 24 8696466026 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4255122782 Sep 09 05:08:45 AM UTC 24 Sep 09 05:08:48 AM UTC 24 554950841 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.310896835 Sep 09 05:08:45 AM UTC 24 Sep 09 05:08:49 AM UTC 24 408852120 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.101632441 Sep 09 05:08:47 AM UTC 24 Sep 09 05:08:50 AM UTC 24 586430767 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1873640479 Sep 09 05:08:36 AM UTC 24 Sep 09 05:08:50 AM UTC 24 4887432533 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2804294115 Sep 09 05:08:47 AM UTC 24 Sep 09 05:08:51 AM UTC 24 426740502 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3260132836 Sep 09 05:08:43 AM UTC 24 Sep 09 05:08:53 AM UTC 24 8980337859 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1154091074 Sep 09 05:08:48 AM UTC 24 Sep 09 05:08:51 AM UTC 24 354025960 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.895938342 Sep 09 05:08:48 AM UTC 24 Sep 09 05:08:53 AM UTC 24 522758328 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.78120166 Sep 09 05:08:46 AM UTC 24 Sep 09 05:08:53 AM UTC 24 578871161 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3363442398 Sep 09 05:08:51 AM UTC 24 Sep 09 05:08:54 AM UTC 24 509257485 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.1185557374 Sep 09 05:08:51 AM UTC 24 Sep 09 05:08:55 AM UTC 24 450457867 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2154520837 Sep 09 05:08:42 AM UTC 24 Sep 09 05:08:56 AM UTC 24 2426647615 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2573294341 Sep 09 05:08:50 AM UTC 24 Sep 09 05:08:56 AM UTC 24 9642297420 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.53202744 Sep 09 05:08:53 AM UTC 24 Sep 09 05:08:56 AM UTC 24 677088921 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3748752713 Sep 09 05:08:52 AM UTC 24 Sep 09 05:08:56 AM UTC 24 385760862 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1246136180 Sep 09 05:08:54 AM UTC 24 Sep 09 05:08:57 AM UTC 24 491735718 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2368128340 Sep 09 05:08:54 AM UTC 24 Sep 09 05:08:59 AM UTC 24 479112931 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.810576904 Sep 09 05:08:57 AM UTC 24 Sep 09 05:09:00 AM UTC 24 319034029 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1172052299 Sep 09 05:08:46 AM UTC 24 Sep 09 05:09:00 AM UTC 24 3979862217 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3328767629 Sep 09 05:08:56 AM UTC 24 Sep 09 05:09:01 AM UTC 24 511776122 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2754253359 Sep 09 05:08:57 AM UTC 24 Sep 09 05:09:02 AM UTC 24 380921105 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1033242823 Sep 09 05:08:56 AM UTC 24 Sep 09 05:09:02 AM UTC 24 495202076 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3318803251 Sep 09 05:08:58 AM UTC 24 Sep 09 05:09:03 AM UTC 24 2577265548 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1153018188 Sep 09 05:08:59 AM UTC 24 Sep 09 05:09:04 AM UTC 24 423416525 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.827559821 Sep 09 05:09:02 AM UTC 24 Sep 09 05:09:04 AM UTC 24 331709804 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1484556191 Sep 09 05:08:57 AM UTC 24 Sep 09 05:09:05 AM UTC 24 4350786964 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2203065594 Sep 09 05:09:01 AM UTC 24 Sep 09 05:09:07 AM UTC 24 521082596 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3235071916 Sep 09 05:09:03 AM UTC 24 Sep 09 05:09:07 AM UTC 24 337011663 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.855202740 Sep 09 05:09:04 AM UTC 24 Sep 09 05:09:08 AM UTC 24 308659568 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2367965024 Sep 09 05:09:06 AM UTC 24 Sep 09 05:09:08 AM UTC 24 553340434 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3468990399 Sep 09 05:09:06 AM UTC 24 Sep 09 05:09:08 AM UTC 24 464704242 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.463870911 Sep 09 05:08:52 AM UTC 24 Sep 09 05:09:09 AM UTC 24 2319811965 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1242173317 Sep 09 05:08:03 AM UTC 24 Sep 09 05:09:09 AM UTC 24 46003970566 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2170755938 Sep 09 05:09:05 AM UTC 24 Sep 09 05:09:10 AM UTC 24 766651647 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.415123989 Sep 09 05:08:45 AM UTC 24 Sep 09 05:09:11 AM UTC 24 4485374428 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1396650821 Sep 09 05:08:55 AM UTC 24 Sep 09 05:09:12 AM UTC 24 2091398210 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1518282573 Sep 09 05:09:09 AM UTC 24 Sep 09 05:09:12 AM UTC 24 524594463 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2527765591 Sep 09 05:09:09 AM UTC 24 Sep 09 05:09:12 AM UTC 24 413442425 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1281718420 Sep 09 05:09:08 AM UTC 24 Sep 09 05:09:12 AM UTC 24 418202154 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3848907638 Sep 09 05:09:10 AM UTC 24 Sep 09 05:09:13 AM UTC 24 523242128 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3896861255 Sep 09 05:09:10 AM UTC 24 Sep 09 05:09:14 AM UTC 24 1792839015 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3274843182 Sep 09 05:09:03 AM UTC 24 Sep 09 05:09:14 AM UTC 24 3862914918 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3876214312 Sep 09 05:09:09 AM UTC 24 Sep 09 05:09:15 AM UTC 24 380334449 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.4206269040 Sep 09 05:09:13 AM UTC 24 Sep 09 05:09:15 AM UTC 24 533355828 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.528448232 Sep 09 05:09:13 AM UTC 24 Sep 09 05:09:18 AM UTC 24 354560449 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3848981715 Sep 09 05:09:15 AM UTC 24 Sep 09 05:09:18 AM UTC 24 799226784 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4276386440 Sep 09 05:09:16 AM UTC 24 Sep 09 05:09:19 AM UTC 24 468811150 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.820810860 Sep 09 05:08:54 AM UTC 24 Sep 09 05:09:19 AM UTC 24 8504214516 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.765736868 Sep 09 05:09:14 AM UTC 24 Sep 09 05:09:19 AM UTC 24 550789492 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.717809479 Sep 09 05:09:16 AM UTC 24 Sep 09 05:09:19 AM UTC 24 410141445 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1003749286 Sep 09 05:09:15 AM UTC 24 Sep 09 05:09:20 AM UTC 24 557315167 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.3239641767 Sep 09 05:09:19 AM UTC 24 Sep 09 05:09:21 AM UTC 24 381386348 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.648373443 Sep 09 05:09:14 AM UTC 24 Sep 09 05:09:22 AM UTC 24 4685926560 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2978285262 Sep 09 05:08:48 AM UTC 24 Sep 09 05:09:22 AM UTC 24 5056094400 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.986474552 Sep 09 05:09:20 AM UTC 24 Sep 09 05:09:23 AM UTC 24 386440653 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2622851141 Sep 09 05:09:20 AM UTC 24 Sep 09 05:09:23 AM UTC 24 327669273 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3994556232 Sep 09 05:09:20 AM UTC 24 Sep 09 05:09:23 AM UTC 24 354115053 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.912205600 Sep 09 05:09:20 AM UTC 24 Sep 09 05:09:23 AM UTC 24 509161084 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1653607693 Sep 09 05:09:19 AM UTC 24 Sep 09 05:09:23 AM UTC 24 345327726 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3866567406 Sep 09 05:09:13 AM UTC 24 Sep 09 05:09:24 AM UTC 24 4344269688 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2712740200 Sep 09 05:09:09 AM UTC 24 Sep 09 05:09:24 AM UTC 24 8887384327 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3676604618 Sep 09 05:09:22 AM UTC 24 Sep 09 05:09:24 AM UTC 24 522710804 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.1721684616 Sep 09 05:09:23 AM UTC 24 Sep 09 05:09:25 AM UTC 24 306101330 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2636444508 Sep 09 05:09:24 AM UTC 24 Sep 09 05:09:26 AM UTC 24 569642229 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3999076318 Sep 09 05:09:24 AM UTC 24 Sep 09 05:09:26 AM UTC 24 385299064 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3796543961 Sep 09 05:09:24 AM UTC 24 Sep 09 05:09:27 AM UTC 24 547394110 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.1948566201 Sep 09 05:09:23 AM UTC 24 Sep 09 05:09:27 AM UTC 24 485361451 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2493484681 Sep 09 05:09:01 AM UTC 24 Sep 09 05:09:27 AM UTC 24 4464695034 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.935069552 Sep 09 05:09:24 AM UTC 24 Sep 09 05:09:27 AM UTC 24 303718470 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.4137258007 Sep 09 05:09:24 AM UTC 24 Sep 09 05:09:27 AM UTC 24 472209838 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.3801905180 Sep 09 05:09:25 AM UTC 24 Sep 09 05:09:27 AM UTC 24 414809227 ps
T901 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.4221867094 Sep 09 05:09:25 AM UTC 24 Sep 09 05:09:28 AM UTC 24 469085992 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.1672247079 Sep 09 05:09:24 AM UTC 24 Sep 09 05:09:28 AM UTC 24 490058308 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.3449851793 Sep 09 05:09:25 AM UTC 24 Sep 09 05:09:28 AM UTC 24 515063638 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.1384653840 Sep 09 05:09:26 AM UTC 24 Sep 09 05:09:28 AM UTC 24 307857245 ps
T905 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2781969203 Sep 09 05:09:25 AM UTC 24 Sep 09 05:09:29 AM UTC 24 433910736 ps
T906 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.630293519 Sep 09 05:09:26 AM UTC 24 Sep 09 05:09:30 AM UTC 24 484994901 ps
T907 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.4110492617 Sep 09 05:09:26 AM UTC 24 Sep 09 05:09:30 AM UTC 24 441616249 ps
T908 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.689796713 Sep 09 05:09:28 AM UTC 24 Sep 09 05:09:30 AM UTC 24 377154019 ps
T909 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.1028231745 Sep 09 05:09:28 AM UTC 24 Sep 09 05:09:30 AM UTC 24 373183949 ps
T910 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.276129548 Sep 09 05:09:28 AM UTC 24 Sep 09 05:09:30 AM UTC 24 336620325 ps
T911 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.1506033389 Sep 09 05:09:29 AM UTC 24 Sep 09 05:09:31 AM UTC 24 419166122 ps
T912 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.1717002022 Sep 09 05:09:28 AM UTC 24 Sep 09 05:09:31 AM UTC 24 325830931 ps
T913 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.3648983998 Sep 09 05:09:29 AM UTC 24 Sep 09 05:09:31 AM UTC 24 512849342 ps
T914 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3229846510 Sep 09 05:09:07 AM UTC 24 Sep 09 05:09:32 AM UTC 24 4492480207 ps
T915 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.2098658544 Sep 09 05:09:29 AM UTC 24 Sep 09 05:09:32 AM UTC 24 319635468 ps
T916 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2807441572 Sep 09 05:09:29 AM UTC 24 Sep 09 05:09:33 AM UTC 24 346605003 ps
T917 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.884976421 Sep 09 05:09:29 AM UTC 24 Sep 09 05:09:33 AM UTC 24 507885030 ps
T918 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1751001522 Sep 09 05:09:05 AM UTC 24 Sep 09 05:09:34 AM UTC 24 8290771815 ps
T919 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.653131444 Sep 09 05:09:18 AM UTC 24 Sep 09 05:09:41 AM UTC 24 4706807610 ps
T920 /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1063587357 Sep 09 05:09:15 AM UTC 24 Sep 09 05:09:54 AM UTC 24 7992447778 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2742855740
Short name T5
Test name
Test status
Simulation time 17585185415 ps
CPU time 12.59 seconds
Started Sep 09 05:19:07 AM UTC 24
Finished Sep 09 05:19:20 AM UTC 24
Peak memory 211732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2742855740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.adc_ctrl_stress_all_with_rand_reset.2742855740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.513854206
Short name T51
Test name
Test status
Simulation time 77425777547 ps
CPU time 365.39 seconds
Started Sep 09 05:19:07 AM UTC 24
Finished Sep 09 05:25:16 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513854206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.513854206
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.2277526303
Short name T19
Test name
Test status
Simulation time 484090399356 ps
CPU time 142.48 seconds
Started Sep 09 05:19:20 AM UTC 24
Finished Sep 09 05:21:45 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277526303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2277526303
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3456644888
Short name T24
Test name
Test status
Simulation time 3328608902 ps
CPU time 21.66 seconds
Started Sep 09 05:20:06 AM UTC 24
Finished Sep 09 05:20:29 AM UTC 24
Peak memory 221888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3456644888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.adc_ctrl_stress_all_with_rand_reset.3456644888
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.245433187
Short name T136
Test name
Test status
Simulation time 497573357134 ps
CPU time 408.07 seconds
Started Sep 09 05:19:48 AM UTC 24
Finished Sep 09 05:26:41 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245433187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.245433187
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.164623570
Short name T50
Test name
Test status
Simulation time 526055885592 ps
CPU time 249.07 seconds
Started Sep 09 05:19:24 AM UTC 24
Finished Sep 09 05:23:37 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164623570 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.164623570
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.1097286495
Short name T236
Test name
Test status
Simulation time 733642969020 ps
CPU time 468.2 seconds
Started Sep 09 05:34:05 AM UTC 24
Finished Sep 09 05:41:59 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097286495 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.1097286495
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2152718057
Short name T58
Test name
Test status
Simulation time 92600723531 ps
CPU time 483.62 seconds
Started Sep 09 05:23:57 AM UTC 24
Finished Sep 09 05:32:05 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152718057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2152718057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.330990013
Short name T238
Test name
Test status
Simulation time 527678910500 ps
CPU time 1255.05 seconds
Started Sep 09 05:19:24 AM UTC 24
Finished Sep 09 05:40:32 AM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330990013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.330990013
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.276537187
Short name T25
Test name
Test status
Simulation time 2878830729 ps
CPU time 13 seconds
Started Sep 09 05:24:21 AM UTC 24
Finished Sep 09 05:24:35 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=276537187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.adc_ctrl_stress_all_with_rand_reset.276537187
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1833127292
Short name T164
Test name
Test status
Simulation time 487032570217 ps
CPU time 1097.76 seconds
Started Sep 09 05:19:05 AM UTC 24
Finished Sep 09 05:37:34 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833127292 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.1833127292
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.3467577056
Short name T152
Test name
Test status
Simulation time 550807660472 ps
CPU time 236.22 seconds
Started Sep 09 05:35:07 AM UTC 24
Finished Sep 09 05:39:07 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467577056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3467577056
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.446801236
Short name T2
Test name
Test status
Simulation time 8224437838 ps
CPU time 3.91 seconds
Started Sep 09 05:19:07 AM UTC 24
Finished Sep 09 05:19:12 AM UTC 24
Peak memory 243552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446801236 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.446801236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.335312593
Short name T173
Test name
Test status
Simulation time 485163402163 ps
CPU time 327.09 seconds
Started Sep 09 05:34:22 AM UTC 24
Finished Sep 09 05:39:53 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335312593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.335312593
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1243978653
Short name T20
Test name
Test status
Simulation time 199835710855 ps
CPU time 180.13 seconds
Started Sep 09 05:19:09 AM UTC 24
Finished Sep 09 05:22:12 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243978653 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.1243978653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3220032364
Short name T239
Test name
Test status
Simulation time 492240560009 ps
CPU time 431.3 seconds
Started Sep 09 05:33:10 AM UTC 24
Finished Sep 09 05:40:26 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220032364 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.3220032364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2281148887
Short name T74
Test name
Test status
Simulation time 372697285 ps
CPU time 4.79 seconds
Started Sep 09 05:07:48 AM UTC 24
Finished Sep 09 05:07:54 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281148887 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2281148887
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2544364112
Short name T149
Test name
Test status
Simulation time 596306241025 ps
CPU time 141.76 seconds
Started Sep 09 05:31:34 AM UTC 24
Finished Sep 09 05:33:59 AM UTC 24
Peak memory 211596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544364112 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.2544364112
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.911167688
Short name T231
Test name
Test status
Simulation time 337238629358 ps
CPU time 78.48 seconds
Started Sep 09 05:34:52 AM UTC 24
Finished Sep 09 05:36:12 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911167688 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.911167688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1021992520
Short name T43
Test name
Test status
Simulation time 195639073357 ps
CPU time 72.36 seconds
Started Sep 09 05:22:27 AM UTC 24
Finished Sep 09 05:23:41 AM UTC 24
Peak memory 221804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1021992520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.adc_ctrl_stress_all_with_rand_reset.1021992520
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.974245772
Short name T110
Test name
Test status
Simulation time 426054180 ps
CPU time 3.12 seconds
Started Sep 09 05:07:45 AM UTC 24
Finished Sep 09 05:07:49 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974245772 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.974245772
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.1317568988
Short name T329
Test name
Test status
Simulation time 585681010583 ps
CPU time 274.79 seconds
Started Sep 09 05:52:47 AM UTC 24
Finished Sep 09 05:57:25 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317568988 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.1317568988
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2089521056
Short name T233
Test name
Test status
Simulation time 546424376565 ps
CPU time 334.74 seconds
Started Sep 09 05:33:00 AM UTC 24
Finished Sep 09 05:38:38 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089521056 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.2089521056
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.492987837
Short name T162
Test name
Test status
Simulation time 486966762809 ps
CPU time 246.41 seconds
Started Sep 09 05:26:42 AM UTC 24
Finished Sep 09 05:30:51 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492987837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.492987837
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.4075164144
Short name T175
Test name
Test status
Simulation time 491121434136 ps
CPU time 522 seconds
Started Sep 09 05:38:40 AM UTC 24
Finished Sep 09 05:47:28 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075164144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4075164144
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.4020759924
Short name T134
Test name
Test status
Simulation time 346859768588 ps
CPU time 222.63 seconds
Started Sep 09 05:21:30 AM UTC 24
Finished Sep 09 05:25:16 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020759924 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.4020759924
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.3022499031
Short name T177
Test name
Test status
Simulation time 499833981594 ps
CPU time 305.45 seconds
Started Sep 09 05:59:58 AM UTC 24
Finished Sep 09 06:05:07 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022499031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3022499031
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3300072151
Short name T246
Test name
Test status
Simulation time 553800594407 ps
CPU time 747.67 seconds
Started Sep 09 05:36:44 AM UTC 24
Finished Sep 09 05:49:20 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300072151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3300072151
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.3179456223
Short name T245
Test name
Test status
Simulation time 334073330054 ps
CPU time 518.45 seconds
Started Sep 09 05:36:14 AM UTC 24
Finished Sep 09 05:44:58 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179456223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3179456223
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1164686491
Short name T257
Test name
Test status
Simulation time 345570352840 ps
CPU time 239.79 seconds
Started Sep 09 05:44:47 AM UTC 24
Finished Sep 09 05:48:50 AM UTC 24
Peak memory 211860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164686491 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.1164686491
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.340448820
Short name T41
Test name
Test status
Simulation time 172300358771 ps
CPU time 174.93 seconds
Started Sep 09 05:19:20 AM UTC 24
Finished Sep 09 05:22:17 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340448820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.340448820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.4220612296
Short name T147
Test name
Test status
Simulation time 497808713837 ps
CPU time 302.56 seconds
Started Sep 09 05:23:18 AM UTC 24
Finished Sep 09 05:28:24 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220612296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.4220612296
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.334435156
Short name T332
Test name
Test status
Simulation time 331126032441 ps
CPU time 197.45 seconds
Started Sep 09 06:04:20 AM UTC 24
Finished Sep 09 06:07:40 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334435156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.334435156
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1329213226
Short name T1
Test name
Test status
Simulation time 348237477 ps
CPU time 1.36 seconds
Started Sep 09 05:19:08 AM UTC 24
Finished Sep 09 05:19:10 AM UTC 24
Peak memory 210692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329213226 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1329213226
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.342237591
Short name T328
Test name
Test status
Simulation time 696213962023 ps
CPU time 805.39 seconds
Started Sep 09 05:54:44 AM UTC 24
Finished Sep 09 06:08:18 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342237591 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.342237591
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3116659324
Short name T374
Test name
Test status
Simulation time 8834518380 ps
CPU time 9.42 seconds
Started Sep 09 05:08:24 AM UTC 24
Finished Sep 09 05:08:35 AM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116659324 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.3116659324
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2140982547
Short name T65
Test name
Test status
Simulation time 28816797422 ps
CPU time 38.63 seconds
Started Sep 09 05:07:32 AM UTC 24
Finished Sep 09 05:08:12 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140982547 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.2140982547
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.238491492
Short name T317
Test name
Test status
Simulation time 340962475324 ps
CPU time 935.16 seconds
Started Sep 09 05:54:34 AM UTC 24
Finished Sep 09 06:10:19 AM UTC 24
Peak memory 212592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238491492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.238491492
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.1104740744
Short name T193
Test name
Test status
Simulation time 540801335284 ps
CPU time 352.5 seconds
Started Sep 09 05:59:50 AM UTC 24
Finished Sep 09 06:05:46 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104740744 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.1104740744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.1953746710
Short name T281
Test name
Test status
Simulation time 343110893615 ps
CPU time 503.7 seconds
Started Sep 09 05:46:58 AM UTC 24
Finished Sep 09 05:55:27 AM UTC 24
Peak memory 211388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953746710 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.1953746710
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.24958977
Short name T194
Test name
Test status
Simulation time 517992748459 ps
CPU time 461.96 seconds
Started Sep 09 05:44:59 AM UTC 24
Finished Sep 09 05:52:46 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24958977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.24958977
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.1029252165
Short name T279
Test name
Test status
Simulation time 332820087968 ps
CPU time 1051.97 seconds
Started Sep 09 05:58:13 AM UTC 24
Finished Sep 09 06:15:56 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029252165 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.1029252165
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.969151337
Short name T151
Test name
Test status
Simulation time 488055208491 ps
CPU time 209.13 seconds
Started Sep 09 05:32:32 AM UTC 24
Finished Sep 09 05:36:04 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969151337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.969151337
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.729104863
Short name T6
Test name
Test status
Simulation time 175944188776 ps
CPU time 300.38 seconds
Started Sep 09 05:20:31 AM UTC 24
Finished Sep 09 05:25:35 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729104863 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.729104863
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.2554786423
Short name T320
Test name
Test status
Simulation time 164377878241 ps
CPU time 41.62 seconds
Started Sep 09 05:41:13 AM UTC 24
Finished Sep 09 05:41:56 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554786423 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.2554786423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.1853961651
Short name T295
Test name
Test status
Simulation time 324792151714 ps
CPU time 408.52 seconds
Started Sep 09 05:40:35 AM UTC 24
Finished Sep 09 05:47:28 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853961651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1853961651
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3819397088
Short name T393
Test name
Test status
Simulation time 160676809113 ps
CPU time 627.87 seconds
Started Sep 09 05:19:05 AM UTC 24
Finished Sep 09 05:29:41 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819397088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.3819397088
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.559073623
Short name T241
Test name
Test status
Simulation time 539006318857 ps
CPU time 330.58 seconds
Started Sep 09 05:43:41 AM UTC 24
Finished Sep 09 05:49:16 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559073623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.559073623
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.1309553021
Short name T268
Test name
Test status
Simulation time 352710412100 ps
CPU time 137.91 seconds
Started Sep 09 05:46:23 AM UTC 24
Finished Sep 09 05:48:43 AM UTC 24
Peak memory 211792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309553021 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.1309553021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.648782390
Short name T207
Test name
Test status
Simulation time 130506370643 ps
CPU time 928.49 seconds
Started Sep 09 05:19:13 AM UTC 24
Finished Sep 09 05:34:51 AM UTC 24
Peak memory 212768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648782390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.648782390
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.4208808896
Short name T342
Test name
Test status
Simulation time 202355136893 ps
CPU time 261.12 seconds
Started Sep 09 05:39:54 AM UTC 24
Finished Sep 09 05:44:18 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208808896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.4208808896
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.2397805097
Short name T333
Test name
Test status
Simulation time 544582353522 ps
CPU time 1463.89 seconds
Started Sep 09 06:01:36 AM UTC 24
Finished Sep 09 06:26:13 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397805097 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.2397805097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.3212783483
Short name T263
Test name
Test status
Simulation time 538149449316 ps
CPU time 383.38 seconds
Started Sep 09 06:04:06 AM UTC 24
Finished Sep 09 06:10:34 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212783483 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.3212783483
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1326073639
Short name T252
Test name
Test status
Simulation time 494557453155 ps
CPU time 1374.19 seconds
Started Sep 09 05:24:58 AM UTC 24
Finished Sep 09 05:48:06 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326073639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1326073639
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.435406441
Short name T348
Test name
Test status
Simulation time 415390394685 ps
CPU time 965.48 seconds
Started Sep 09 06:03:16 AM UTC 24
Finished Sep 09 06:19:32 AM UTC 24
Peak memory 212832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435406441 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.435406441
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.1528328255
Short name T785
Test name
Test status
Simulation time 347648581193 ps
CPU time 1024.66 seconds
Started Sep 09 06:20:53 AM UTC 24
Finished Sep 09 06:38:08 AM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528328255 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.1528328255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.127159009
Short name T379
Test name
Test status
Simulation time 129568006829 ps
CPU time 450.66 seconds
Started Sep 09 05:40:17 AM UTC 24
Finished Sep 09 05:47:52 AM UTC 24
Peak memory 212020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127159009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.127159009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.528358850
Short name T264
Test name
Test status
Simulation time 507508061489 ps
CPU time 1392.16 seconds
Started Sep 09 05:48:44 AM UTC 24
Finished Sep 09 06:12:10 AM UTC 24
Peak memory 212524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528358850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.528358850
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.3124303925
Short name T222
Test name
Test status
Simulation time 820565467994 ps
CPU time 501 seconds
Started Sep 09 05:57:17 AM UTC 24
Finished Sep 09 06:05:43 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124303925 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.3124303925
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1539310784
Short name T138
Test name
Test status
Simulation time 369452567716 ps
CPU time 510.89 seconds
Started Sep 09 05:19:40 AM UTC 24
Finished Sep 09 05:28:17 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539310784 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.1539310784
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.3909720902
Short name T272
Test name
Test status
Simulation time 338095483913 ps
CPU time 273.01 seconds
Started Sep 09 06:07:45 AM UTC 24
Finished Sep 09 06:12:22 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909720902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3909720902
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.383170622
Short name T312
Test name
Test status
Simulation time 488244941221 ps
CPU time 646.46 seconds
Started Sep 09 06:09:39 AM UTC 24
Finished Sep 09 06:20:32 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383170622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.383170622
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.1220011365
Short name T303
Test name
Test status
Simulation time 574974472679 ps
CPU time 328.5 seconds
Started Sep 09 06:17:51 AM UTC 24
Finished Sep 09 06:23:24 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220011365 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.1220011365
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.1805953387
Short name T265
Test name
Test status
Simulation time 501500086017 ps
CPU time 1652.28 seconds
Started Sep 09 06:03:37 AM UTC 24
Finished Sep 09 06:31:25 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805953387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1805953387
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3386027842
Short name T73
Test name
Test status
Simulation time 501510067 ps
CPU time 4.57 seconds
Started Sep 09 05:07:40 AM UTC 24
Finished Sep 09 05:07:45 AM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386027842 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3386027842
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.955051991
Short name T139
Test name
Test status
Simulation time 501840712265 ps
CPU time 564.11 seconds
Started Sep 09 05:19:04 AM UTC 24
Finished Sep 09 05:28:35 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955051991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.955051991
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3628789058
Short name T337
Test name
Test status
Simulation time 9565239680 ps
CPU time 9.8 seconds
Started Sep 09 05:45:20 AM UTC 24
Finished Sep 09 05:45:31 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3628789058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.adc_ctrl_stress_all_with_rand_reset.3628789058
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.1254950435
Short name T178
Test name
Test status
Simulation time 608273499132 ps
CPU time 1321.15 seconds
Started Sep 09 05:46:14 AM UTC 24
Finished Sep 09 06:08:28 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254950435 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.1254950435
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.416003311
Short name T331
Test name
Test status
Simulation time 337415498964 ps
CPU time 421.15 seconds
Started Sep 09 05:47:40 AM UTC 24
Finished Sep 09 05:54:46 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416003311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.416003311
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.1528342002
Short name T227
Test name
Test status
Simulation time 558420513399 ps
CPU time 1624.2 seconds
Started Sep 09 05:54:08 AM UTC 24
Finished Sep 09 06:21:28 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528342002 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.1528342002
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.3576159126
Short name T362
Test name
Test status
Simulation time 513624791593 ps
CPU time 1547.77 seconds
Started Sep 09 06:15:00 AM UTC 24
Finished Sep 09 06:41:03 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576159126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3576159126
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.303042981
Short name T290
Test name
Test status
Simulation time 489408504584 ps
CPU time 383.05 seconds
Started Sep 09 06:21:56 AM UTC 24
Finished Sep 09 06:28:23 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303042981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.303042981
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2573294341
Short name T83
Test name
Test status
Simulation time 9642297420 ps
CPU time 5.42 seconds
Started Sep 09 05:08:50 AM UTC 24
Finished Sep 09 05:08:56 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573294341 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.2573294341
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.843386969
Short name T52
Test name
Test status
Simulation time 81742385133 ps
CPU time 478.55 seconds
Started Sep 09 05:19:13 AM UTC 24
Finished Sep 09 05:27:17 AM UTC 24
Peak memory 221836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843386969 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.843386969
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.795901640
Short name T269
Test name
Test status
Simulation time 497990801551 ps
CPU time 1360.81 seconds
Started Sep 09 05:30:47 AM UTC 24
Finished Sep 09 05:53:42 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795901640 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.795901640
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1526621070
Short name T215
Test name
Test status
Simulation time 461280644141 ps
CPU time 820.5 seconds
Started Sep 09 05:32:27 AM UTC 24
Finished Sep 09 05:46:15 AM UTC 24
Peak memory 213076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526621070 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.1526621070
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.3901362641
Short name T163
Test name
Test status
Simulation time 331605294304 ps
CPU time 131.49 seconds
Started Sep 09 05:32:31 AM UTC 24
Finished Sep 09 05:34:45 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901362641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3901362641
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.360992228
Short name T190
Test name
Test status
Simulation time 539069635778 ps
CPU time 403.55 seconds
Started Sep 09 05:39:47 AM UTC 24
Finished Sep 09 05:46:36 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360992228 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.360992228
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.2725638155
Short name T195
Test name
Test status
Simulation time 504555058508 ps
CPU time 394.2 seconds
Started Sep 09 05:57:40 AM UTC 24
Finished Sep 09 06:04:19 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725638155 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.2725638155
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4228385545
Short name T180
Test name
Test status
Simulation time 2624416975 ps
CPU time 12.49 seconds
Started Sep 09 06:12:01 AM UTC 24
Finished Sep 09 06:12:15 AM UTC 24
Peak memory 221676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4228385545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.adc_ctrl_stress_all_with_rand_reset.4228385545
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4022738193
Short name T639
Test name
Test status
Simulation time 10173128449 ps
CPU time 8.2 seconds
Started Sep 09 06:13:28 AM UTC 24
Finished Sep 09 06:13:37 AM UTC 24
Peak memory 221740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4022738193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.adc_ctrl_stress_all_with_rand_reset.4022738193
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.3074465232
Short name T182
Test name
Test status
Simulation time 498075837374 ps
CPU time 185.56 seconds
Started Sep 09 06:18:31 AM UTC 24
Finished Sep 09 06:21:39 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074465232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3074465232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.4213949118
Short name T355
Test name
Test status
Simulation time 160063022350 ps
CPU time 326.91 seconds
Started Sep 09 06:17:15 AM UTC 24
Finished Sep 09 06:22:46 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213949118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4213949118
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2740652055
Short name T270
Test name
Test status
Simulation time 496218801772 ps
CPU time 985.63 seconds
Started Sep 09 05:22:57 AM UTC 24
Finished Sep 09 05:39:33 AM UTC 24
Peak memory 212508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740652055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2740652055
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.767666972
Short name T298
Test name
Test status
Simulation time 327358306419 ps
CPU time 796.39 seconds
Started Sep 09 05:28:12 AM UTC 24
Finished Sep 09 05:41:36 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767666972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.767666972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3464232936
Short name T234
Test name
Test status
Simulation time 169620001347 ps
CPU time 159.89 seconds
Started Sep 09 05:29:48 AM UTC 24
Finished Sep 09 05:32:31 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464232936 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.3464232936
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.1060630184
Short name T224
Test name
Test status
Simulation time 137797231972 ps
CPU time 1013.37 seconds
Started Sep 09 05:33:39 AM UTC 24
Finished Sep 09 05:50:43 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060630184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1060630184
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.553748055
Short name T59
Test name
Test status
Simulation time 138187997159 ps
CPU time 460.25 seconds
Started Sep 09 05:35:50 AM UTC 24
Finished Sep 09 05:43:35 AM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553748055 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.553748055
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.1534985463
Short name T210
Test name
Test status
Simulation time 92262357246 ps
CPU time 362.2 seconds
Started Sep 09 05:36:53 AM UTC 24
Finished Sep 09 05:42:59 AM UTC 24
Peak memory 211960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534985463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1534985463
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1351750423
Short name T237
Test name
Test status
Simulation time 14505277178 ps
CPU time 18.6 seconds
Started Sep 09 05:36:54 AM UTC 24
Finished Sep 09 05:37:14 AM UTC 24
Peak memory 221892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1351750423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.adc_ctrl_stress_all_with_rand_reset.1351750423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2984757302
Short name T206
Test name
Test status
Simulation time 3964105176 ps
CPU time 11.41 seconds
Started Sep 09 05:40:19 AM UTC 24
Finished Sep 09 05:40:31 AM UTC 24
Peak memory 221956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2984757302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.adc_ctrl_stress_all_with_rand_reset.2984757302
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.2684081896
Short name T176
Test name
Test status
Simulation time 550951069488 ps
CPU time 435.36 seconds
Started Sep 09 05:44:26 AM UTC 24
Finished Sep 09 05:51:46 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684081896 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.2684081896
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.3416691441
Short name T292
Test name
Test status
Simulation time 349122426545 ps
CPU time 327.46 seconds
Started Sep 09 05:49:37 AM UTC 24
Finished Sep 09 05:55:09 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416691441 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.3416691441
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.579569388
Short name T250
Test name
Test status
Simulation time 331205148095 ps
CPU time 200.85 seconds
Started Sep 09 06:08:28 AM UTC 24
Finished Sep 09 06:11:52 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579569388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.579569388
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.3248458075
Short name T378
Test name
Test status
Simulation time 127843681130 ps
CPU time 753.02 seconds
Started Sep 09 06:08:46 AM UTC 24
Finished Sep 09 06:21:26 AM UTC 24
Peak memory 211708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248458075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3248458075
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.1628591508
Short name T220
Test name
Test status
Simulation time 122006185544 ps
CPU time 525.68 seconds
Started Sep 09 06:13:20 AM UTC 24
Finished Sep 09 06:22:11 AM UTC 24
Peak memory 211704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628591508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1628591508
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.2634990041
Short name T345
Test name
Test status
Simulation time 184103681367 ps
CPU time 421.92 seconds
Started Sep 09 06:27:14 AM UTC 24
Finished Sep 09 06:34:21 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634990041 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.2634990041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.3785840239
Short name T289
Test name
Test status
Simulation time 491439979577 ps
CPU time 125.95 seconds
Started Sep 09 06:27:26 AM UTC 24
Finished Sep 09 06:29:34 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785840239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3785840239
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1823144513
Short name T127
Test name
Test status
Simulation time 820536159 ps
CPU time 5.81 seconds
Started Sep 09 05:07:34 AM UTC 24
Finished Sep 09 05:07:41 AM UTC 24
Peak memory 211368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823144513 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.1823144513
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1604949847
Short name T107
Test name
Test status
Simulation time 1208599384 ps
CPU time 2.74 seconds
Started Sep 09 05:07:28 AM UTC 24
Finished Sep 09 05:07:32 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604949847 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.1604949847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.462948686
Short name T70
Test name
Test status
Simulation time 663943639 ps
CPU time 1.85 seconds
Started Sep 09 05:07:36 AM UTC 24
Finished Sep 09 05:07:39 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=462948686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr
_mem_rw_with_rand_reset.462948686
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1699255480
Short name T108
Test name
Test status
Simulation time 531169476 ps
CPU time 1.9 seconds
Started Sep 09 05:07:30 AM UTC 24
Finished Sep 09 05:07:33 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699255480 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1699255480
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.3256097004
Short name T801
Test name
Test status
Simulation time 513702735 ps
CPU time 2.12 seconds
Started Sep 09 05:07:26 AM UTC 24
Finished Sep 09 05:07:29 AM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256097004 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3256097004
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.849544023
Short name T64
Test name
Test status
Simulation time 4389415304 ps
CPU time 19.03 seconds
Started Sep 09 05:07:35 AM UTC 24
Finished Sep 09 05:07:56 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849544023 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.849544023
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1102746653
Short name T69
Test name
Test status
Simulation time 575087860 ps
CPU time 3.56 seconds
Started Sep 09 05:07:19 AM UTC 24
Finished Sep 09 05:07:24 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102746653 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1102746653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1801321086
Short name T66
Test name
Test status
Simulation time 4668494306 ps
CPU time 8.15 seconds
Started Sep 09 05:07:25 AM UTC 24
Finished Sep 09 05:07:35 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801321086 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.1801321086
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2461632022
Short name T111
Test name
Test status
Simulation time 1179459343 ps
CPU time 5.5 seconds
Started Sep 09 05:07:46 AM UTC 24
Finished Sep 09 05:07:53 AM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461632022 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.2461632022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2528499672
Short name T827
Test name
Test status
Simulation time 52725263086 ps
CPU time 56.81 seconds
Started Sep 09 05:07:46 AM UTC 24
Finished Sep 09 05:08:44 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528499672 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.2528499672
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3832281137
Short name T109
Test name
Test status
Simulation time 603762077 ps
CPU time 2.57 seconds
Started Sep 09 05:07:42 AM UTC 24
Finished Sep 09 05:07:45 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832281137 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.3832281137
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3132495426
Short name T80
Test name
Test status
Simulation time 511917961 ps
CPU time 3.78 seconds
Started Sep 09 05:07:47 AM UTC 24
Finished Sep 09 05:07:52 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3132495426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cs
r_mem_rw_with_rand_reset.3132495426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3327773655
Short name T802
Test name
Test status
Simulation time 554740126 ps
CPU time 1.34 seconds
Started Sep 09 05:07:42 AM UTC 24
Finished Sep 09 05:07:44 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327773655 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3327773655
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4220244099
Short name T63
Test name
Test status
Simulation time 2429981244 ps
CPU time 5.44 seconds
Started Sep 09 05:07:46 AM UTC 24
Finished Sep 09 05:07:52 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220244099 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.4220244099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4251424803
Short name T67
Test name
Test status
Simulation time 4786882949 ps
CPU time 5.83 seconds
Started Sep 09 05:07:41 AM UTC 24
Finished Sep 09 05:07:48 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251424803 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.4251424803
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.310896835
Short name T835
Test name
Test status
Simulation time 408852120 ps
CPU time 2.53 seconds
Started Sep 09 05:08:45 AM UTC 24
Finished Sep 09 05:08:49 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=310896835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_cs
r_mem_rw_with_rand_reset.310896835
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4255122782
Short name T834
Test name
Test status
Simulation time 554950841 ps
CPU time 1.75 seconds
Started Sep 09 05:08:45 AM UTC 24
Finished Sep 09 05:08:48 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255122782 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4255122782
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3160235682
Short name T833
Test name
Test status
Simulation time 410326261 ps
CPU time 2.69 seconds
Started Sep 09 05:08:44 AM UTC 24
Finished Sep 09 05:08:48 AM UTC 24
Peak memory 211108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160235682 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3160235682
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.415123989
Short name T864
Test name
Test status
Simulation time 4485374428 ps
CPU time 24.96 seconds
Started Sep 09 05:08:45 AM UTC 24
Finished Sep 09 05:09:11 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415123989 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.415123989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3859328636
Short name T831
Test name
Test status
Simulation time 507722467 ps
CPU time 2.18 seconds
Started Sep 09 05:08:42 AM UTC 24
Finished Sep 09 05:08:45 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859328636 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3859328636
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3260132836
Short name T839
Test name
Test status
Simulation time 8980337859 ps
CPU time 8.79 seconds
Started Sep 09 05:08:43 AM UTC 24
Finished Sep 09 05:08:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260132836 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.3260132836
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1154091074
Short name T840
Test name
Test status
Simulation time 354025960 ps
CPU time 1.63 seconds
Started Sep 09 05:08:48 AM UTC 24
Finished Sep 09 05:08:51 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1154091074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_c
sr_mem_rw_with_rand_reset.1154091074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.101632441
Short name T836
Test name
Test status
Simulation time 586430767 ps
CPU time 1.44 seconds
Started Sep 09 05:08:47 AM UTC 24
Finished Sep 09 05:08:50 AM UTC 24
Peak memory 209916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101632441 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.101632441
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2804294115
Short name T838
Test name
Test status
Simulation time 426740502 ps
CPU time 2.67 seconds
Started Sep 09 05:08:47 AM UTC 24
Finished Sep 09 05:08:51 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804294115 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2804294115
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2978285262
Short name T883
Test name
Test status
Simulation time 5056094400 ps
CPU time 31.9 seconds
Started Sep 09 05:08:48 AM UTC 24
Finished Sep 09 05:09:22 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978285262 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.2978285262
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.78120166
Short name T842
Test name
Test status
Simulation time 578871161 ps
CPU time 5.91 seconds
Started Sep 09 05:08:46 AM UTC 24
Finished Sep 09 05:08:53 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78120166 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.78120166
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1172052299
Short name T851
Test name
Test status
Simulation time 3979862217 ps
CPU time 12.25 seconds
Started Sep 09 05:08:46 AM UTC 24
Finished Sep 09 05:09:00 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172052299 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.1172052299
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3748752713
Short name T847
Test name
Test status
Simulation time 385760862 ps
CPU time 3.39 seconds
Started Sep 09 05:08:52 AM UTC 24
Finished Sep 09 05:08:56 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3748752713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c
sr_mem_rw_with_rand_reset.3748752713
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3363442398
Short name T843
Test name
Test status
Simulation time 509257485 ps
CPU time 2.4 seconds
Started Sep 09 05:08:51 AM UTC 24
Finished Sep 09 05:08:54 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363442398 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3363442398
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.1185557374
Short name T844
Test name
Test status
Simulation time 450457867 ps
CPU time 3.15 seconds
Started Sep 09 05:08:51 AM UTC 24
Finished Sep 09 05:08:55 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185557374 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1185557374
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.463870911
Short name T862
Test name
Test status
Simulation time 2319811965 ps
CPU time 15.59 seconds
Started Sep 09 05:08:52 AM UTC 24
Finished Sep 09 05:09:09 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463870911 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.463870911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.895938342
Short name T841
Test name
Test status
Simulation time 522758328 ps
CPU time 3.52 seconds
Started Sep 09 05:08:48 AM UTC 24
Finished Sep 09 05:08:53 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895938342 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.895938342
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3328767629
Short name T852
Test name
Test status
Simulation time 511776122 ps
CPU time 4.04 seconds
Started Sep 09 05:08:56 AM UTC 24
Finished Sep 09 05:09:01 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3328767629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_c
sr_mem_rw_with_rand_reset.3328767629
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2368128340
Short name T849
Test name
Test status
Simulation time 479112931 ps
CPU time 3.41 seconds
Started Sep 09 05:08:54 AM UTC 24
Finished Sep 09 05:08:59 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368128340 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2368128340
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1246136180
Short name T848
Test name
Test status
Simulation time 491735718 ps
CPU time 2.24 seconds
Started Sep 09 05:08:54 AM UTC 24
Finished Sep 09 05:08:57 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246136180 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1246136180
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1396650821
Short name T865
Test name
Test status
Simulation time 2091398210 ps
CPU time 15.48 seconds
Started Sep 09 05:08:55 AM UTC 24
Finished Sep 09 05:09:12 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396650821 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.1396650821
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.53202744
Short name T846
Test name
Test status
Simulation time 677088921 ps
CPU time 2.44 seconds
Started Sep 09 05:08:53 AM UTC 24
Finished Sep 09 05:08:56 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53202744 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.53202744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.820810860
Short name T877
Test name
Test status
Simulation time 8504214516 ps
CPU time 23.68 seconds
Started Sep 09 05:08:54 AM UTC 24
Finished Sep 09 05:09:19 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820810860 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.820810860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1153018188
Short name T855
Test name
Test status
Simulation time 423416525 ps
CPU time 3.24 seconds
Started Sep 09 05:08:59 AM UTC 24
Finished Sep 09 05:09:04 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1153018188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_c
sr_mem_rw_with_rand_reset.1153018188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2754253359
Short name T117
Test name
Test status
Simulation time 380921105 ps
CPU time 3.16 seconds
Started Sep 09 05:08:57 AM UTC 24
Finished Sep 09 05:09:02 AM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754253359 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2754253359
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.810576904
Short name T850
Test name
Test status
Simulation time 319034029 ps
CPU time 1.34 seconds
Started Sep 09 05:08:57 AM UTC 24
Finished Sep 09 05:09:00 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810576904 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.810576904
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3318803251
Short name T854
Test name
Test status
Simulation time 2577265548 ps
CPU time 3.6 seconds
Started Sep 09 05:08:58 AM UTC 24
Finished Sep 09 05:09:03 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318803251 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.3318803251
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1033242823
Short name T853
Test name
Test status
Simulation time 495202076 ps
CPU time 4.32 seconds
Started Sep 09 05:08:56 AM UTC 24
Finished Sep 09 05:09:02 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033242823 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1033242823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1484556191
Short name T857
Test name
Test status
Simulation time 4350786964 ps
CPU time 6.88 seconds
Started Sep 09 05:08:57 AM UTC 24
Finished Sep 09 05:09:05 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484556191 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.1484556191
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.855202740
Short name T859
Test name
Test status
Simulation time 308659568 ps
CPU time 2.8 seconds
Started Sep 09 05:09:04 AM UTC 24
Finished Sep 09 05:09:08 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=855202740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_cs
r_mem_rw_with_rand_reset.855202740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3235071916
Short name T120
Test name
Test status
Simulation time 337011663 ps
CPU time 2.87 seconds
Started Sep 09 05:09:03 AM UTC 24
Finished Sep 09 05:09:07 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235071916 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3235071916
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.827559821
Short name T856
Test name
Test status
Simulation time 331709804 ps
CPU time 1.39 seconds
Started Sep 09 05:09:02 AM UTC 24
Finished Sep 09 05:09:04 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827559821 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.827559821
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3274843182
Short name T871
Test name
Test status
Simulation time 3862914918 ps
CPU time 10.31 seconds
Started Sep 09 05:09:03 AM UTC 24
Finished Sep 09 05:09:14 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274843182 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.3274843182
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2203065594
Short name T858
Test name
Test status
Simulation time 521082596 ps
CPU time 4.85 seconds
Started Sep 09 05:09:01 AM UTC 24
Finished Sep 09 05:09:07 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203065594 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2203065594
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2493484681
Short name T897
Test name
Test status
Simulation time 4464695034 ps
CPU time 24.87 seconds
Started Sep 09 05:09:01 AM UTC 24
Finished Sep 09 05:09:27 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493484681 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.2493484681
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1281718420
Short name T868
Test name
Test status
Simulation time 418202154 ps
CPU time 3.27 seconds
Started Sep 09 05:09:08 AM UTC 24
Finished Sep 09 05:09:12 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1281718420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_c
sr_mem_rw_with_rand_reset.1281718420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3468990399
Short name T861
Test name
Test status
Simulation time 464704242 ps
CPU time 1.26 seconds
Started Sep 09 05:09:06 AM UTC 24
Finished Sep 09 05:09:08 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468990399 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3468990399
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2367965024
Short name T860
Test name
Test status
Simulation time 553340434 ps
CPU time 1.16 seconds
Started Sep 09 05:09:06 AM UTC 24
Finished Sep 09 05:09:08 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367965024 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2367965024
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3229846510
Short name T914
Test name
Test status
Simulation time 4492480207 ps
CPU time 23.57 seconds
Started Sep 09 05:09:07 AM UTC 24
Finished Sep 09 05:09:32 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229846510 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.3229846510
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2170755938
Short name T863
Test name
Test status
Simulation time 766651647 ps
CPU time 3.6 seconds
Started Sep 09 05:09:05 AM UTC 24
Finished Sep 09 05:09:10 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170755938 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2170755938
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1751001522
Short name T918
Test name
Test status
Simulation time 8290771815 ps
CPU time 27.74 seconds
Started Sep 09 05:09:05 AM UTC 24
Finished Sep 09 05:09:34 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751001522 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.1751001522
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3848907638
Short name T869
Test name
Test status
Simulation time 523242128 ps
CPU time 2.1 seconds
Started Sep 09 05:09:10 AM UTC 24
Finished Sep 09 05:09:13 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3848907638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c
sr_mem_rw_with_rand_reset.3848907638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2527765591
Short name T867
Test name
Test status
Simulation time 413442425 ps
CPU time 1.96 seconds
Started Sep 09 05:09:09 AM UTC 24
Finished Sep 09 05:09:12 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527765591 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2527765591
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1518282573
Short name T866
Test name
Test status
Simulation time 524594463 ps
CPU time 1.53 seconds
Started Sep 09 05:09:09 AM UTC 24
Finished Sep 09 05:09:12 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518282573 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1518282573
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3896861255
Short name T870
Test name
Test status
Simulation time 1792839015 ps
CPU time 2.28 seconds
Started Sep 09 05:09:10 AM UTC 24
Finished Sep 09 05:09:14 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896861255 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.3896861255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3876214312
Short name T872
Test name
Test status
Simulation time 380334449 ps
CPU time 4.68 seconds
Started Sep 09 05:09:09 AM UTC 24
Finished Sep 09 05:09:15 AM UTC 24
Peak memory 227696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876214312 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3876214312
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2712740200
Short name T890
Test name
Test status
Simulation time 8887384327 ps
CPU time 13.57 seconds
Started Sep 09 05:09:09 AM UTC 24
Finished Sep 09 05:09:24 AM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712740200 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.2712740200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1003749286
Short name T880
Test name
Test status
Simulation time 557315167 ps
CPU time 3.9 seconds
Started Sep 09 05:09:15 AM UTC 24
Finished Sep 09 05:09:20 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1003749286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c
sr_mem_rw_with_rand_reset.1003749286
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.765736868
Short name T878
Test name
Test status
Simulation time 550789492 ps
CPU time 4.1 seconds
Started Sep 09 05:09:14 AM UTC 24
Finished Sep 09 05:09:19 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765736868 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.765736868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.4206269040
Short name T873
Test name
Test status
Simulation time 533355828 ps
CPU time 1.51 seconds
Started Sep 09 05:09:13 AM UTC 24
Finished Sep 09 05:09:15 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206269040 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4206269040
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.648373443
Short name T882
Test name
Test status
Simulation time 4685926560 ps
CPU time 7.02 seconds
Started Sep 09 05:09:14 AM UTC 24
Finished Sep 09 05:09:22 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648373443 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.648373443
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.528448232
Short name T874
Test name
Test status
Simulation time 354560449 ps
CPU time 4.25 seconds
Started Sep 09 05:09:13 AM UTC 24
Finished Sep 09 05:09:18 AM UTC 24
Peak memory 227492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528448232 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.528448232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3866567406
Short name T889
Test name
Test status
Simulation time 4344269688 ps
CPU time 9.99 seconds
Started Sep 09 05:09:13 AM UTC 24
Finished Sep 09 05:09:24 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866567406 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.3866567406
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1653607693
Short name T888
Test name
Test status
Simulation time 345327726 ps
CPU time 2.97 seconds
Started Sep 09 05:09:19 AM UTC 24
Finished Sep 09 05:09:23 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1653607693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_c
sr_mem_rw_with_rand_reset.1653607693
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4276386440
Short name T876
Test name
Test status
Simulation time 468811150 ps
CPU time 1.7 seconds
Started Sep 09 05:09:16 AM UTC 24
Finished Sep 09 05:09:19 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276386440 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4276386440
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.717809479
Short name T879
Test name
Test status
Simulation time 410141445 ps
CPU time 1.99 seconds
Started Sep 09 05:09:16 AM UTC 24
Finished Sep 09 05:09:19 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717809479 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.717809479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.653131444
Short name T919
Test name
Test status
Simulation time 4706807610 ps
CPU time 21.51 seconds
Started Sep 09 05:09:18 AM UTC 24
Finished Sep 09 05:09:41 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653131444 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.653131444
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3848981715
Short name T875
Test name
Test status
Simulation time 799226784 ps
CPU time 2.63 seconds
Started Sep 09 05:09:15 AM UTC 24
Finished Sep 09 05:09:18 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848981715 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3848981715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1063587357
Short name T920
Test name
Test status
Simulation time 7992447778 ps
CPU time 37.49 seconds
Started Sep 09 05:09:15 AM UTC 24
Finished Sep 09 05:09:54 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063587357 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.1063587357
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2414552580
Short name T805
Test name
Test status
Simulation time 1220679230 ps
CPU time 9.19 seconds
Started Sep 09 05:07:55 AM UTC 24
Finished Sep 09 05:08:05 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414552580 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.2414552580
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3788711610
Short name T815
Test name
Test status
Simulation time 26271447980 ps
CPU time 35.66 seconds
Started Sep 09 05:07:55 AM UTC 24
Finished Sep 09 05:08:32 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788711610 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.3788711610
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2069317842
Short name T112
Test name
Test status
Simulation time 709535069 ps
CPU time 2.26 seconds
Started Sep 09 05:07:53 AM UTC 24
Finished Sep 09 05:07:57 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069317842 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.2069317842
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1587517377
Short name T81
Test name
Test status
Simulation time 464406367 ps
CPU time 1.93 seconds
Started Sep 09 05:07:57 AM UTC 24
Finished Sep 09 05:08:00 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1587517377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs
r_mem_rw_with_rand_reset.1587517377
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2354732941
Short name T128
Test name
Test status
Simulation time 416771078 ps
CPU time 1.42 seconds
Started Sep 09 05:07:53 AM UTC 24
Finished Sep 09 05:07:56 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354732941 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2354732941
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1006360065
Short name T803
Test name
Test status
Simulation time 360501115 ps
CPU time 2.63 seconds
Started Sep 09 05:07:52 AM UTC 24
Finished Sep 09 05:07:56 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006360065 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1006360065
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1229087836
Short name T121
Test name
Test status
Simulation time 2431274215 ps
CPU time 18.03 seconds
Started Sep 09 05:07:57 AM UTC 24
Finished Sep 09 05:08:16 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229087836 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.1229087836
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.159808330
Short name T79
Test name
Test status
Simulation time 5001639836 ps
CPU time 26.16 seconds
Started Sep 09 05:07:50 AM UTC 24
Finished Sep 09 05:08:18 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159808330 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.159808330
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.3239641767
Short name T881
Test name
Test status
Simulation time 381386348 ps
CPU time 1.06 seconds
Started Sep 09 05:09:19 AM UTC 24
Finished Sep 09 05:09:21 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239641767 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3239641767
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.912205600
Short name T887
Test name
Test status
Simulation time 509161084 ps
CPU time 1.67 seconds
Started Sep 09 05:09:20 AM UTC 24
Finished Sep 09 05:09:23 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912205600 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.912205600
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2622851141
Short name T885
Test name
Test status
Simulation time 327669273 ps
CPU time 1.34 seconds
Started Sep 09 05:09:20 AM UTC 24
Finished Sep 09 05:09:23 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622851141 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2622851141
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3994556232
Short name T886
Test name
Test status
Simulation time 354115053 ps
CPU time 1.3 seconds
Started Sep 09 05:09:20 AM UTC 24
Finished Sep 09 05:09:23 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994556232 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3994556232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.986474552
Short name T884
Test name
Test status
Simulation time 386440653 ps
CPU time 1.28 seconds
Started Sep 09 05:09:20 AM UTC 24
Finished Sep 09 05:09:23 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986474552 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.986474552
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3676604618
Short name T891
Test name
Test status
Simulation time 522710804 ps
CPU time 1.94 seconds
Started Sep 09 05:09:22 AM UTC 24
Finished Sep 09 05:09:24 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676604618 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3676604618
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.1948566201
Short name T896
Test name
Test status
Simulation time 485361451 ps
CPU time 3.18 seconds
Started Sep 09 05:09:23 AM UTC 24
Finished Sep 09 05:09:27 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948566201 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1948566201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.1721684616
Short name T892
Test name
Test status
Simulation time 306101330 ps
CPU time 1.48 seconds
Started Sep 09 05:09:23 AM UTC 24
Finished Sep 09 05:09:25 AM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721684616 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1721684616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2636444508
Short name T893
Test name
Test status
Simulation time 569642229 ps
CPU time 1.08 seconds
Started Sep 09 05:09:24 AM UTC 24
Finished Sep 09 05:09:26 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636444508 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2636444508
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.1672247079
Short name T902
Test name
Test status
Simulation time 490058308 ps
CPU time 3.03 seconds
Started Sep 09 05:09:24 AM UTC 24
Finished Sep 09 05:09:28 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672247079 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1672247079
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.265950086
Short name T807
Test name
Test status
Simulation time 971777024 ps
CPU time 6.51 seconds
Started Sep 09 05:08:05 AM UTC 24
Finished Sep 09 05:08:13 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265950086 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.265950086
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1242173317
Short name T118
Test name
Test status
Simulation time 46003970566 ps
CPU time 64.52 seconds
Started Sep 09 05:08:03 AM UTC 24
Finished Sep 09 05:09:09 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242173317 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.1242173317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1903928705
Short name T114
Test name
Test status
Simulation time 752182485 ps
CPU time 4.98 seconds
Started Sep 09 05:08:00 AM UTC 24
Finished Sep 09 05:08:06 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903928705 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.1903928705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2065496135
Short name T88
Test name
Test status
Simulation time 519103542 ps
CPU time 1.89 seconds
Started Sep 09 05:08:06 AM UTC 24
Finished Sep 09 05:08:09 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2065496135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cs
r_mem_rw_with_rand_reset.2065496135
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2705408863
Short name T113
Test name
Test status
Simulation time 342092352 ps
CPU time 2.64 seconds
Started Sep 09 05:08:02 AM UTC 24
Finished Sep 09 05:08:06 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705408863 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2705408863
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.4004061135
Short name T804
Test name
Test status
Simulation time 305784702 ps
CPU time 1.65 seconds
Started Sep 09 05:08:00 AM UTC 24
Finished Sep 09 05:08:03 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004061135 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4004061135
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.954193779
Short name T123
Test name
Test status
Simulation time 4595771735 ps
CPU time 22.19 seconds
Started Sep 09 05:08:06 AM UTC 24
Finished Sep 09 05:08:30 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954193779 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.954193779
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4140224719
Short name T77
Test name
Test status
Simulation time 497538475 ps
CPU time 3.35 seconds
Started Sep 09 05:07:57 AM UTC 24
Finished Sep 09 05:08:01 AM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140224719 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4140224719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1732600530
Short name T68
Test name
Test status
Simulation time 4246264777 ps
CPU time 7.32 seconds
Started Sep 09 05:07:58 AM UTC 24
Finished Sep 09 05:08:06 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732600530 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.1732600530
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.935069552
Short name T898
Test name
Test status
Simulation time 303718470 ps
CPU time 2.5 seconds
Started Sep 09 05:09:24 AM UTC 24
Finished Sep 09 05:09:27 AM UTC 24
Peak memory 211176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935069552 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.935069552
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.4137258007
Short name T899
Test name
Test status
Simulation time 472209838 ps
CPU time 2.57 seconds
Started Sep 09 05:09:24 AM UTC 24
Finished Sep 09 05:09:27 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137258007 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.4137258007
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3796543961
Short name T895
Test name
Test status
Simulation time 547394110 ps
CPU time 1.65 seconds
Started Sep 09 05:09:24 AM UTC 24
Finished Sep 09 05:09:27 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796543961 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3796543961
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3999076318
Short name T894
Test name
Test status
Simulation time 385299064 ps
CPU time 1.42 seconds
Started Sep 09 05:09:24 AM UTC 24
Finished Sep 09 05:09:26 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999076318 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3999076318
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.3801905180
Short name T900
Test name
Test status
Simulation time 414809227 ps
CPU time 1.43 seconds
Started Sep 09 05:09:25 AM UTC 24
Finished Sep 09 05:09:27 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801905180 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3801905180
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.3449851793
Short name T903
Test name
Test status
Simulation time 515063638 ps
CPU time 2.23 seconds
Started Sep 09 05:09:25 AM UTC 24
Finished Sep 09 05:09:28 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449851793 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3449851793
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2781969203
Short name T905
Test name
Test status
Simulation time 433910736 ps
CPU time 3.09 seconds
Started Sep 09 05:09:25 AM UTC 24
Finished Sep 09 05:09:29 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781969203 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2781969203
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.4221867094
Short name T901
Test name
Test status
Simulation time 469085992 ps
CPU time 1.46 seconds
Started Sep 09 05:09:25 AM UTC 24
Finished Sep 09 05:09:28 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221867094 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4221867094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.4110492617
Short name T907
Test name
Test status
Simulation time 441616249 ps
CPU time 2.15 seconds
Started Sep 09 05:09:26 AM UTC 24
Finished Sep 09 05:09:30 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110492617 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.4110492617
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.630293519
Short name T906
Test name
Test status
Simulation time 484994901 ps
CPU time 2.17 seconds
Started Sep 09 05:09:26 AM UTC 24
Finished Sep 09 05:09:30 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630293519 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.630293519
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4264663880
Short name T115
Test name
Test status
Simulation time 1089916397 ps
CPU time 5.95 seconds
Started Sep 09 05:08:14 AM UTC 24
Finished Sep 09 05:08:21 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264663880 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.4264663880
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1425612840
Short name T814
Test name
Test status
Simulation time 27078055628 ps
CPU time 16.01 seconds
Started Sep 09 05:08:14 AM UTC 24
Finished Sep 09 05:08:31 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425612840 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.1425612840
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1534246538
Short name T808
Test name
Test status
Simulation time 1266333901 ps
CPU time 7.53 seconds
Started Sep 09 05:08:11 AM UTC 24
Finished Sep 09 05:08:20 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534246538 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.1534246538
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2968755207
Short name T809
Test name
Test status
Simulation time 366734031 ps
CPU time 3.25 seconds
Started Sep 09 05:08:18 AM UTC 24
Finished Sep 09 05:08:22 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2968755207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cs
r_mem_rw_with_rand_reset.2968755207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1474044736
Short name T122
Test name
Test status
Simulation time 329195922 ps
CPU time 2.89 seconds
Started Sep 09 05:08:14 AM UTC 24
Finished Sep 09 05:08:17 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474044736 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1474044736
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1640873681
Short name T806
Test name
Test status
Simulation time 382719016 ps
CPU time 1.14 seconds
Started Sep 09 05:08:10 AM UTC 24
Finished Sep 09 05:08:13 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640873681 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1640873681
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1259812170
Short name T124
Test name
Test status
Simulation time 1958644163 ps
CPU time 15.37 seconds
Started Sep 09 05:08:17 AM UTC 24
Finished Sep 09 05:08:33 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259812170 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.1259812170
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.27877984
Short name T78
Test name
Test status
Simulation time 505214864 ps
CPU time 2.69 seconds
Started Sep 09 05:08:07 AM UTC 24
Finished Sep 09 05:08:11 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27877984 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.27877984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1946568186
Short name T71
Test name
Test status
Simulation time 8013820640 ps
CPU time 11.74 seconds
Started Sep 09 05:08:10 AM UTC 24
Finished Sep 09 05:08:23 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946568186 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.1946568186
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.1384653840
Short name T904
Test name
Test status
Simulation time 307857245 ps
CPU time 1.02 seconds
Started Sep 09 05:09:26 AM UTC 24
Finished Sep 09 05:09:28 AM UTC 24
Peak memory 209916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384653840 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1384653840
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.276129548
Short name T910
Test name
Test status
Simulation time 336620325 ps
CPU time 1.88 seconds
Started Sep 09 05:09:28 AM UTC 24
Finished Sep 09 05:09:30 AM UTC 24
Peak memory 209924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276129548 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.276129548
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.1717002022
Short name T912
Test name
Test status
Simulation time 325830931 ps
CPU time 2.65 seconds
Started Sep 09 05:09:28 AM UTC 24
Finished Sep 09 05:09:31 AM UTC 24
Peak memory 210844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717002022 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1717002022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.689796713
Short name T908
Test name
Test status
Simulation time 377154019 ps
CPU time 1.07 seconds
Started Sep 09 05:09:28 AM UTC 24
Finished Sep 09 05:09:30 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689796713 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.689796713
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.1028231745
Short name T909
Test name
Test status
Simulation time 373183949 ps
CPU time 1.36 seconds
Started Sep 09 05:09:28 AM UTC 24
Finished Sep 09 05:09:30 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028231745 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1028231745
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.3648983998
Short name T913
Test name
Test status
Simulation time 512849342 ps
CPU time 1.61 seconds
Started Sep 09 05:09:29 AM UTC 24
Finished Sep 09 05:09:31 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648983998 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3648983998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.1506033389
Short name T911
Test name
Test status
Simulation time 419166122 ps
CPU time 1.03 seconds
Started Sep 09 05:09:29 AM UTC 24
Finished Sep 09 05:09:31 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506033389 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1506033389
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.2098658544
Short name T915
Test name
Test status
Simulation time 319635468 ps
CPU time 2.37 seconds
Started Sep 09 05:09:29 AM UTC 24
Finished Sep 09 05:09:32 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098658544 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2098658544
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.884976421
Short name T917
Test name
Test status
Simulation time 507885030 ps
CPU time 3.6 seconds
Started Sep 09 05:09:29 AM UTC 24
Finished Sep 09 05:09:33 AM UTC 24
Peak memory 211176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884976421 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.884976421
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2807441572
Short name T916
Test name
Test status
Simulation time 346605003 ps
CPU time 2.67 seconds
Started Sep 09 05:09:29 AM UTC 24
Finished Sep 09 05:09:33 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807441572 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2807441572
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3217094232
Short name T812
Test name
Test status
Simulation time 323751906 ps
CPU time 2.64 seconds
Started Sep 09 05:08:24 AM UTC 24
Finished Sep 09 05:08:28 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3217094232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_cs
r_mem_rw_with_rand_reset.3217094232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2932577989
Short name T811
Test name
Test status
Simulation time 482362857 ps
CPU time 3.48 seconds
Started Sep 09 05:08:21 AM UTC 24
Finished Sep 09 05:08:25 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932577989 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2932577989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2451679320
Short name T810
Test name
Test status
Simulation time 373816817 ps
CPU time 1.89 seconds
Started Sep 09 05:08:21 AM UTC 24
Finished Sep 09 05:08:24 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451679320 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2451679320
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.38542544
Short name T125
Test name
Test status
Simulation time 2365127130 ps
CPU time 10.5 seconds
Started Sep 09 05:08:23 AM UTC 24
Finished Sep 09 05:08:35 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38542544 -assert nopostproc +
UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.38542544
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4229458427
Short name T75
Test name
Test status
Simulation time 1028371022 ps
CPU time 3.58 seconds
Started Sep 09 05:08:19 AM UTC 24
Finished Sep 09 05:08:23 AM UTC 24
Peak memory 221380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229458427 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4229458427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1596898116
Short name T72
Test name
Test status
Simulation time 8531433919 ps
CPU time 9.2 seconds
Started Sep 09 05:08:19 AM UTC 24
Finished Sep 09 05:08:29 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596898116 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.1596898116
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3257448306
Short name T817
Test name
Test status
Simulation time 386845496 ps
CPU time 3.33 seconds
Started Sep 09 05:08:31 AM UTC 24
Finished Sep 09 05:08:35 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3257448306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_cs
r_mem_rw_with_rand_reset.3257448306
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2805396243
Short name T116
Test name
Test status
Simulation time 508772149 ps
CPU time 3.91 seconds
Started Sep 09 05:08:28 AM UTC 24
Finished Sep 09 05:08:33 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805396243 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2805396243
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.1884151193
Short name T813
Test name
Test status
Simulation time 432318537 ps
CPU time 2.75 seconds
Started Sep 09 05:08:26 AM UTC 24
Finished Sep 09 05:08:30 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884151193 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1884151193
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3598973287
Short name T832
Test name
Test status
Simulation time 3014834645 ps
CPU time 15.61 seconds
Started Sep 09 05:08:29 AM UTC 24
Finished Sep 09 05:08:46 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598973287 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.3598973287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3719257077
Short name T76
Test name
Test status
Simulation time 626402349 ps
CPU time 3.26 seconds
Started Sep 09 05:08:24 AM UTC 24
Finished Sep 09 05:08:28 AM UTC 24
Peak memory 211360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719257077 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3719257077
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.219358762
Short name T820
Test name
Test status
Simulation time 485034676 ps
CPU time 1.84 seconds
Started Sep 09 05:08:34 AM UTC 24
Finished Sep 09 05:08:37 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=219358762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr
_mem_rw_with_rand_reset.219358762
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2354778127
Short name T819
Test name
Test status
Simulation time 337764593 ps
CPU time 1.42 seconds
Started Sep 09 05:08:33 AM UTC 24
Finished Sep 09 05:08:35 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354778127 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2354778127
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1914466384
Short name T818
Test name
Test status
Simulation time 520419822 ps
CPU time 2.22 seconds
Started Sep 09 05:08:32 AM UTC 24
Finished Sep 09 05:08:35 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914466384 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1914466384
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2665194440
Short name T126
Test name
Test status
Simulation time 4157212118 ps
CPU time 6.85 seconds
Started Sep 09 05:08:34 AM UTC 24
Finished Sep 09 05:08:42 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665194440 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.2665194440
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1125838261
Short name T816
Test name
Test status
Simulation time 511982838 ps
CPU time 3.05 seconds
Started Sep 09 05:08:31 AM UTC 24
Finished Sep 09 05:08:35 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125838261 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1125838261
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.933926375
Short name T822
Test name
Test status
Simulation time 9155944545 ps
CPU time 8.2 seconds
Started Sep 09 05:08:31 AM UTC 24
Finished Sep 09 05:08:40 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933926375 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.933926375
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2068045925
Short name T824
Test name
Test status
Simulation time 494734654 ps
CPU time 3.38 seconds
Started Sep 09 05:08:36 AM UTC 24
Finished Sep 09 05:08:41 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2068045925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs
r_mem_rw_with_rand_reset.2068045925
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3402768031
Short name T821
Test name
Test status
Simulation time 502273257 ps
CPU time 1.71 seconds
Started Sep 09 05:08:36 AM UTC 24
Finished Sep 09 05:08:39 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402768031 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3402768031
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.816583068
Short name T825
Test name
Test status
Simulation time 514849387 ps
CPU time 3.66 seconds
Started Sep 09 05:08:36 AM UTC 24
Finished Sep 09 05:08:41 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816583068 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.816583068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4019016216
Short name T830
Test name
Test status
Simulation time 4909920997 ps
CPU time 7.56 seconds
Started Sep 09 05:08:36 AM UTC 24
Finished Sep 09 05:08:45 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019016216 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.4019016216
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3214928198
Short name T823
Test name
Test status
Simulation time 822983977 ps
CPU time 4.17 seconds
Started Sep 09 05:08:35 AM UTC 24
Finished Sep 09 05:08:40 AM UTC 24
Peak memory 221444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214928198 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3214928198
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1873640479
Short name T837
Test name
Test status
Simulation time 4887432533 ps
CPU time 13.07 seconds
Started Sep 09 05:08:36 AM UTC 24
Finished Sep 09 05:08:50 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873640479 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.1873640479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1596287510
Short name T829
Test name
Test status
Simulation time 597172832 ps
CPU time 1.51 seconds
Started Sep 09 05:08:42 AM UTC 24
Finished Sep 09 05:08:45 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1596287510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs
r_mem_rw_with_rand_reset.1596287510
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3196885514
Short name T119
Test name
Test status
Simulation time 387332694 ps
CPU time 1.65 seconds
Started Sep 09 05:08:41 AM UTC 24
Finished Sep 09 05:08:43 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196885514 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3196885514
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2193823364
Short name T828
Test name
Test status
Simulation time 438962733 ps
CPU time 2.94 seconds
Started Sep 09 05:08:40 AM UTC 24
Finished Sep 09 05:08:44 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193823364 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2193823364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2154520837
Short name T845
Test name
Test status
Simulation time 2426647615 ps
CPU time 12.61 seconds
Started Sep 09 05:08:42 AM UTC 24
Finished Sep 09 05:08:56 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154520837 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.2154520837
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.215880408
Short name T826
Test name
Test status
Simulation time 708014216 ps
CPU time 2.91 seconds
Started Sep 09 05:08:37 AM UTC 24
Finished Sep 09 05:08:41 AM UTC 24
Peak memory 211576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215880408 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.215880408
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2393805861
Short name T82
Test name
Test status
Simulation time 8696466026 ps
CPU time 7.14 seconds
Started Sep 09 05:08:39 AM UTC 24
Finished Sep 09 05:08:48 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393805861 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.2393805861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1311385219
Short name T18
Test name
Test status
Simulation time 206982042483 ps
CPU time 138.57 seconds
Started Sep 09 05:19:05 AM UTC 24
Finished Sep 09 05:21:26 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311385219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1311385219
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2352470715
Short name T15
Test name
Test status
Simulation time 168581028174 ps
CPU time 108.39 seconds
Started Sep 09 05:19:04 AM UTC 24
Finished Sep 09 05:20:54 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352470715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2352470715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.3248508208
Short name T204
Test name
Test status
Simulation time 334049584330 ps
CPU time 468.09 seconds
Started Sep 09 05:19:04 AM UTC 24
Finished Sep 09 05:26:57 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248508208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.3248508208
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.1856884554
Short name T144
Test name
Test status
Simulation time 370927637369 ps
CPU time 646.64 seconds
Started Sep 09 05:19:05 AM UTC 24
Finished Sep 09 05:30:00 AM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856884554 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.1856884554
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2880735004
Short name T432
Test name
Test status
Simulation time 596782399062 ps
CPU time 1258.53 seconds
Started Sep 09 05:19:05 AM UTC 24
Finished Sep 09 05:40:16 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880735004 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.2880735004
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.2662878823
Short name T10
Test name
Test status
Simulation time 29503653508 ps
CPU time 20.82 seconds
Started Sep 09 05:19:05 AM UTC 24
Finished Sep 09 05:19:27 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662878823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2662878823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.3857132745
Short name T3
Test name
Test status
Simulation time 4961008031 ps
CPU time 8.51 seconds
Started Sep 09 05:19:05 AM UTC 24
Finished Sep 09 05:19:15 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857132745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3857132745
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.3961887266
Short name T4
Test name
Test status
Simulation time 5606501357 ps
CPU time 13.05 seconds
Started Sep 09 05:19:04 AM UTC 24
Finished Sep 09 05:19:18 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961887266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3961887266
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.346986819
Short name T258
Test name
Test status
Simulation time 496826452871 ps
CPU time 1046.85 seconds
Started Sep 09 05:19:07 AM UTC 24
Finished Sep 09 05:36:44 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346986819 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.346986819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.281113775
Short name T21
Test name
Test status
Simulation time 446825652 ps
CPU time 1.21 seconds
Started Sep 09 05:19:16 AM UTC 24
Finished Sep 09 05:19:18 AM UTC 24
Peak memory 209464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281113775 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.281113775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.884943061
Short name T131
Test name
Test status
Simulation time 191357219094 ps
CPU time 583.4 seconds
Started Sep 09 05:19:12 AM UTC 24
Finished Sep 09 05:29:02 AM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884943061 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.884943061
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1553596025
Short name T49
Test name
Test status
Simulation time 165860911078 ps
CPU time 252.12 seconds
Started Sep 09 05:19:12 AM UTC 24
Finished Sep 09 05:23:28 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553596025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1553596025
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.2830782387
Short name T150
Test name
Test status
Simulation time 334064391882 ps
CPU time 900.15 seconds
Started Sep 09 05:19:09 AM UTC 24
Finished Sep 09 05:34:18 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830782387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2830782387
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3911800409
Short name T85
Test name
Test status
Simulation time 160790936294 ps
CPU time 211.94 seconds
Started Sep 09 05:19:09 AM UTC 24
Finished Sep 09 05:22:44 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911800409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.3911800409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.1142712245
Short name T230
Test name
Test status
Simulation time 161782430581 ps
CPU time 345.73 seconds
Started Sep 09 05:19:08 AM UTC 24
Finished Sep 09 05:24:58 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142712245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1142712245
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.1174041283
Short name T13
Test name
Test status
Simulation time 331116324413 ps
CPU time 68.93 seconds
Started Sep 09 05:19:08 AM UTC 24
Finished Sep 09 05:20:19 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174041283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.1174041283
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2301557883
Short name T267
Test name
Test status
Simulation time 357059788992 ps
CPU time 1205.15 seconds
Started Sep 09 05:19:09 AM UTC 24
Finished Sep 09 05:39:27 AM UTC 24
Peak memory 212748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301557883 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.2301557883
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.2657490638
Short name T56
Test name
Test status
Simulation time 38102810708 ps
CPU time 25.27 seconds
Started Sep 09 05:19:13 AM UTC 24
Finished Sep 09 05:19:40 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657490638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2657490638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.478149797
Short name T11
Test name
Test status
Simulation time 4105287012 ps
CPU time 14.81 seconds
Started Sep 09 05:19:12 AM UTC 24
Finished Sep 09 05:19:28 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478149797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.478149797
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3997655559
Short name T23
Test name
Test status
Simulation time 4551162150 ps
CPU time 20.94 seconds
Started Sep 09 05:19:13 AM UTC 24
Finished Sep 09 05:19:36 AM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997655559 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3997655559
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.2315197688
Short name T12
Test name
Test status
Simulation time 6011976764 ps
CPU time 19.62 seconds
Started Sep 09 05:19:08 AM UTC 24
Finished Sep 09 05:19:29 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315197688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2315197688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.513142339
Short name T9
Test name
Test status
Simulation time 17062644733 ps
CPU time 7.52 seconds
Started Sep 09 05:19:13 AM UTC 24
Finished Sep 09 05:19:22 AM UTC 24
Peak memory 221664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=513142339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.adc_ctrl_stress_all_with_rand_reset.513142339
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.1052586740
Short name T398
Test name
Test status
Simulation time 409696011 ps
CPU time 1.09 seconds
Started Sep 09 05:30:47 AM UTC 24
Finished Sep 09 05:30:49 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052586740 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1052586740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2715210798
Short name T259
Test name
Test status
Simulation time 182249575467 ps
CPU time 67.51 seconds
Started Sep 09 05:30:00 AM UTC 24
Finished Sep 09 05:31:10 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715210798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2715210798
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.2534204813
Short name T145
Test name
Test status
Simulation time 162268104916 ps
CPU time 36.49 seconds
Started Sep 09 05:29:30 AM UTC 24
Finished Sep 09 05:30:08 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534204813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2534204813
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.533203429
Short name T409
Test name
Test status
Simulation time 477821179720 ps
CPU time 330.67 seconds
Started Sep 09 05:29:31 AM UTC 24
Finished Sep 09 05:35:06 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533203429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.533203429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2692085559
Short name T457
Test name
Test status
Simulation time 326148370600 ps
CPU time 885.71 seconds
Started Sep 09 05:29:25 AM UTC 24
Finished Sep 09 05:44:19 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692085559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2692085559
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.850404152
Short name T170
Test name
Test status
Simulation time 485626270978 ps
CPU time 310.43 seconds
Started Sep 09 05:29:27 AM UTC 24
Finished Sep 09 05:34:41 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850404152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.850404152
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.4030769516
Short name T232
Test name
Test status
Simulation time 562313414482 ps
CPU time 612.15 seconds
Started Sep 09 05:29:31 AM UTC 24
Finished Sep 09 05:39:50 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030769516 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.4030769516
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3315763380
Short name T467
Test name
Test status
Simulation time 600730109513 ps
CPU time 982.4 seconds
Started Sep 09 05:29:41 AM UTC 24
Finished Sep 09 05:46:14 AM UTC 24
Peak memory 212568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315763380 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.3315763380
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.2894783364
Short name T208
Test name
Test status
Simulation time 106378404153 ps
CPU time 372.07 seconds
Started Sep 09 05:30:38 AM UTC 24
Finished Sep 09 05:36:53 AM UTC 24
Peak memory 211816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894783364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2894783364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1365142017
Short name T397
Test name
Test status
Simulation time 24637079497 ps
CPU time 16.4 seconds
Started Sep 09 05:30:29 AM UTC 24
Finished Sep 09 05:30:46 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365142017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1365142017
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.679697734
Short name T394
Test name
Test status
Simulation time 4295422624 ps
CPU time 18.64 seconds
Started Sep 09 05:30:09 AM UTC 24
Finished Sep 09 05:30:28 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679697734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.679697734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.2055832937
Short name T392
Test name
Test status
Simulation time 5561786851 ps
CPU time 6.97 seconds
Started Sep 09 05:29:21 AM UTC 24
Finished Sep 09 05:29:29 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055832937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2055832937
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3958652437
Short name T46
Test name
Test status
Simulation time 1223595172 ps
CPU time 8.09 seconds
Started Sep 09 05:30:40 AM UTC 24
Finished Sep 09 05:30:49 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3958652437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.adc_ctrl_stress_all_with_rand_reset.3958652437
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.2144233263
Short name T400
Test name
Test status
Simulation time 404540206 ps
CPU time 2.39 seconds
Started Sep 09 05:32:28 AM UTC 24
Finished Sep 09 05:32:31 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144233263 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2144233263
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1305207830
Short name T161
Test name
Test status
Simulation time 554325814718 ps
CPU time 167.33 seconds
Started Sep 09 05:31:44 AM UTC 24
Finished Sep 09 05:34:33 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305207830 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.1305207830
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3115072572
Short name T242
Test name
Test status
Simulation time 328119623297 ps
CPU time 418.59 seconds
Started Sep 09 05:31:45 AM UTC 24
Finished Sep 09 05:38:48 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115072572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3115072572
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.1027745683
Short name T253
Test name
Test status
Simulation time 165621558825 ps
CPU time 233.97 seconds
Started Sep 09 05:31:11 AM UTC 24
Finished Sep 09 05:35:09 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027745683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1027745683
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3527097378
Short name T160
Test name
Test status
Simulation time 327453079213 ps
CPU time 173.15 seconds
Started Sep 09 05:31:17 AM UTC 24
Finished Sep 09 05:34:13 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527097378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.3527097378
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2238025390
Short name T291
Test name
Test status
Simulation time 329116264841 ps
CPU time 796.55 seconds
Started Sep 09 05:30:50 AM UTC 24
Finished Sep 09 05:44:14 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238025390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2238025390
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.1745966215
Short name T419
Test name
Test status
Simulation time 322597134132 ps
CPU time 360.13 seconds
Started Sep 09 05:30:52 AM UTC 24
Finished Sep 09 05:36:57 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745966215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.1745966215
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3095130194
Short name T445
Test name
Test status
Simulation time 203571609798 ps
CPU time 621.83 seconds
Started Sep 09 05:31:36 AM UTC 24
Finished Sep 09 05:42:05 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095130194 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.3095130194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1858950091
Short name T209
Test name
Test status
Simulation time 104724754145 ps
CPU time 592.33 seconds
Started Sep 09 05:32:13 AM UTC 24
Finished Sep 09 05:42:11 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858950091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1858950091
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.1777207700
Short name T403
Test name
Test status
Simulation time 39968984293 ps
CPU time 77.99 seconds
Started Sep 09 05:32:06 AM UTC 24
Finished Sep 09 05:33:25 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777207700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1777207700
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.2507236051
Short name T187
Test name
Test status
Simulation time 5052178575 ps
CPU time 21.86 seconds
Started Sep 09 05:32:05 AM UTC 24
Finished Sep 09 05:32:28 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507236051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2507236051
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.4064315751
Short name T399
Test name
Test status
Simulation time 5774298492 ps
CPU time 25.53 seconds
Started Sep 09 05:30:50 AM UTC 24
Finished Sep 09 05:31:17 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064315751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4064315751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.480952294
Short name T27
Test name
Test status
Simulation time 165581960913 ps
CPU time 35.91 seconds
Started Sep 09 05:32:13 AM UTC 24
Finished Sep 09 05:32:50 AM UTC 24
Peak memory 222008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=480952294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
11.adc_ctrl_stress_all_with_rand_reset.480952294
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.920760787
Short name T407
Test name
Test status
Simulation time 471408108 ps
CPU time 1.04 seconds
Started Sep 09 05:34:09 AM UTC 24
Finished Sep 09 05:34:11 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920760787 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.920760787
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.621443777
Short name T294
Test name
Test status
Simulation time 344666464756 ps
CPU time 789.45 seconds
Started Sep 09 05:33:27 AM UTC 24
Finished Sep 09 05:46:44 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621443777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.621443777
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.795912185
Short name T483
Test name
Test status
Simulation time 331021134467 ps
CPU time 930.03 seconds
Started Sep 09 05:32:51 AM UTC 24
Finished Sep 09 05:48:31 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795912185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.795912185
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.2835885103
Short name T171
Test name
Test status
Simulation time 496263722333 ps
CPU time 181.1 seconds
Started Sep 09 05:32:32 AM UTC 24
Finished Sep 09 05:35:36 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835885103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.2835885103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3043177087
Short name T415
Test name
Test status
Simulation time 190035073826 ps
CPU time 186.21 seconds
Started Sep 09 05:33:08 AM UTC 24
Finished Sep 09 05:36:17 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043177087 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.3043177087
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.2045817829
Short name T406
Test name
Test status
Simulation time 30726804041 ps
CPU time 30.49 seconds
Started Sep 09 05:33:33 AM UTC 24
Finished Sep 09 05:34:05 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045817829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2045817829
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.3430871237
Short name T404
Test name
Test status
Simulation time 4203639132 ps
CPU time 4.24 seconds
Started Sep 09 05:33:27 AM UTC 24
Finished Sep 09 05:33:32 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430871237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3430871237
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.2671783514
Short name T401
Test name
Test status
Simulation time 6159337449 ps
CPU time 26.91 seconds
Started Sep 09 05:32:30 AM UTC 24
Finished Sep 09 05:32:58 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671783514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2671783514
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1422621946
Short name T375
Test name
Test status
Simulation time 13088426020 ps
CPU time 7.27 seconds
Started Sep 09 05:34:00 AM UTC 24
Finished Sep 09 05:34:08 AM UTC 24
Peak memory 221732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1422621946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.adc_ctrl_stress_all_with_rand_reset.1422621946
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.4086578569
Short name T412
Test name
Test status
Simulation time 358223715 ps
CPU time 1.02 seconds
Started Sep 09 05:36:03 AM UTC 24
Finished Sep 09 05:36:05 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086578569 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4086578569
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.663283862
Short name T553
Test name
Test status
Simulation time 491554632506 ps
CPU time 1497.54 seconds
Started Sep 09 05:34:35 AM UTC 24
Finished Sep 09 05:59:49 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663283862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.663283862
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.2436903375
Short name T489
Test name
Test status
Simulation time 323364926421 ps
CPU time 905.6 seconds
Started Sep 09 05:34:14 AM UTC 24
Finished Sep 09 05:49:29 AM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436903375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2436903375
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.579381727
Short name T440
Test name
Test status
Simulation time 167228500689 ps
CPU time 424.54 seconds
Started Sep 09 05:34:18 AM UTC 24
Finished Sep 09 05:41:28 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579381727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.579381727
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.1124278081
Short name T308
Test name
Test status
Simulation time 206763867834 ps
CPU time 764.78 seconds
Started Sep 09 05:34:42 AM UTC 24
Finished Sep 09 05:47:35 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124278081 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.1124278081
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1598182359
Short name T435
Test name
Test status
Simulation time 401878911313 ps
CPU time 344.13 seconds
Started Sep 09 05:34:46 AM UTC 24
Finished Sep 09 05:40:34 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598182359 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.1598182359
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.4271491235
Short name T212
Test name
Test status
Simulation time 118790826943 ps
CPU time 576.53 seconds
Started Sep 09 05:35:37 AM UTC 24
Finished Sep 09 05:45:20 AM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271491235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4271491235
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.611935632
Short name T414
Test name
Test status
Simulation time 40341725746 ps
CPU time 43.81 seconds
Started Sep 09 05:35:30 AM UTC 24
Finished Sep 09 05:36:15 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611935632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.611935632
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3336550246
Short name T410
Test name
Test status
Simulation time 4779413086 ps
CPU time 19.69 seconds
Started Sep 09 05:35:09 AM UTC 24
Finished Sep 09 05:35:30 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336550246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3336550246
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2513105988
Short name T408
Test name
Test status
Simulation time 5869367629 ps
CPU time 7.57 seconds
Started Sep 09 05:34:12 AM UTC 24
Finished Sep 09 05:34:21 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513105988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2513105988
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3604046469
Short name T411
Test name
Test status
Simulation time 1631052630 ps
CPU time 7.78 seconds
Started Sep 09 05:35:40 AM UTC 24
Finished Sep 09 05:35:49 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3604046469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.adc_ctrl_stress_all_with_rand_reset.3604046469
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.4229768400
Short name T421
Test name
Test status
Simulation time 295001249 ps
CPU time 2.08 seconds
Started Sep 09 05:37:00 AM UTC 24
Finished Sep 09 05:37:03 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229768400 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4229768400
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.1955121283
Short name T330
Test name
Test status
Simulation time 329270420621 ps
CPU time 913.2 seconds
Started Sep 09 05:36:35 AM UTC 24
Finished Sep 09 05:51:59 AM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955121283 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.1955121283
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3682654333
Short name T536
Test name
Test status
Simulation time 489426060037 ps
CPU time 1292.27 seconds
Started Sep 09 05:36:16 AM UTC 24
Finished Sep 09 05:58:01 AM UTC 24
Peak memory 212584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682654333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.3682654333
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.2493028639
Short name T226
Test name
Test status
Simulation time 330817997203 ps
CPU time 894.46 seconds
Started Sep 09 05:36:07 AM UTC 24
Finished Sep 09 05:51:10 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493028639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2493028639
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.4009169256
Short name T424
Test name
Test status
Simulation time 163770591111 ps
CPU time 146.01 seconds
Started Sep 09 05:36:14 AM UTC 24
Finished Sep 09 05:38:42 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009169256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.4009169256
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2388160128
Short name T274
Test name
Test status
Simulation time 206309921305 ps
CPU time 227.93 seconds
Started Sep 09 05:36:18 AM UTC 24
Finished Sep 09 05:40:09 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388160128 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.2388160128
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1684975688
Short name T418
Test name
Test status
Simulation time 197104306391 ps
CPU time 25.77 seconds
Started Sep 09 05:36:25 AM UTC 24
Finished Sep 09 05:36:52 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684975688 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.1684975688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.2998111480
Short name T423
Test name
Test status
Simulation time 41911296417 ps
CPU time 93.9 seconds
Started Sep 09 05:36:52 AM UTC 24
Finished Sep 09 05:38:28 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998111480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2998111480
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.852755820
Short name T420
Test name
Test status
Simulation time 4618839153 ps
CPU time 11.05 seconds
Started Sep 09 05:36:46 AM UTC 24
Finished Sep 09 05:36:58 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852755820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.852755820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.3697855136
Short name T413
Test name
Test status
Simulation time 5715547753 ps
CPU time 6.54 seconds
Started Sep 09 05:36:05 AM UTC 24
Finished Sep 09 05:36:13 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697855136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3697855136
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.3628910598
Short name T544
Test name
Test status
Simulation time 329994943208 ps
CPU time 1290.38 seconds
Started Sep 09 05:36:58 AM UTC 24
Finished Sep 09 05:58:40 AM UTC 24
Peak memory 212868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628910598 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.3628910598
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.59599973
Short name T428
Test name
Test status
Simulation time 411837344 ps
CPU time 2.53 seconds
Started Sep 09 05:39:19 AM UTC 24
Finished Sep 09 05:39:23 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59599973 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.59599973
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1128060635
Short name T271
Test name
Test status
Simulation time 341718961857 ps
CPU time 171.41 seconds
Started Sep 09 05:38:28 AM UTC 24
Finished Sep 09 05:41:22 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128060635 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.1128060635
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.1640774577
Short name T249
Test name
Test status
Simulation time 164364615665 ps
CPU time 229.65 seconds
Started Sep 09 05:37:18 AM UTC 24
Finished Sep 09 05:41:11 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640774577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1640774577
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4046378343
Short name T442
Test name
Test status
Simulation time 328260095485 ps
CPU time 240 seconds
Started Sep 09 05:37:34 AM UTC 24
Finished Sep 09 05:41:37 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046378343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.4046378343
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.172591664
Short name T166
Test name
Test status
Simulation time 163299023152 ps
CPU time 497.19 seconds
Started Sep 09 05:37:14 AM UTC 24
Finished Sep 09 05:45:36 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172591664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.172591664
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.211666490
Short name T504
Test name
Test status
Simulation time 326084031824 ps
CPU time 956.2 seconds
Started Sep 09 05:37:15 AM UTC 24
Finished Sep 09 05:53:21 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211666490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.211666490
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.3177565129
Short name T366
Test name
Test status
Simulation time 180960781355 ps
CPU time 116.7 seconds
Started Sep 09 05:38:06 AM UTC 24
Finished Sep 09 05:40:05 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177565129 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.3177565129
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1054284512
Short name T519
Test name
Test status
Simulation time 400023629653 ps
CPU time 991.27 seconds
Started Sep 09 05:38:19 AM UTC 24
Finished Sep 09 05:55:00 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054284512 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.1054284512
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.2183167547
Short name T465
Test name
Test status
Simulation time 102023889054 ps
CPU time 410.38 seconds
Started Sep 09 05:39:07 AM UTC 24
Finished Sep 09 05:46:01 AM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183167547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2183167547
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.1661061202
Short name T429
Test name
Test status
Simulation time 42168669983 ps
CPU time 38.02 seconds
Started Sep 09 05:38:49 AM UTC 24
Finished Sep 09 05:39:28 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661061202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1661061202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1636448888
Short name T426
Test name
Test status
Simulation time 5233363833 ps
CPU time 23.06 seconds
Started Sep 09 05:38:43 AM UTC 24
Finished Sep 09 05:39:07 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636448888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1636448888
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.3144471523
Short name T422
Test name
Test status
Simulation time 5546220127 ps
CPU time 12.2 seconds
Started Sep 09 05:37:04 AM UTC 24
Finished Sep 09 05:37:17 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144471523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3144471523
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.660093624
Short name T363
Test name
Test status
Simulation time 181162649064 ps
CPU time 215.98 seconds
Started Sep 09 05:39:08 AM UTC 24
Finished Sep 09 05:42:47 AM UTC 24
Peak memory 211660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660093624 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.660093624
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1667085644
Short name T427
Test name
Test status
Simulation time 2414174892 ps
CPU time 9.44 seconds
Started Sep 09 05:39:08 AM UTC 24
Finished Sep 09 05:39:18 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1667085644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.adc_ctrl_stress_all_with_rand_reset.1667085644
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1930910085
Short name T434
Test name
Test status
Simulation time 530969316 ps
CPU time 2.98 seconds
Started Sep 09 05:40:27 AM UTC 24
Finished Sep 09 05:40:31 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930910085 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1930910085
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.865866477
Short name T255
Test name
Test status
Simulation time 335950267420 ps
CPU time 482.39 seconds
Started Sep 09 05:39:53 AM UTC 24
Finished Sep 09 05:48:01 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865866477 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.865866477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2284757113
Short name T280
Test name
Test status
Simulation time 161630476234 ps
CPU time 164.39 seconds
Started Sep 09 05:39:34 AM UTC 24
Finished Sep 09 05:42:22 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284757113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2284757113
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2166993286
Short name T449
Test name
Test status
Simulation time 328831458827 ps
CPU time 203.05 seconds
Started Sep 09 05:39:34 AM UTC 24
Finished Sep 09 05:43:00 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166993286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.2166993286
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1689408419
Short name T439
Test name
Test status
Simulation time 165508086130 ps
CPU time 110.71 seconds
Started Sep 09 05:39:27 AM UTC 24
Finished Sep 09 05:41:20 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689408419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1689408419
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.429302671
Short name T493
Test name
Test status
Simulation time 488016582325 ps
CPU time 670.11 seconds
Started Sep 09 05:39:29 AM UTC 24
Finished Sep 09 05:50:47 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429302671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.429302671
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1198802666
Short name T494
Test name
Test status
Simulation time 207559004319 ps
CPU time 648.84 seconds
Started Sep 09 05:39:50 AM UTC 24
Finished Sep 09 05:50:47 AM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198802666 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.1198802666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.2690505257
Short name T436
Test name
Test status
Simulation time 30651022991 ps
CPU time 25.57 seconds
Started Sep 09 05:40:10 AM UTC 24
Finished Sep 09 05:40:37 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690505257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2690505257
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.3573162759
Short name T433
Test name
Test status
Simulation time 4712743476 ps
CPU time 13.63 seconds
Started Sep 09 05:40:06 AM UTC 24
Finished Sep 09 05:40:20 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573162759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3573162759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1059927769
Short name T431
Test name
Test status
Simulation time 5834443718 ps
CPU time 27.62 seconds
Started Sep 09 05:39:23 AM UTC 24
Finished Sep 09 05:39:52 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059927769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1059927769
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.4046169742
Short name T305
Test name
Test status
Simulation time 221344519969 ps
CPU time 117.15 seconds
Started Sep 09 05:40:21 AM UTC 24
Finished Sep 09 05:42:20 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046169742 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.4046169742
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.1105626889
Short name T443
Test name
Test status
Simulation time 344057255 ps
CPU time 2.36 seconds
Started Sep 09 05:41:57 AM UTC 24
Finished Sep 09 05:42:01 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105626889 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1105626889
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.4055908807
Short name T335
Test name
Test status
Simulation time 496699441586 ps
CPU time 757.61 seconds
Started Sep 09 05:41:21 AM UTC 24
Finished Sep 09 05:54:06 AM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055908807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4055908807
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1152509660
Short name T451
Test name
Test status
Simulation time 334431532287 ps
CPU time 147.49 seconds
Started Sep 09 05:40:37 AM UTC 24
Finished Sep 09 05:43:07 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152509660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.1152509660
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.3541961467
Short name T461
Test name
Test status
Simulation time 164423764551 ps
CPU time 282.64 seconds
Started Sep 09 05:40:32 AM UTC 24
Finished Sep 09 05:45:18 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541961467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3541961467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.3188433287
Short name T474
Test name
Test status
Simulation time 326441328007 ps
CPU time 421.61 seconds
Started Sep 09 05:40:32 AM UTC 24
Finished Sep 09 05:47:38 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188433287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.3188433287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.2904451653
Short name T302
Test name
Test status
Simulation time 175670482089 ps
CPU time 135.24 seconds
Started Sep 09 05:40:38 AM UTC 24
Finished Sep 09 05:42:56 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904451653 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.2904451653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.116262505
Short name T468
Test name
Test status
Simulation time 608461445390 ps
CPU time 333.63 seconds
Started Sep 09 05:40:44 AM UTC 24
Finished Sep 09 05:46:22 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116262505 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.116262505
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.1986345742
Short name T99
Test name
Test status
Simulation time 100264916506 ps
CPU time 478.92 seconds
Started Sep 09 05:41:30 AM UTC 24
Finished Sep 09 05:49:34 AM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986345742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1986345742
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1792151428
Short name T447
Test name
Test status
Simulation time 32371797629 ps
CPU time 72.58 seconds
Started Sep 09 05:41:29 AM UTC 24
Finished Sep 09 05:42:43 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792151428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1792151428
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.1871113865
Short name T441
Test name
Test status
Simulation time 4981148654 ps
CPU time 4.89 seconds
Started Sep 09 05:41:23 AM UTC 24
Finished Sep 09 05:41:29 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871113865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1871113865
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.340283743
Short name T437
Test name
Test status
Simulation time 5989605282 ps
CPU time 4.16 seconds
Started Sep 09 05:40:32 AM UTC 24
Finished Sep 09 05:40:37 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340283743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.340283743
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.1219327341
Short name T301
Test name
Test status
Simulation time 172963233748 ps
CPU time 171.3 seconds
Started Sep 09 05:41:38 AM UTC 24
Finished Sep 09 05:44:32 AM UTC 24
Peak memory 211724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219327341 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.1219327341
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3224329424
Short name T28
Test name
Test status
Simulation time 32471049110 ps
CPU time 38.17 seconds
Started Sep 09 05:41:37 AM UTC 24
Finished Sep 09 05:42:17 AM UTC 24
Peak memory 221668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3224329424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.adc_ctrl_stress_all_with_rand_reset.3224329424
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.2387063153
Short name T450
Test name
Test status
Simulation time 422761322 ps
CPU time 1.75 seconds
Started Sep 09 05:43:01 AM UTC 24
Finished Sep 09 05:43:04 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387063153 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2387063153
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3318705202
Short name T287
Test name
Test status
Simulation time 357202800448 ps
CPU time 169.52 seconds
Started Sep 09 05:42:23 AM UTC 24
Finished Sep 09 05:45:15 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318705202 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.3318705202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.167028342
Short name T256
Test name
Test status
Simulation time 169602039057 ps
CPU time 123.27 seconds
Started Sep 09 05:42:41 AM UTC 24
Finished Sep 09 05:44:46 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167028342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.167028342
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.3990667295
Short name T282
Test name
Test status
Simulation time 497060311410 ps
CPU time 978.55 seconds
Started Sep 09 05:42:06 AM UTC 24
Finished Sep 09 05:58:35 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990667295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3990667295
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1619430297
Short name T456
Test name
Test status
Simulation time 164800502820 ps
CPU time 123.22 seconds
Started Sep 09 05:42:12 AM UTC 24
Finished Sep 09 05:44:17 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619430297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.1619430297
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.1182715236
Short name T343
Test name
Test status
Simulation time 329001001582 ps
CPU time 209.59 seconds
Started Sep 09 05:42:01 AM UTC 24
Finished Sep 09 05:45:34 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182715236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1182715236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.1895151625
Short name T453
Test name
Test status
Simulation time 320880751575 ps
CPU time 95.48 seconds
Started Sep 09 05:42:04 AM UTC 24
Finished Sep 09 05:43:42 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895151625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.1895151625
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.3294002917
Short name T278
Test name
Test status
Simulation time 540440176242 ps
CPU time 729.14 seconds
Started Sep 09 05:42:18 AM UTC 24
Finished Sep 09 05:54:34 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294002917 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.3294002917
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2725366899
Short name T526
Test name
Test status
Simulation time 614868069151 ps
CPU time 837.9 seconds
Started Sep 09 05:42:21 AM UTC 24
Finished Sep 09 05:56:27 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725366899 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.2725366899
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.2832200288
Short name T223
Test name
Test status
Simulation time 69384201601 ps
CPU time 250.48 seconds
Started Sep 09 05:42:56 AM UTC 24
Finished Sep 09 05:47:09 AM UTC 24
Peak memory 212032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832200288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2832200288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.2246861755
Short name T455
Test name
Test status
Simulation time 25399352963 ps
CPU time 79.98 seconds
Started Sep 09 05:42:48 AM UTC 24
Finished Sep 09 05:44:10 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246861755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2246861755
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.3492721084
Short name T448
Test name
Test status
Simulation time 5021396259 ps
CPU time 10.81 seconds
Started Sep 09 05:42:44 AM UTC 24
Finished Sep 09 05:42:56 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492721084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3492721084
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2112910092
Short name T444
Test name
Test status
Simulation time 5866222949 ps
CPU time 3.61 seconds
Started Sep 09 05:41:59 AM UTC 24
Finished Sep 09 05:42:04 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112910092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2112910092
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.2189062181
Short name T359
Test name
Test status
Simulation time 358324405451 ps
CPU time 901.02 seconds
Started Sep 09 05:43:00 AM UTC 24
Finished Sep 09 05:58:10 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189062181 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.2189062181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2526763178
Short name T29
Test name
Test status
Simulation time 2797758452 ps
CPU time 12.39 seconds
Started Sep 09 05:42:57 AM UTC 24
Finished Sep 09 05:43:11 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2526763178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.adc_ctrl_stress_all_with_rand_reset.2526763178
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.451712130
Short name T458
Test name
Test status
Simulation time 401433773 ps
CPU time 1.98 seconds
Started Sep 09 05:44:18 AM UTC 24
Finished Sep 09 05:44:21 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451712130 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.451712130
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.1245264513
Short name T103
Test name
Test status
Simulation time 163766253966 ps
CPU time 369.22 seconds
Started Sep 09 05:43:35 AM UTC 24
Finished Sep 09 05:49:49 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245264513 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.1245264513
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.3648367374
Short name T488
Test name
Test status
Simulation time 162472623438 ps
CPU time 375.17 seconds
Started Sep 09 05:43:08 AM UTC 24
Finished Sep 09 05:49:27 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648367374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3648367374
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3725810412
Short name T482
Test name
Test status
Simulation time 165478991780 ps
CPU time 302.47 seconds
Started Sep 09 05:43:12 AM UTC 24
Finished Sep 09 05:48:18 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725810412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.3725810412
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.3887217292
Short name T319
Test name
Test status
Simulation time 164877015025 ps
CPU time 64.43 seconds
Started Sep 09 05:43:05 AM UTC 24
Finished Sep 09 05:44:11 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887217292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3887217292
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.1401723225
Short name T469
Test name
Test status
Simulation time 325262880907 ps
CPU time 220.71 seconds
Started Sep 09 05:43:05 AM UTC 24
Finished Sep 09 05:46:48 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401723225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.1401723225
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.202556212
Short name T262
Test name
Test status
Simulation time 264114972156 ps
CPU time 261.67 seconds
Started Sep 09 05:43:27 AM UTC 24
Finished Sep 09 05:47:52 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202556212 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.202556212
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.663636068
Short name T472
Test name
Test status
Simulation time 409977826168 ps
CPU time 228.48 seconds
Started Sep 09 05:43:32 AM UTC 24
Finished Sep 09 05:47:23 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663636068 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.663636068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.2908054270
Short name T221
Test name
Test status
Simulation time 124613842753 ps
CPU time 644.43 seconds
Started Sep 09 05:44:10 AM UTC 24
Finished Sep 09 05:55:01 AM UTC 24
Peak memory 211824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908054270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2908054270
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.4093849574
Short name T459
Test name
Test status
Simulation time 41938667233 ps
CPU time 31.01 seconds
Started Sep 09 05:43:49 AM UTC 24
Finished Sep 09 05:44:22 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093849574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4093849574
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.3080254074
Short name T454
Test name
Test status
Simulation time 4975082983 ps
CPU time 5.23 seconds
Started Sep 09 05:43:42 AM UTC 24
Finished Sep 09 05:43:48 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080254074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3080254074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1580567954
Short name T452
Test name
Test status
Simulation time 5885385591 ps
CPU time 23.93 seconds
Started Sep 09 05:43:02 AM UTC 24
Finished Sep 09 05:43:27 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580567954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1580567954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.3663094232
Short name T92
Test name
Test status
Simulation time 521540554010 ps
CPU time 750.25 seconds
Started Sep 09 05:44:15 AM UTC 24
Finished Sep 09 05:56:54 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663094232 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.3663094232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.291318945
Short name T30
Test name
Test status
Simulation time 4298015879 ps
CPU time 9.85 seconds
Started Sep 09 05:44:11 AM UTC 24
Finished Sep 09 05:44:23 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=291318945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
19.adc_ctrl_stress_all_with_rand_reset.291318945
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.3773200008
Short name T42
Test name
Test status
Simulation time 330495445 ps
CPU time 2.49 seconds
Started Sep 09 05:19:36 AM UTC 24
Finished Sep 09 05:19:39 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773200008 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3773200008
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2001837390
Short name T189
Test name
Test status
Simulation time 326621149128 ps
CPU time 347.94 seconds
Started Sep 09 05:19:20 AM UTC 24
Finished Sep 09 05:25:12 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001837390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.2001837390
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.822759446
Short name T384
Test name
Test status
Simulation time 499431136499 ps
CPU time 491.49 seconds
Started Sep 09 05:19:20 AM UTC 24
Finished Sep 09 05:27:36 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822759446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.822759446
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.499226975
Short name T135
Test name
Test status
Simulation time 595222981863 ps
CPU time 406.85 seconds
Started Sep 09 05:19:22 AM UTC 24
Finished Sep 09 05:26:14 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499226975 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.499226975
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4043075132
Short name T130
Test name
Test status
Simulation time 597552934340 ps
CPU time 328.96 seconds
Started Sep 09 05:19:22 AM UTC 24
Finished Sep 09 05:24:55 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043075132 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.4043075132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.1439116233
Short name T55
Test name
Test status
Simulation time 85691346719 ps
CPU time 438.02 seconds
Started Sep 09 05:19:30 AM UTC 24
Finished Sep 09 05:26:53 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439116233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1439116233
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1520890319
Short name T142
Test name
Test status
Simulation time 25527148811 ps
CPU time 53.23 seconds
Started Sep 09 05:19:28 AM UTC 24
Finished Sep 09 05:20:23 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520890319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1520890319
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.24217586
Short name T22
Test name
Test status
Simulation time 3443575978 ps
CPU time 4.7 seconds
Started Sep 09 05:19:28 AM UTC 24
Finished Sep 09 05:19:34 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24217586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.24217586
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.177263009
Short name T47
Test name
Test status
Simulation time 7852158939 ps
CPU time 5.72 seconds
Started Sep 09 05:19:35 AM UTC 24
Finished Sep 09 05:19:41 AM UTC 24
Peak memory 243552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177263009 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.177263009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3330243276
Short name T8
Test name
Test status
Simulation time 5672505231 ps
CPU time 4.83 seconds
Started Sep 09 05:19:16 AM UTC 24
Finished Sep 09 05:19:22 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330243276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3330243276
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.2317614040
Short name T62
Test name
Test status
Simulation time 9629195194 ps
CPU time 39.38 seconds
Started Sep 09 05:19:33 AM UTC 24
Finished Sep 09 05:20:13 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317614040 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.2317614040
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.593875550
Short name T40
Test name
Test status
Simulation time 2759791739 ps
CPU time 15.32 seconds
Started Sep 09 05:19:30 AM UTC 24
Finished Sep 09 05:19:47 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=593875550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
2.adc_ctrl_stress_all_with_rand_reset.593875550
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.1533774156
Short name T463
Test name
Test status
Simulation time 398346025 ps
CPU time 2.06 seconds
Started Sep 09 05:45:35 AM UTC 24
Finished Sep 09 05:45:38 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533774156 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1533774156
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.3509644668
Short name T528
Test name
Test status
Simulation time 492013810894 ps
CPU time 763.08 seconds
Started Sep 09 05:44:23 AM UTC 24
Finished Sep 09 05:57:14 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509644668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3509644668
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2650736800
Short name T104
Test name
Test status
Simulation time 327239639686 ps
CPU time 334.43 seconds
Started Sep 09 05:44:23 AM UTC 24
Finished Sep 09 05:50:01 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650736800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.2650736800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.1105721148
Short name T602
Test name
Test status
Simulation time 490900073792 ps
CPU time 1432.11 seconds
Started Sep 09 05:44:21 AM UTC 24
Finished Sep 09 06:08:28 AM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105721148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1105721148
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.3729781913
Short name T575
Test name
Test status
Simulation time 490582637062 ps
CPU time 1171.33 seconds
Started Sep 09 05:44:22 AM UTC 24
Finished Sep 09 06:04:05 AM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729781913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.3729781913
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.446287214
Short name T512
Test name
Test status
Simulation time 192832517930 ps
CPU time 595.04 seconds
Started Sep 09 05:44:33 AM UTC 24
Finished Sep 09 05:54:35 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446287214 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.446287214
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.1129640379
Short name T90
Test name
Test status
Simulation time 129399180850 ps
CPU time 677.85 seconds
Started Sep 09 05:45:19 AM UTC 24
Finished Sep 09 05:56:44 AM UTC 24
Peak memory 212088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129640379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1129640379
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.3032506759
Short name T464
Test name
Test status
Simulation time 34277452854 ps
CPU time 34.31 seconds
Started Sep 09 05:45:19 AM UTC 24
Finished Sep 09 05:45:55 AM UTC 24
Peak memory 210852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032506759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3032506759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.104547130
Short name T462
Test name
Test status
Simulation time 3638828974 ps
CPU time 1.8 seconds
Started Sep 09 05:45:15 AM UTC 24
Finished Sep 09 05:45:19 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104547130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.104547130
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.1722368267
Short name T460
Test name
Test status
Simulation time 5903027667 ps
CPU time 5.41 seconds
Started Sep 09 05:44:19 AM UTC 24
Finished Sep 09 05:44:25 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722368267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1722368267
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.240249362
Short name T275
Test name
Test status
Simulation time 495393677153 ps
CPU time 319.42 seconds
Started Sep 09 05:45:33 AM UTC 24
Finished Sep 09 05:50:56 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240249362 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.240249362
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.274923616
Short name T471
Test name
Test status
Simulation time 502201006 ps
CPU time 1.58 seconds
Started Sep 09 05:47:02 AM UTC 24
Finished Sep 09 05:47:04 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274923616 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.274923616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.847619664
Short name T284
Test name
Test status
Simulation time 430905925993 ps
CPU time 1059.98 seconds
Started Sep 09 05:46:33 AM UTC 24
Finished Sep 09 06:04:24 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847619664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.847619664
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.740461177
Short name T254
Test name
Test status
Simulation time 159529658866 ps
CPU time 53.25 seconds
Started Sep 09 05:46:02 AM UTC 24
Finished Sep 09 05:46:57 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740461177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.740461177
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1204449288
Short name T105
Test name
Test status
Simulation time 327220307424 ps
CPU time 235.28 seconds
Started Sep 09 05:46:04 AM UTC 24
Finished Sep 09 05:50:02 AM UTC 24
Peak memory 211780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204449288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.1204449288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.771065181
Short name T485
Test name
Test status
Simulation time 327010904794 ps
CPU time 190.41 seconds
Started Sep 09 05:45:39 AM UTC 24
Finished Sep 09 05:48:52 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771065181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.771065181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.1884701222
Short name T476
Test name
Test status
Simulation time 330690235004 ps
CPU time 110.5 seconds
Started Sep 09 05:45:56 AM UTC 24
Finished Sep 09 05:47:48 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884701222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.1884701222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1706392134
Short name T478
Test name
Test status
Simulation time 403533611108 ps
CPU time 95.76 seconds
Started Sep 09 05:46:16 AM UTC 24
Finished Sep 09 05:47:54 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706392134 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.1706392134
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.1064292474
Short name T552
Test name
Test status
Simulation time 117987534926 ps
CPU time 772.16 seconds
Started Sep 09 05:46:48 AM UTC 24
Finished Sep 09 05:59:48 AM UTC 24
Peak memory 211824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064292474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1064292474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.2014883503
Short name T477
Test name
Test status
Simulation time 34620605061 ps
CPU time 66.59 seconds
Started Sep 09 05:46:44 AM UTC 24
Finished Sep 09 05:47:53 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014883503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2014883503
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.3935621935
Short name T470
Test name
Test status
Simulation time 4513938015 ps
CPU time 10.6 seconds
Started Sep 09 05:46:36 AM UTC 24
Finished Sep 09 05:46:48 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935621935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3935621935
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.2804727518
Short name T466
Test name
Test status
Simulation time 5788617703 ps
CPU time 24.49 seconds
Started Sep 09 05:45:38 AM UTC 24
Finished Sep 09 05:46:03 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804727518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2804727518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4100926894
Short name T370
Test name
Test status
Simulation time 8516864121 ps
CPU time 10.21 seconds
Started Sep 09 05:46:50 AM UTC 24
Finished Sep 09 05:47:01 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4100926894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.adc_ctrl_stress_all_with_rand_reset.4100926894
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.3752775281
Short name T480
Test name
Test status
Simulation time 391884581 ps
CPU time 1.26 seconds
Started Sep 09 05:47:59 AM UTC 24
Finished Sep 09 05:48:01 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752775281 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3752775281
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.2879038153
Short name T321
Test name
Test status
Simulation time 489989815687 ps
CPU time 592.33 seconds
Started Sep 09 05:47:39 AM UTC 24
Finished Sep 09 05:57:38 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879038153 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.2879038153
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.536428250
Short name T316
Test name
Test status
Simulation time 497832973675 ps
CPU time 89.55 seconds
Started Sep 09 05:47:28 AM UTC 24
Finished Sep 09 05:48:59 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536428250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.536428250
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3104977310
Short name T603
Test name
Test status
Simulation time 492723555505 ps
CPU time 1254.41 seconds
Started Sep 09 05:47:29 AM UTC 24
Finished Sep 09 06:08:35 AM UTC 24
Peak memory 212580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104977310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.3104977310
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.2402955956
Short name T568
Test name
Test status
Simulation time 323371751600 ps
CPU time 941.9 seconds
Started Sep 09 05:47:10 AM UTC 24
Finished Sep 09 06:03:01 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402955956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2402955956
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.475968071
Short name T522
Test name
Test status
Simulation time 168889313355 ps
CPU time 507.99 seconds
Started Sep 09 05:47:24 AM UTC 24
Finished Sep 09 05:55:58 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475968071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.475968071
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.822927993
Short name T106
Test name
Test status
Simulation time 202971210487 ps
CPU time 145.86 seconds
Started Sep 09 05:47:34 AM UTC 24
Finished Sep 09 05:50:02 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822927993 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.822927993
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3967633222
Short name T550
Test name
Test status
Simulation time 393457726385 ps
CPU time 721.76 seconds
Started Sep 09 05:47:36 AM UTC 24
Finished Sep 09 05:59:46 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967633222 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.3967633222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.175516744
Short name T376
Test name
Test status
Simulation time 128125453917 ps
CPU time 854.96 seconds
Started Sep 09 05:47:53 AM UTC 24
Finished Sep 09 06:02:16 AM UTC 24
Peak memory 212876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175516744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.175516744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.867450103
Short name T101
Test name
Test status
Simulation time 26564387886 ps
CPU time 108.95 seconds
Started Sep 09 05:47:53 AM UTC 24
Finished Sep 09 05:49:43 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867450103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.867450103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.4203995001
Short name T479
Test name
Test status
Simulation time 3469233735 ps
CPU time 7.3 seconds
Started Sep 09 05:47:49 AM UTC 24
Finished Sep 09 05:47:58 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203995001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.4203995001
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.3004400402
Short name T473
Test name
Test status
Simulation time 5950403647 ps
CPU time 27.48 seconds
Started Sep 09 05:47:05 AM UTC 24
Finished Sep 09 05:47:33 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004400402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3004400402
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.3747359527
Short name T310
Test name
Test status
Simulation time 333332493065 ps
CPU time 191.33 seconds
Started Sep 09 05:47:55 AM UTC 24
Finished Sep 09 05:51:09 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747359527 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.3747359527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3491598739
Short name T276
Test name
Test status
Simulation time 79292973948 ps
CPU time 19.46 seconds
Started Sep 09 05:47:54 AM UTC 24
Finished Sep 09 05:48:14 AM UTC 24
Peak memory 221660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3491598739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.adc_ctrl_stress_all_with_rand_reset.3491598739
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.3854617561
Short name T487
Test name
Test status
Simulation time 476908064 ps
CPU time 1.35 seconds
Started Sep 09 05:49:18 AM UTC 24
Finished Sep 09 05:49:20 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854617561 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3854617561
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.394292738
Short name T505
Test name
Test status
Simulation time 165379313813 ps
CPU time 282.83 seconds
Started Sep 09 05:48:36 AM UTC 24
Finished Sep 09 05:53:23 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394292738 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.394292738
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.752760147
Short name T240
Test name
Test status
Simulation time 328949509061 ps
CPU time 342 seconds
Started Sep 09 05:48:07 AM UTC 24
Finished Sep 09 05:53:53 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752760147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.752760147
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4064282857
Short name T601
Test name
Test status
Simulation time 492748156698 ps
CPU time 1197.01 seconds
Started Sep 09 05:48:15 AM UTC 24
Finished Sep 09 06:08:25 AM UTC 24
Peak memory 212584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064282857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.4064282857
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.2702539579
Short name T325
Test name
Test status
Simulation time 328541300984 ps
CPU time 256.25 seconds
Started Sep 09 05:48:02 AM UTC 24
Finished Sep 09 05:52:21 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702539579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2702539579
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.4200282942
Short name T98
Test name
Test status
Simulation time 325721921173 ps
CPU time 84.85 seconds
Started Sep 09 05:48:07 AM UTC 24
Finished Sep 09 05:49:34 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200282942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.4200282942
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.3460828676
Short name T351
Test name
Test status
Simulation time 189221162274 ps
CPU time 56.03 seconds
Started Sep 09 05:48:19 AM UTC 24
Finished Sep 09 05:49:17 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460828676 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.3460828676
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2314754716
Short name T530
Test name
Test status
Simulation time 403270320951 ps
CPU time 525.27 seconds
Started Sep 09 05:48:32 AM UTC 24
Finished Sep 09 05:57:24 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314754716 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.2314754716
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.1362019374
Short name T216
Test name
Test status
Simulation time 127565311144 ps
CPU time 645.2 seconds
Started Sep 09 05:48:57 AM UTC 24
Finished Sep 09 05:59:49 AM UTC 24
Peak memory 211780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362019374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1362019374
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.4004630247
Short name T100
Test name
Test status
Simulation time 42731942320 ps
CPU time 43.08 seconds
Started Sep 09 05:48:53 AM UTC 24
Finished Sep 09 05:49:37 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004630247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.4004630247
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.2531406789
Short name T486
Test name
Test status
Simulation time 3408566273 ps
CPU time 4.22 seconds
Started Sep 09 05:48:50 AM UTC 24
Finished Sep 09 05:48:56 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531406789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2531406789
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.1315118214
Short name T481
Test name
Test status
Simulation time 6034239932 ps
CPU time 2.97 seconds
Started Sep 09 05:48:02 AM UTC 24
Finished Sep 09 05:48:06 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315118214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1315118214
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.3564481896
Short name T314
Test name
Test status
Simulation time 336588900354 ps
CPU time 531.16 seconds
Started Sep 09 05:49:17 AM UTC 24
Finished Sep 09 05:58:14 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564481896 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.3564481896
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3753720859
Short name T86
Test name
Test status
Simulation time 7009346490 ps
CPU time 32.05 seconds
Started Sep 09 05:49:00 AM UTC 24
Finished Sep 09 05:49:33 AM UTC 24
Peak memory 222024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3753720859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.adc_ctrl_stress_all_with_rand_reset.3753720859
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.925370861
Short name T491
Test name
Test status
Simulation time 524503002 ps
CPU time 1.96 seconds
Started Sep 09 05:50:08 AM UTC 24
Finished Sep 09 05:50:11 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925370861 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.925370861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.4192090762
Short name T89
Test name
Test status
Simulation time 343458206336 ps
CPU time 408.56 seconds
Started Sep 09 05:49:44 AM UTC 24
Finished Sep 09 05:56:38 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192090762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4192090762
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.360798080
Short name T350
Test name
Test status
Simulation time 163742711095 ps
CPU time 233.9 seconds
Started Sep 09 05:49:30 AM UTC 24
Finished Sep 09 05:53:27 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360798080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.360798080
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2260542367
Short name T514
Test name
Test status
Simulation time 166225261785 ps
CPU time 302.94 seconds
Started Sep 09 05:49:34 AM UTC 24
Finished Sep 09 05:54:41 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260542367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.2260542367
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.3622352803
Short name T535
Test name
Test status
Simulation time 492014381259 ps
CPU time 513.4 seconds
Started Sep 09 05:49:21 AM UTC 24
Finished Sep 09 05:58:00 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622352803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3622352803
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.1868520453
Short name T525
Test name
Test status
Simulation time 326458676246 ps
CPU time 410.64 seconds
Started Sep 09 05:49:28 AM UTC 24
Finished Sep 09 05:56:23 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868520453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.1868520453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.930044226
Short name T324
Test name
Test status
Simulation time 353272647787 ps
CPU time 525.65 seconds
Started Sep 09 05:49:34 AM UTC 24
Finished Sep 09 05:58:25 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930044226 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.930044226
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.587331478
Short name T499
Test name
Test status
Simulation time 194468849689 ps
CPU time 135.21 seconds
Started Sep 09 05:49:35 AM UTC 24
Finished Sep 09 05:51:53 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587331478 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.587331478
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.1205752969
Short name T558
Test name
Test status
Simulation time 80852046015 ps
CPU time 637.78 seconds
Started Sep 09 05:50:02 AM UTC 24
Finished Sep 09 06:00:46 AM UTC 24
Peak memory 212088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205752969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1205752969
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.1975221105
Short name T495
Test name
Test status
Simulation time 30361438804 ps
CPU time 63.69 seconds
Started Sep 09 05:49:50 AM UTC 24
Finished Sep 09 05:50:55 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975221105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1975221105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.821676823
Short name T490
Test name
Test status
Simulation time 3879653175 ps
CPU time 17.81 seconds
Started Sep 09 05:49:48 AM UTC 24
Finished Sep 09 05:50:07 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821676823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.821676823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.1762320930
Short name T102
Test name
Test status
Simulation time 5495014335 ps
CPU time 24.52 seconds
Started Sep 09 05:49:21 AM UTC 24
Finished Sep 09 05:49:47 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762320930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1762320930
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.175514570
Short name T360
Test name
Test status
Simulation time 385939858754 ps
CPU time 503.24 seconds
Started Sep 09 05:50:03 AM UTC 24
Finished Sep 09 05:58:32 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175514570 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.175514570
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2452789167
Short name T352
Test name
Test status
Simulation time 70144746830 ps
CPU time 40.26 seconds
Started Sep 09 05:50:03 AM UTC 24
Finished Sep 09 05:50:45 AM UTC 24
Peak memory 221944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2452789167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.adc_ctrl_stress_all_with_rand_reset.2452789167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.698560531
Short name T501
Test name
Test status
Simulation time 278713587 ps
CPU time 2.06 seconds
Started Sep 09 05:51:53 AM UTC 24
Finished Sep 09 05:51:56 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698560531 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.698560531
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.149457698
Short name T283
Test name
Test status
Simulation time 329570315424 ps
CPU time 103.97 seconds
Started Sep 09 05:50:57 AM UTC 24
Finished Sep 09 05:52:43 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149457698 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.149457698
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.3269182605
Short name T541
Test name
Test status
Simulation time 168320707179 ps
CPU time 436.73 seconds
Started Sep 09 05:51:10 AM UTC 24
Finished Sep 09 05:58:31 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269182605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3269182605
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.1872403323
Short name T364
Test name
Test status
Simulation time 167311851622 ps
CPU time 152.28 seconds
Started Sep 09 05:50:45 AM UTC 24
Finished Sep 09 05:53:20 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872403323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1872403323
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4163017201
Short name T542
Test name
Test status
Simulation time 161754431218 ps
CPU time 461.89 seconds
Started Sep 09 05:50:47 AM UTC 24
Finished Sep 09 05:58:34 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163017201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.4163017201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.790860421
Short name T511
Test name
Test status
Simulation time 163195963029 ps
CPU time 232.69 seconds
Started Sep 09 05:50:37 AM UTC 24
Finished Sep 09 05:54:33 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790860421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.790860421
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.3024961376
Short name T547
Test name
Test status
Simulation time 324712630600 ps
CPU time 501.48 seconds
Started Sep 09 05:50:43 AM UTC 24
Finished Sep 09 05:59:11 AM UTC 24
Peak memory 211660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024961376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.3024961376
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.124329335
Short name T369
Test name
Test status
Simulation time 565269243796 ps
CPU time 903.47 seconds
Started Sep 09 05:50:48 AM UTC 24
Finished Sep 09 06:06:01 AM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124329335 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.124329335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2103962668
Short name T534
Test name
Test status
Simulation time 406399259282 ps
CPU time 402.4 seconds
Started Sep 09 05:50:55 AM UTC 24
Finished Sep 09 05:57:43 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103962668 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.2103962668
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.3910988861
Short name T377
Test name
Test status
Simulation time 89912693182 ps
CPU time 529.45 seconds
Started Sep 09 05:51:33 AM UTC 24
Finished Sep 09 06:00:28 AM UTC 24
Peak memory 211780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910988861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3910988861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.3752788740
Short name T498
Test name
Test status
Simulation time 42399190037 ps
CPU time 19.66 seconds
Started Sep 09 05:51:19 AM UTC 24
Finished Sep 09 05:51:40 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752788740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3752788740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.3134382866
Short name T496
Test name
Test status
Simulation time 3867127421 ps
CPU time 6.3 seconds
Started Sep 09 05:51:11 AM UTC 24
Finished Sep 09 05:51:18 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134382866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3134382866
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.17431848
Short name T492
Test name
Test status
Simulation time 5718199770 ps
CPU time 23.11 seconds
Started Sep 09 05:50:12 AM UTC 24
Finished Sep 09 05:50:36 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17431848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.17431848
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.325952228
Short name T365
Test name
Test status
Simulation time 334931900657 ps
CPU time 1182.79 seconds
Started Sep 09 05:51:47 AM UTC 24
Finished Sep 09 06:11:43 AM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325952228 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.325952228
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2118907360
Short name T500
Test name
Test status
Simulation time 2346512311 ps
CPU time 10.89 seconds
Started Sep 09 05:51:41 AM UTC 24
Finished Sep 09 05:51:53 AM UTC 24
Peak memory 211596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2118907360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.adc_ctrl_stress_all_with_rand_reset.2118907360
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.3941977112
Short name T506
Test name
Test status
Simulation time 318937555 ps
CPU time 2.09 seconds
Started Sep 09 05:53:42 AM UTC 24
Finished Sep 09 05:53:45 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941977112 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3941977112
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.2194312771
Short name T95
Test name
Test status
Simulation time 346037961775 ps
CPU time 240.69 seconds
Started Sep 09 05:52:58 AM UTC 24
Finished Sep 09 05:57:02 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194312771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2194312771
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.1465590853
Short name T313
Test name
Test status
Simulation time 163847938925 ps
CPU time 93.26 seconds
Started Sep 09 05:51:59 AM UTC 24
Finished Sep 09 05:53:34 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465590853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1465590853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2726537475
Short name T513
Test name
Test status
Simulation time 164444962590 ps
CPU time 150.77 seconds
Started Sep 09 05:52:04 AM UTC 24
Finished Sep 09 05:54:37 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726537475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.2726537475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.3060105563
Short name T521
Test name
Test status
Simulation time 331241062909 ps
CPU time 224.23 seconds
Started Sep 09 05:51:57 AM UTC 24
Finished Sep 09 05:55:45 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060105563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3060105563
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.2557661530
Short name T510
Test name
Test status
Simulation time 331236339507 ps
CPU time 139.71 seconds
Started Sep 09 05:51:59 AM UTC 24
Finished Sep 09 05:54:21 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557661530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.2557661530
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.1598003049
Short name T361
Test name
Test status
Simulation time 353053916484 ps
CPU time 1266.42 seconds
Started Sep 09 05:52:23 AM UTC 24
Finished Sep 09 06:13:42 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598003049 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.1598003049
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2933934252
Short name T563
Test name
Test status
Simulation time 191196593741 ps
CPU time 525.23 seconds
Started Sep 09 05:52:44 AM UTC 24
Finished Sep 09 06:01:35 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933934252 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.2933934252
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.4101314613
Short name T598
Test name
Test status
Simulation time 138828127451 ps
CPU time 877.02 seconds
Started Sep 09 05:53:23 AM UTC 24
Finished Sep 09 06:08:09 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101314613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4101314613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.3059833564
Short name T509
Test name
Test status
Simulation time 39191124041 ps
CPU time 46.87 seconds
Started Sep 09 05:53:22 AM UTC 24
Finished Sep 09 05:54:10 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059833564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3059833564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.1591732854
Short name T507
Test name
Test status
Simulation time 4069272101 ps
CPU time 23.25 seconds
Started Sep 09 05:53:21 AM UTC 24
Finished Sep 09 05:53:46 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591732854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1591732854
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.258033313
Short name T502
Test name
Test status
Simulation time 5953332295 ps
CPU time 3.46 seconds
Started Sep 09 05:51:54 AM UTC 24
Finished Sep 09 05:51:59 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258033313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.258033313
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.1968047735
Short name T297
Test name
Test status
Simulation time 394720473551 ps
CPU time 139.45 seconds
Started Sep 09 05:53:35 AM UTC 24
Finished Sep 09 05:55:57 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968047735 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.1968047735
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2176754658
Short name T31
Test name
Test status
Simulation time 13551104047 ps
CPU time 12.56 seconds
Started Sep 09 05:53:28 AM UTC 24
Finished Sep 09 05:53:42 AM UTC 24
Peak memory 222004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2176754658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.adc_ctrl_stress_all_with_rand_reset.2176754658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.1828267110
Short name T516
Test name
Test status
Simulation time 475937979 ps
CPU time 2.95 seconds
Started Sep 09 05:54:47 AM UTC 24
Finished Sep 09 05:54:52 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828267110 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1828267110
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.2997202581
Short name T326
Test name
Test status
Simulation time 487469444822 ps
CPU time 779.08 seconds
Started Sep 09 05:54:22 AM UTC 24
Finished Sep 09 06:07:29 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997202581 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.2997202581
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.3484117613
Short name T91
Test name
Test status
Simulation time 166055394804 ps
CPU time 166.54 seconds
Started Sep 09 05:53:54 AM UTC 24
Finished Sep 09 05:56:43 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484117613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3484117613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.111909424
Short name T566
Test name
Test status
Simulation time 164770211474 ps
CPU time 487.37 seconds
Started Sep 09 05:54:07 AM UTC 24
Finished Sep 09 06:02:20 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111909424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.111909424
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.2592378378
Short name T338
Test name
Test status
Simulation time 325985897594 ps
CPU time 229.81 seconds
Started Sep 09 05:53:47 AM UTC 24
Finished Sep 09 05:57:39 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592378378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2592378378
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.124555583
Short name T539
Test name
Test status
Simulation time 491752430105 ps
CPU time 263.85 seconds
Started Sep 09 05:53:47 AM UTC 24
Finished Sep 09 05:58:14 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124555583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.124555583
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2219062476
Short name T533
Test name
Test status
Simulation time 404427169940 ps
CPU time 201.13 seconds
Started Sep 09 05:54:11 AM UTC 24
Finished Sep 09 05:57:35 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219062476 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.2219062476
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.1836473674
Short name T581
Test name
Test status
Simulation time 118144152132 ps
CPU time 612.9 seconds
Started Sep 09 05:54:38 AM UTC 24
Finished Sep 09 06:04:58 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836473674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1836473674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.3491242404
Short name T518
Test name
Test status
Simulation time 24587575296 ps
CPU time 20.52 seconds
Started Sep 09 05:54:35 AM UTC 24
Finished Sep 09 05:54:57 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491242404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3491242404
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.2702435256
Short name T515
Test name
Test status
Simulation time 3181651637 ps
CPU time 7.11 seconds
Started Sep 09 05:54:35 AM UTC 24
Finished Sep 09 05:54:43 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702435256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2702435256
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.991136467
Short name T508
Test name
Test status
Simulation time 5712785269 ps
CPU time 23.71 seconds
Started Sep 09 05:53:42 AM UTC 24
Finished Sep 09 05:54:07 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991136467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.991136467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.228399848
Short name T517
Test name
Test status
Simulation time 5219202272 ps
CPU time 12.38 seconds
Started Sep 09 05:54:42 AM UTC 24
Finished Sep 09 05:54:56 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=228399848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
27.adc_ctrl_stress_all_with_rand_reset.228399848
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.4026378509
Short name T527
Test name
Test status
Simulation time 350748212 ps
CPU time 1.57 seconds
Started Sep 09 05:56:25 AM UTC 24
Finished Sep 09 05:56:28 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026378509 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.4026378509
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.2613885301
Short name T368
Test name
Test status
Simulation time 161492163395 ps
CPU time 40.87 seconds
Started Sep 09 05:55:28 AM UTC 24
Finished Sep 09 05:56:10 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613885301 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.2613885301
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.4271428562
Short name T191
Test name
Test status
Simulation time 492526174443 ps
CPU time 262.15 seconds
Started Sep 09 05:55:45 AM UTC 24
Finished Sep 09 06:00:11 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271428562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4271428562
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.282983050
Short name T725
Test name
Test status
Simulation time 495581244662 ps
CPU time 1717.21 seconds
Started Sep 09 05:55:02 AM UTC 24
Finished Sep 09 06:23:56 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282983050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.282983050
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3630213273
Short name T94
Test name
Test status
Simulation time 167061586476 ps
CPU time 116.6 seconds
Started Sep 09 05:55:02 AM UTC 24
Finished Sep 09 05:57:01 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630213273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.3630213273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.4082240377
Short name T623
Test name
Test status
Simulation time 325592678069 ps
CPU time 972.89 seconds
Started Sep 09 05:54:57 AM UTC 24
Finished Sep 09 06:11:20 AM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082240377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.4082240377
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.323833810
Short name T545
Test name
Test status
Simulation time 329147187282 ps
CPU time 227.45 seconds
Started Sep 09 05:54:58 AM UTC 24
Finished Sep 09 05:58:48 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323833810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.323833810
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.4021037154
Short name T524
Test name
Test status
Simulation time 185811690718 ps
CPU time 66.02 seconds
Started Sep 09 05:55:10 AM UTC 24
Finished Sep 09 05:56:18 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021037154 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.4021037154
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2847625418
Short name T537
Test name
Test status
Simulation time 201059148762 ps
CPU time 170.14 seconds
Started Sep 09 05:55:18 AM UTC 24
Finished Sep 09 05:58:11 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847625418 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.2847625418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.366781693
Short name T564
Test name
Test status
Simulation time 84083681066 ps
CPU time 341.38 seconds
Started Sep 09 05:56:02 AM UTC 24
Finished Sep 09 06:01:47 AM UTC 24
Peak memory 211828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366781693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.366781693
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.1637933567
Short name T96
Test name
Test status
Simulation time 32772444267 ps
CPU time 67.54 seconds
Started Sep 09 05:55:58 AM UTC 24
Finished Sep 09 05:57:07 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637933567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1637933567
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.2740713117
Short name T523
Test name
Test status
Simulation time 2881838053 ps
CPU time 2.8 seconds
Started Sep 09 05:55:58 AM UTC 24
Finished Sep 09 05:56:02 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740713117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2740713117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.2322843324
Short name T520
Test name
Test status
Simulation time 5806049726 ps
CPU time 23.28 seconds
Started Sep 09 05:54:53 AM UTC 24
Finished Sep 09 05:55:17 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322843324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2322843324
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.151375633
Short name T588
Test name
Test status
Simulation time 265882303842 ps
CPU time 552.11 seconds
Started Sep 09 05:56:19 AM UTC 24
Finished Sep 09 06:05:36 AM UTC 24
Peak memory 222088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151375633 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.151375633
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3592807990
Short name T87
Test name
Test status
Simulation time 56946940147 ps
CPU time 15.72 seconds
Started Sep 09 05:56:11 AM UTC 24
Finished Sep 09 05:56:28 AM UTC 24
Peak memory 221996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3592807990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.adc_ctrl_stress_all_with_rand_reset.3592807990
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.2871517334
Short name T531
Test name
Test status
Simulation time 413286634 ps
CPU time 1.26 seconds
Started Sep 09 05:57:22 AM UTC 24
Finished Sep 09 05:57:24 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871517334 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2871517334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.314339820
Short name T371
Test name
Test status
Simulation time 330827450086 ps
CPU time 550.46 seconds
Started Sep 09 05:56:56 AM UTC 24
Finished Sep 09 06:06:13 AM UTC 24
Peak memory 211864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314339820 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.314339820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.3670593845
Short name T315
Test name
Test status
Simulation time 170236985329 ps
CPU time 73.81 seconds
Started Sep 09 05:57:01 AM UTC 24
Finished Sep 09 05:58:17 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670593845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3670593845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.1919375207
Short name T633
Test name
Test status
Simulation time 327731536686 ps
CPU time 924.19 seconds
Started Sep 09 05:56:38 AM UTC 24
Finished Sep 09 06:12:12 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919375207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1919375207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2520094657
Short name T574
Test name
Test status
Simulation time 487937403533 ps
CPU time 412.45 seconds
Started Sep 09 05:56:44 AM UTC 24
Finished Sep 09 06:03:42 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520094657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.2520094657
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.3555040972
Short name T676
Test name
Test status
Simulation time 512069745620 ps
CPU time 1317.11 seconds
Started Sep 09 05:56:29 AM UTC 24
Finished Sep 09 06:18:39 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555040972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3555040972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.851009566
Short name T606
Test name
Test status
Simulation time 325737736282 ps
CPU time 721.72 seconds
Started Sep 09 05:56:29 AM UTC 24
Finished Sep 09 06:08:39 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851009566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.851009566
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.829876781
Short name T339
Test name
Test status
Simulation time 666483831039 ps
CPU time 534.23 seconds
Started Sep 09 05:56:45 AM UTC 24
Finished Sep 09 06:05:46 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829876781 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.829876781
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1735827402
Short name T741
Test name
Test status
Simulation time 608640667650 ps
CPU time 1730.34 seconds
Started Sep 09 05:56:55 AM UTC 24
Finished Sep 09 06:26:02 AM UTC 24
Peak memory 212876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735827402 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.1735827402
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.3389200836
Short name T217
Test name
Test status
Simulation time 102116215665 ps
CPU time 685.19 seconds
Started Sep 09 05:57:09 AM UTC 24
Finished Sep 09 06:08:42 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389200836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3389200836
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.1954215838
Short name T529
Test name
Test status
Simulation time 26478963313 ps
CPU time 14.04 seconds
Started Sep 09 05:57:08 AM UTC 24
Finished Sep 09 05:57:24 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954215838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1954215838
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.3266442006
Short name T97
Test name
Test status
Simulation time 3486654623 ps
CPU time 4.14 seconds
Started Sep 09 05:57:03 AM UTC 24
Finished Sep 09 05:57:08 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266442006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3266442006
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.2942455436
Short name T93
Test name
Test status
Simulation time 6056652902 ps
CPU time 25.68 seconds
Started Sep 09 05:56:28 AM UTC 24
Finished Sep 09 05:56:55 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942455436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2942455436
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3984418551
Short name T32
Test name
Test status
Simulation time 5445560519 ps
CPU time 5.92 seconds
Started Sep 09 05:57:15 AM UTC 24
Finished Sep 09 05:57:22 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3984418551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.adc_ctrl_stress_all_with_rand_reset.3984418551
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.3860614048
Short name T141
Test name
Test status
Simulation time 467777168 ps
CPU time 2.69 seconds
Started Sep 09 05:20:19 AM UTC 24
Finished Sep 09 05:20:23 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860614048 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3860614048
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1124924875
Short name T48
Test name
Test status
Simulation time 344790754236 ps
CPU time 212.25 seconds
Started Sep 09 05:19:42 AM UTC 24
Finished Sep 09 05:23:17 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124924875 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.1124924875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2209166691
Short name T14
Test name
Test status
Simulation time 165440754418 ps
CPU time 67.61 seconds
Started Sep 09 05:19:40 AM UTC 24
Finished Sep 09 05:20:49 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209166691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2209166691
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.142179417
Short name T17
Test name
Test status
Simulation time 167150664584 ps
CPU time 98.57 seconds
Started Sep 09 05:19:40 AM UTC 24
Finished Sep 09 05:21:20 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142179417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.142179417
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.2446576406
Short name T266
Test name
Test status
Simulation time 167270414471 ps
CPU time 581.33 seconds
Started Sep 09 05:19:36 AM UTC 24
Finished Sep 09 05:29:24 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446576406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2446576406
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2652795625
Short name T202
Test name
Test status
Simulation time 325807313868 ps
CPU time 415.94 seconds
Started Sep 09 05:19:38 AM UTC 24
Finished Sep 09 05:26:38 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652795625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.2652795625
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3927230365
Short name T475
Test name
Test status
Simulation time 591385056904 ps
CPU time 1663.04 seconds
Started Sep 09 05:19:41 AM UTC 24
Finished Sep 09 05:47:40 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927230365 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.3927230365
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1170060714
Short name T60
Test name
Test status
Simulation time 90612531816 ps
CPU time 559.3 seconds
Started Sep 09 05:20:06 AM UTC 24
Finished Sep 09 05:29:31 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170060714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1170060714
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.3647113088
Short name T57
Test name
Test status
Simulation time 35395709483 ps
CPU time 19.43 seconds
Started Sep 09 05:19:58 AM UTC 24
Finished Sep 09 05:20:18 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647113088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3647113088
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2437227658
Short name T61
Test name
Test status
Simulation time 3091098593 ps
CPU time 7.84 seconds
Started Sep 09 05:19:55 AM UTC 24
Finished Sep 09 05:20:04 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437227658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2437227658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.2035230875
Short name T34
Test name
Test status
Simulation time 4702946307 ps
CPU time 10.99 seconds
Started Sep 09 05:20:19 AM UTC 24
Finished Sep 09 05:20:31 AM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035230875 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2035230875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.3501729181
Short name T140
Test name
Test status
Simulation time 5875467019 ps
CPU time 19.79 seconds
Started Sep 09 05:19:36 AM UTC 24
Finished Sep 09 05:19:57 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501729181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3501729181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2866214094
Short name T159
Test name
Test status
Simulation time 505164753118 ps
CPU time 728.78 seconds
Started Sep 09 05:20:14 AM UTC 24
Finished Sep 09 05:32:31 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866214094 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.2866214094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.3745684887
Short name T540
Test name
Test status
Simulation time 288993657 ps
CPU time 2.13 seconds
Started Sep 09 05:58:15 AM UTC 24
Finished Sep 09 05:58:18 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745684887 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3745684887
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.2939774693
Short name T306
Test name
Test status
Simulation time 349415191274 ps
CPU time 853.54 seconds
Started Sep 09 05:57:44 AM UTC 24
Finished Sep 09 06:12:06 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939774693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2939774693
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.3459019026
Short name T357
Test name
Test status
Simulation time 331530971080 ps
CPU time 192.07 seconds
Started Sep 09 05:57:26 AM UTC 24
Finished Sep 09 06:00:41 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459019026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3459019026
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3396738007
Short name T557
Test name
Test status
Simulation time 329714585113 ps
CPU time 189.68 seconds
Started Sep 09 05:57:29 AM UTC 24
Finished Sep 09 06:00:42 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396738007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.3396738007
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.2334954767
Short name T599
Test name
Test status
Simulation time 496895068538 ps
CPU time 640.78 seconds
Started Sep 09 05:57:24 AM UTC 24
Finished Sep 09 06:08:11 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334954767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2334954767
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.1251121120
Short name T576
Test name
Test status
Simulation time 321810312229 ps
CPU time 405.81 seconds
Started Sep 09 05:57:25 AM UTC 24
Finished Sep 09 06:04:16 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251121120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.1251121120
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.3499984417
Short name T288
Test name
Test status
Simulation time 357611314196 ps
CPU time 858.7 seconds
Started Sep 09 05:57:36 AM UTC 24
Finished Sep 09 06:12:04 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499984417 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.3499984417
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3572690248
Short name T625
Test name
Test status
Simulation time 598702499025 ps
CPU time 819.77 seconds
Started Sep 09 05:57:39 AM UTC 24
Finished Sep 09 06:11:28 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572690248 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.3572690248
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.1969300805
Short name T572
Test name
Test status
Simulation time 86686429936 ps
CPU time 322.54 seconds
Started Sep 09 05:58:11 AM UTC 24
Finished Sep 09 06:03:37 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969300805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1969300805
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.106707350
Short name T555
Test name
Test status
Simulation time 30222841955 ps
CPU time 112.5 seconds
Started Sep 09 05:58:02 AM UTC 24
Finished Sep 09 05:59:56 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106707350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.106707350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.2103698010
Short name T538
Test name
Test status
Simulation time 4818364885 ps
CPU time 10.66 seconds
Started Sep 09 05:58:01 AM UTC 24
Finished Sep 09 05:58:12 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103698010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2103698010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.2648056641
Short name T532
Test name
Test status
Simulation time 5816954511 ps
CPU time 3.58 seconds
Started Sep 09 05:57:24 AM UTC 24
Finished Sep 09 05:57:29 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648056641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2648056641
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.306940033
Short name T33
Test name
Test status
Simulation time 2625095555 ps
CPU time 16.31 seconds
Started Sep 09 05:58:12 AM UTC 24
Finished Sep 09 05:58:30 AM UTC 24
Peak memory 221672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=306940033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
30.adc_ctrl_stress_all_with_rand_reset.306940033
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.1489548763
Short name T549
Test name
Test status
Simulation time 426576430 ps
CPU time 1.13 seconds
Started Sep 09 05:59:18 AM UTC 24
Finished Sep 09 05:59:20 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489548763 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1489548763
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.1235607629
Short name T336
Test name
Test status
Simulation time 163851989475 ps
CPU time 79.39 seconds
Started Sep 09 05:58:36 AM UTC 24
Finished Sep 09 05:59:57 AM UTC 24
Peak memory 211856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235607629 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.1235607629
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.386640927
Short name T634
Test name
Test status
Simulation time 540151344128 ps
CPU time 813.07 seconds
Started Sep 09 05:58:36 AM UTC 24
Finished Sep 09 06:12:17 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386640927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.386640927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.1079013524
Short name T580
Test name
Test status
Simulation time 165139651724 ps
CPU time 378.39 seconds
Started Sep 09 05:58:26 AM UTC 24
Finished Sep 09 06:04:49 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079013524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1079013524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2925436152
Short name T577
Test name
Test status
Simulation time 160107713147 ps
CPU time 344.67 seconds
Started Sep 09 05:58:30 AM UTC 24
Finished Sep 09 06:04:19 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925436152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.2925436152
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.2649103885
Short name T692
Test name
Test status
Simulation time 498073431422 ps
CPU time 1317 seconds
Started Sep 09 05:58:17 AM UTC 24
Finished Sep 09 06:20:27 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649103885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2649103885
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.2488553253
Short name T586
Test name
Test status
Simulation time 165221899273 ps
CPU time 414.96 seconds
Started Sep 09 05:58:19 AM UTC 24
Finished Sep 09 06:05:19 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488553253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.2488553253
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.2208426849
Short name T367
Test name
Test status
Simulation time 578407805973 ps
CPU time 864.28 seconds
Started Sep 09 05:58:31 AM UTC 24
Finished Sep 09 06:13:05 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208426849 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.2208426849
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1659273319
Short name T614
Test name
Test status
Simulation time 412823690014 ps
CPU time 678.89 seconds
Started Sep 09 05:58:32 AM UTC 24
Finished Sep 09 06:09:59 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659273319 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.1659273319
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.3853822562
Short name T592
Test name
Test status
Simulation time 115533964103 ps
CPU time 461.67 seconds
Started Sep 09 05:58:49 AM UTC 24
Finished Sep 09 06:06:35 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853822562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3853822562
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.2277835149
Short name T554
Test name
Test status
Simulation time 32228455643 ps
CPU time 66.92 seconds
Started Sep 09 05:58:42 AM UTC 24
Finished Sep 09 05:59:50 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277835149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2277835149
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.828459418
Short name T546
Test name
Test status
Simulation time 4693879515 ps
CPU time 13.28 seconds
Started Sep 09 05:58:41 AM UTC 24
Finished Sep 09 05:58:55 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828459418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.828459418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.368638184
Short name T543
Test name
Test status
Simulation time 6201559795 ps
CPU time 24.2 seconds
Started Sep 09 05:58:15 AM UTC 24
Finished Sep 09 05:58:40 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368638184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.368638184
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.4156963127
Short name T648
Test name
Test status
Simulation time 773427468470 ps
CPU time 940.65 seconds
Started Sep 09 05:59:12 AM UTC 24
Finished Sep 09 06:15:02 AM UTC 24
Peak memory 223180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156963127 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.4156963127
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3455496060
Short name T548
Test name
Test status
Simulation time 33036662580 ps
CPU time 20.75 seconds
Started Sep 09 05:58:56 AM UTC 24
Finished Sep 09 05:59:18 AM UTC 24
Peak memory 221688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3455496060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.adc_ctrl_stress_all_with_rand_reset.3455496060
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.3020254282
Short name T559
Test name
Test status
Simulation time 444063565 ps
CPU time 1.74 seconds
Started Sep 09 06:00:47 AM UTC 24
Finished Sep 09 06:00:50 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020254282 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3020254282
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.4094202955
Short name T585
Test name
Test status
Simulation time 338218110631 ps
CPU time 315.69 seconds
Started Sep 09 05:59:57 AM UTC 24
Finished Sep 09 06:05:16 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094202955 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.4094202955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.4018931403
Short name T341
Test name
Test status
Simulation time 157928612784 ps
CPU time 489.8 seconds
Started Sep 09 05:59:49 AM UTC 24
Finished Sep 09 06:08:05 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018931403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4018931403
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3143339732
Short name T562
Test name
Test status
Simulation time 165198048109 ps
CPU time 88.31 seconds
Started Sep 09 05:59:49 AM UTC 24
Finished Sep 09 06:01:20 AM UTC 24
Peak memory 211728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143339732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.3143339732
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.2669934006
Short name T192
Test name
Test status
Simulation time 487940285923 ps
CPU time 197.95 seconds
Started Sep 09 05:59:47 AM UTC 24
Finished Sep 09 06:03:08 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669934006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2669934006
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.2070126445
Short name T565
Test name
Test status
Simulation time 323152472056 ps
CPU time 132.32 seconds
Started Sep 09 05:59:47 AM UTC 24
Finished Sep 09 06:02:02 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070126445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.2070126445
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1618246808
Short name T685
Test name
Test status
Simulation time 397034700786 ps
CPU time 1175.04 seconds
Started Sep 09 05:59:51 AM UTC 24
Finished Sep 09 06:19:38 AM UTC 24
Peak memory 212568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618246808 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.1618246808
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.1345311386
Short name T380
Test name
Test status
Simulation time 74833549063 ps
CPU time 341.97 seconds
Started Sep 09 06:00:36 AM UTC 24
Finished Sep 09 06:06:22 AM UTC 24
Peak memory 211780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345311386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1345311386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.1599277494
Short name T560
Test name
Test status
Simulation time 29689355857 ps
CPU time 25.8 seconds
Started Sep 09 06:00:29 AM UTC 24
Finished Sep 09 06:00:56 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599277494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1599277494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.3493595514
Short name T556
Test name
Test status
Simulation time 4635847302 ps
CPU time 21.96 seconds
Started Sep 09 06:00:12 AM UTC 24
Finished Sep 09 06:00:35 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493595514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3493595514
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.2327443718
Short name T551
Test name
Test status
Simulation time 5952950614 ps
CPU time 24.18 seconds
Started Sep 09 05:59:21 AM UTC 24
Finished Sep 09 05:59:47 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327443718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2327443718
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.3667373092
Short name T646
Test name
Test status
Simulation time 324139726383 ps
CPU time 824.58 seconds
Started Sep 09 06:00:42 AM UTC 24
Finished Sep 09 06:14:35 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667373092 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.3667373092
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.720890537
Short name T39
Test name
Test status
Simulation time 51439421018 ps
CPU time 18.1 seconds
Started Sep 09 06:00:42 AM UTC 24
Finished Sep 09 06:01:01 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=720890537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
32.adc_ctrl_stress_all_with_rand_reset.720890537
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.1709256614
Short name T571
Test name
Test status
Simulation time 448039940 ps
CPU time 1.07 seconds
Started Sep 09 06:03:28 AM UTC 24
Finished Sep 09 06:03:31 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709256614 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1709256614
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.1131324673
Short name T307
Test name
Test status
Simulation time 236765103839 ps
CPU time 90.65 seconds
Started Sep 09 06:02:03 AM UTC 24
Finished Sep 09 06:03:35 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131324673 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.1131324673
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.2990771142
Short name T616
Test name
Test status
Simulation time 362668851856 ps
CPU time 500.62 seconds
Started Sep 09 06:02:17 AM UTC 24
Finished Sep 09 06:10:43 AM UTC 24
Peak memory 211712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990771142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2990771142
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.3428008545
Short name T578
Test name
Test status
Simulation time 160612375715 ps
CPU time 200.2 seconds
Started Sep 09 06:01:02 AM UTC 24
Finished Sep 09 06:04:26 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428008545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3428008545
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4006402547
Short name T678
Test name
Test status
Simulation time 328872822326 ps
CPU time 1049.11 seconds
Started Sep 09 06:01:21 AM UTC 24
Finished Sep 09 06:19:01 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006402547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.4006402547
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.3851483608
Short name T198
Test name
Test status
Simulation time 488567464111 ps
CPU time 373.42 seconds
Started Sep 09 06:00:57 AM UTC 24
Finished Sep 09 06:07:15 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851483608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3851483608
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.896435669
Short name T594
Test name
Test status
Simulation time 482331856629 ps
CPU time 361.15 seconds
Started Sep 09 06:01:00 AM UTC 24
Finished Sep 09 06:07:06 AM UTC 24
Peak memory 211600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896435669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.896435669
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1643019288
Short name T584
Test name
Test status
Simulation time 200589281995 ps
CPU time 200.37 seconds
Started Sep 09 06:01:48 AM UTC 24
Finished Sep 09 06:05:11 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643019288 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.1643019288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.698512890
Short name T613
Test name
Test status
Simulation time 109887061858 ps
CPU time 391.81 seconds
Started Sep 09 06:03:02 AM UTC 24
Finished Sep 09 06:09:38 AM UTC 24
Peak memory 212020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698512890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.698512890
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.3506817418
Short name T570
Test name
Test status
Simulation time 40972981154 ps
CPU time 43.83 seconds
Started Sep 09 06:02:42 AM UTC 24
Finished Sep 09 06:03:27 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506817418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3506817418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.1900769423
Short name T567
Test name
Test status
Simulation time 4318683361 ps
CPU time 19.78 seconds
Started Sep 09 06:02:20 AM UTC 24
Finished Sep 09 06:02:41 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900769423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1900769423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.2821767619
Short name T561
Test name
Test status
Simulation time 6114501523 ps
CPU time 7.46 seconds
Started Sep 09 06:00:51 AM UTC 24
Finished Sep 09 06:01:00 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821767619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2821767619
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3476457014
Short name T569
Test name
Test status
Simulation time 1701979095 ps
CPU time 5.62 seconds
Started Sep 09 06:03:09 AM UTC 24
Finished Sep 09 06:03:16 AM UTC 24
Peak memory 221820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3476457014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.adc_ctrl_stress_all_with_rand_reset.3476457014
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.1043437465
Short name T583
Test name
Test status
Simulation time 532620118 ps
CPU time 3.04 seconds
Started Sep 09 06:04:59 AM UTC 24
Finished Sep 09 06:05:02 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043437465 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1043437465
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.2322142636
Short name T691
Test name
Test status
Simulation time 357663814558 ps
CPU time 949.87 seconds
Started Sep 09 06:04:20 AM UTC 24
Finished Sep 09 06:20:19 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322142636 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.2322142636
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.779649229
Short name T615
Test name
Test status
Simulation time 158592777261 ps
CPU time 414.71 seconds
Started Sep 09 06:03:38 AM UTC 24
Finished Sep 09 06:10:37 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779649229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.779649229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4017016731
Short name T689
Test name
Test status
Simulation time 322418613220 ps
CPU time 977.17 seconds
Started Sep 09 06:03:43 AM UTC 24
Finished Sep 09 06:20:10 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017016731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.4017016731
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.1767874224
Short name T628
Test name
Test status
Simulation time 165110586132 ps
CPU time 471.4 seconds
Started Sep 09 06:03:38 AM UTC 24
Finished Sep 09 06:11:34 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767874224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.1767874224
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3646369418
Short name T629
Test name
Test status
Simulation time 610593289447 ps
CPU time 437.96 seconds
Started Sep 09 06:04:16 AM UTC 24
Finished Sep 09 06:11:40 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646369418 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.3646369418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.682129855
Short name T673
Test name
Test status
Simulation time 121635528002 ps
CPU time 813.67 seconds
Started Sep 09 06:04:34 AM UTC 24
Finished Sep 09 06:18:16 AM UTC 24
Peak memory 211828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682129855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.682129855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.2644835170
Short name T589
Test name
Test status
Simulation time 28031859555 ps
CPU time 69.64 seconds
Started Sep 09 06:04:27 AM UTC 24
Finished Sep 09 06:05:39 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644835170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2644835170
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.2754553166
Short name T579
Test name
Test status
Simulation time 5218853486 ps
CPU time 6.89 seconds
Started Sep 09 06:04:25 AM UTC 24
Finished Sep 09 06:04:33 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754553166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2754553166
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.2773599427
Short name T573
Test name
Test status
Simulation time 6002716709 ps
CPU time 4.58 seconds
Started Sep 09 06:03:31 AM UTC 24
Finished Sep 09 06:03:37 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773599427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2773599427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3263663439
Short name T612
Test name
Test status
Simulation time 349366617129 ps
CPU time 270.2 seconds
Started Sep 09 06:04:58 AM UTC 24
Finished Sep 09 06:09:32 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263663439 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.3263663439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3127301415
Short name T582
Test name
Test status
Simulation time 3853903896 ps
CPU time 7.4 seconds
Started Sep 09 06:04:49 AM UTC 24
Finished Sep 09 06:04:58 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3127301415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.adc_ctrl_stress_all_with_rand_reset.3127301415
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.1317642901
Short name T591
Test name
Test status
Simulation time 423770347 ps
CPU time 0.95 seconds
Started Sep 09 06:06:14 AM UTC 24
Finished Sep 09 06:06:16 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317642901 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1317642901
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.2758115811
Short name T323
Test name
Test status
Simulation time 343156504549 ps
CPU time 899.36 seconds
Started Sep 09 06:05:40 AM UTC 24
Finished Sep 09 06:20:49 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758115811 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.2758115811
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.565038161
Short name T604
Test name
Test status
Simulation time 325734235378 ps
CPU time 170.45 seconds
Started Sep 09 06:05:44 AM UTC 24
Finished Sep 09 06:08:37 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565038161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.565038161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.707632952
Short name T179
Test name
Test status
Simulation time 493354336354 ps
CPU time 307.1 seconds
Started Sep 09 06:05:17 AM UTC 24
Finished Sep 09 06:10:28 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707632952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.707632952
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.67412926
Short name T596
Test name
Test status
Simulation time 163211720012 ps
CPU time 159.69 seconds
Started Sep 09 06:05:19 AM UTC 24
Finished Sep 09 06:08:01 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67412926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.67412926
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.1576349339
Short name T309
Test name
Test status
Simulation time 163161459704 ps
CPU time 183.44 seconds
Started Sep 09 06:05:08 AM UTC 24
Finished Sep 09 06:08:14 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576349339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1576349339
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.2595916161
Short name T643
Test name
Test status
Simulation time 324926070084 ps
CPU time 548.82 seconds
Started Sep 09 06:05:12 AM UTC 24
Finished Sep 09 06:14:27 AM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595916161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.2595916161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.3368639411
Short name T693
Test name
Test status
Simulation time 367110659781 ps
CPU time 888.97 seconds
Started Sep 09 06:05:30 AM UTC 24
Finished Sep 09 06:20:28 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368639411 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.3368639411
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.444299099
Short name T645
Test name
Test status
Simulation time 590048957313 ps
CPU time 528.82 seconds
Started Sep 09 06:05:37 AM UTC 24
Finished Sep 09 06:14:32 AM UTC 24
Peak memory 211660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444299099 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.444299099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.1109598073
Short name T659
Test name
Test status
Simulation time 122099070886 ps
CPU time 627.42 seconds
Started Sep 09 06:05:55 AM UTC 24
Finished Sep 09 06:16:30 AM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109598073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1109598073
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.1998541195
Short name T595
Test name
Test status
Simulation time 28072968770 ps
CPU time 115.03 seconds
Started Sep 09 06:05:47 AM UTC 24
Finished Sep 09 06:07:45 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998541195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1998541195
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.2528385064
Short name T590
Test name
Test status
Simulation time 2986328494 ps
CPU time 7.42 seconds
Started Sep 09 06:05:46 AM UTC 24
Finished Sep 09 06:05:55 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528385064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2528385064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.3447524621
Short name T587
Test name
Test status
Simulation time 5959869465 ps
CPU time 24.64 seconds
Started Sep 09 06:05:04 AM UTC 24
Finished Sep 09 06:05:29 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447524621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3447524621
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.3209838608
Short name T251
Test name
Test status
Simulation time 391487949490 ps
CPU time 1335.17 seconds
Started Sep 09 06:06:12 AM UTC 24
Finished Sep 09 06:28:42 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209838608 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.3209838608
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3837248432
Short name T311
Test name
Test status
Simulation time 5298737617 ps
CPU time 7.41 seconds
Started Sep 09 06:06:03 AM UTC 24
Finished Sep 09 06:06:11 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3837248432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.adc_ctrl_stress_all_with_rand_reset.3837248432
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.3830469729
Short name T600
Test name
Test status
Simulation time 359384954 ps
CPU time 1 seconds
Started Sep 09 06:08:15 AM UTC 24
Finished Sep 09 06:08:17 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830469729 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3830469729
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.4285263711
Short name T327
Test name
Test status
Simulation time 337286550542 ps
CPU time 185.57 seconds
Started Sep 09 06:07:41 AM UTC 24
Finished Sep 09 06:10:50 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285263711 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.4285263711
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.666661480
Short name T647
Test name
Test status
Simulation time 165707636907 ps
CPU time 490.07 seconds
Started Sep 09 06:06:44 AM UTC 24
Finished Sep 09 06:15:00 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666661480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.666661480
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.333624824
Short name T624
Test name
Test status
Simulation time 323819312910 ps
CPU time 251.85 seconds
Started Sep 09 06:07:07 AM UTC 24
Finished Sep 09 06:11:22 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333624824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.333624824
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.2609714186
Short name T609
Test name
Test status
Simulation time 164647561262 ps
CPU time 161.58 seconds
Started Sep 09 06:06:23 AM UTC 24
Finished Sep 09 06:09:07 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609714186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2609714186
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.2352020647
Short name T644
Test name
Test status
Simulation time 163301894014 ps
CPU time 467.05 seconds
Started Sep 09 06:06:36 AM UTC 24
Finished Sep 09 06:14:28 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352020647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.2352020647
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.3943982877
Short name T373
Test name
Test status
Simulation time 274580203590 ps
CPU time 334.17 seconds
Started Sep 09 06:07:16 AM UTC 24
Finished Sep 09 06:12:54 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943982877 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.3943982877
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2424059988
Short name T658
Test name
Test status
Simulation time 395116818591 ps
CPU time 521.3 seconds
Started Sep 09 06:07:30 AM UTC 24
Finished Sep 09 06:16:17 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424059988 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.2424059988
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.3245963445
Short name T688
Test name
Test status
Simulation time 134175927254 ps
CPU time 708.89 seconds
Started Sep 09 06:08:09 AM UTC 24
Finished Sep 09 06:20:06 AM UTC 24
Peak memory 211896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245963445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3245963445
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.2747506989
Short name T605
Test name
Test status
Simulation time 33398732490 ps
CPU time 31.58 seconds
Started Sep 09 06:08:06 AM UTC 24
Finished Sep 09 06:08:38 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747506989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2747506989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.1285179130
Short name T597
Test name
Test status
Simulation time 4233109076 ps
CPU time 5 seconds
Started Sep 09 06:08:02 AM UTC 24
Finished Sep 09 06:08:08 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285179130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1285179130
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.282700126
Short name T593
Test name
Test status
Simulation time 6053410652 ps
CPU time 25.25 seconds
Started Sep 09 06:06:17 AM UTC 24
Finished Sep 09 06:06:43 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282700126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.282700126
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.540191655
Short name T740
Test name
Test status
Simulation time 301949905125 ps
CPU time 1055.9 seconds
Started Sep 09 06:08:12 AM UTC 24
Finished Sep 09 06:25:57 AM UTC 24
Peak memory 212804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540191655 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.540191655
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2279883340
Short name T293
Test name
Test status
Simulation time 2709533507 ps
CPU time 22.75 seconds
Started Sep 09 06:08:10 AM UTC 24
Finished Sep 09 06:08:34 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2279883340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.adc_ctrl_stress_all_with_rand_reset.2279883340
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.406291828
Short name T610
Test name
Test status
Simulation time 454824553 ps
CPU time 2.65 seconds
Started Sep 09 06:09:08 AM UTC 24
Finished Sep 09 06:09:12 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406291828 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.406291828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.178638447
Short name T196
Test name
Test status
Simulation time 502844163534 ps
CPU time 260.12 seconds
Started Sep 09 06:08:38 AM UTC 24
Finished Sep 09 06:13:02 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178638447 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.178638447
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.2770762334
Short name T700
Test name
Test status
Simulation time 348347351396 ps
CPU time 747.83 seconds
Started Sep 09 06:08:40 AM UTC 24
Finished Sep 09 06:21:16 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770762334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2770762334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3159985819
Short name T627
Test name
Test status
Simulation time 326563483757 ps
CPU time 181.73 seconds
Started Sep 09 06:08:28 AM UTC 24
Finished Sep 09 06:11:33 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159985819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.3159985819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.2773900301
Short name T622
Test name
Test status
Simulation time 156377185937 ps
CPU time 167.15 seconds
Started Sep 09 06:08:19 AM UTC 24
Finished Sep 09 06:11:08 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773900301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2773900301
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.1123026140
Short name T618
Test name
Test status
Simulation time 335171080428 ps
CPU time 142.38 seconds
Started Sep 09 06:08:25 AM UTC 24
Finished Sep 09 06:10:50 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123026140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.1123026140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.301876378
Short name T763
Test name
Test status
Simulation time 525556950064 ps
CPU time 1222.12 seconds
Started Sep 09 06:08:34 AM UTC 24
Finished Sep 09 06:29:08 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301876378 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.301876378
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.761485318
Short name T656
Test name
Test status
Simulation time 604643041992 ps
CPU time 452.32 seconds
Started Sep 09 06:08:36 AM UTC 24
Finished Sep 09 06:16:14 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761485318 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.761485318
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.2585050163
Short name T619
Test name
Test status
Simulation time 44729966358 ps
CPU time 128.83 seconds
Started Sep 09 06:08:43 AM UTC 24
Finished Sep 09 06:10:54 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585050163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2585050163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.3922854196
Short name T607
Test name
Test status
Simulation time 3659323067 ps
CPU time 4.65 seconds
Started Sep 09 06:08:40 AM UTC 24
Finished Sep 09 06:08:45 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922854196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3922854196
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.857771546
Short name T608
Test name
Test status
Simulation time 6047768661 ps
CPU time 26.85 seconds
Started Sep 09 06:08:18 AM UTC 24
Finished Sep 09 06:08:46 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857771546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.857771546
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.1994739732
Short name T661
Test name
Test status
Simulation time 168821095792 ps
CPU time 452.06 seconds
Started Sep 09 06:09:03 AM UTC 24
Finished Sep 09 06:16:40 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994739732 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.1994739732
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1652035747
Short name T285
Test name
Test status
Simulation time 3353195631 ps
CPU time 13.84 seconds
Started Sep 09 06:08:47 AM UTC 24
Finished Sep 09 06:09:02 AM UTC 24
Peak memory 211596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1652035747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.adc_ctrl_stress_all_with_rand_reset.1652035747
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.2951135702
Short name T621
Test name
Test status
Simulation time 357461452 ps
CPU time 2.35 seconds
Started Sep 09 06:11:00 AM UTC 24
Finished Sep 09 06:11:04 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951135702 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2951135702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.2787959704
Short name T687
Test name
Test status
Simulation time 509188443269 ps
CPU time 561.55 seconds
Started Sep 09 06:10:35 AM UTC 24
Finished Sep 09 06:20:03 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787959704 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.2787959704
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.2982045945
Short name T710
Test name
Test status
Simulation time 554632833280 ps
CPU time 705.98 seconds
Started Sep 09 06:10:38 AM UTC 24
Finished Sep 09 06:22:31 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982045945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2982045945
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1070673345
Short name T635
Test name
Test status
Simulation time 169531976682 ps
CPU time 150.1 seconds
Started Sep 09 06:09:59 AM UTC 24
Finished Sep 09 06:12:32 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070673345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.1070673345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.2290672256
Short name T372
Test name
Test status
Simulation time 333128901591 ps
CPU time 1073.47 seconds
Started Sep 09 06:09:27 AM UTC 24
Finished Sep 09 06:27:32 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290672256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2290672256
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.3441871522
Short name T652
Test name
Test status
Simulation time 493437118732 ps
CPU time 367.32 seconds
Started Sep 09 06:09:33 AM UTC 24
Finished Sep 09 06:15:45 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441871522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.3441871522
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.3980255550
Short name T304
Test name
Test status
Simulation time 353041325499 ps
CPU time 333.06 seconds
Started Sep 09 06:10:19 AM UTC 24
Finished Sep 09 06:15:56 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980255550 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.3980255550
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.638601833
Short name T665
Test name
Test status
Simulation time 629513843110 ps
CPU time 397.28 seconds
Started Sep 09 06:10:29 AM UTC 24
Finished Sep 09 06:17:10 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638601833 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.638601833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.3040169297
Short name T660
Test name
Test status
Simulation time 73320715370 ps
CPU time 343.96 seconds
Started Sep 09 06:10:51 AM UTC 24
Finished Sep 09 06:16:39 AM UTC 24
Peak memory 211840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040169297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3040169297
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.4156681876
Short name T631
Test name
Test status
Simulation time 25073434085 ps
CPU time 68.85 seconds
Started Sep 09 06:10:50 AM UTC 24
Finished Sep 09 06:12:00 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156681876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4156681876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.40244935
Short name T617
Test name
Test status
Simulation time 4129997494 ps
CPU time 4.65 seconds
Started Sep 09 06:10:44 AM UTC 24
Finished Sep 09 06:10:50 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40244935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.40244935
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.133826016
Short name T611
Test name
Test status
Simulation time 6017334272 ps
CPU time 13.03 seconds
Started Sep 09 06:09:12 AM UTC 24
Finished Sep 09 06:09:26 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133826016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.133826016
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.3095558348
Short name T638
Test name
Test status
Simulation time 201737740311 ps
CPU time 150.7 seconds
Started Sep 09 06:10:54 AM UTC 24
Finished Sep 09 06:13:28 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095558348 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.3095558348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2945406639
Short name T620
Test name
Test status
Simulation time 5470214699 ps
CPU time 7.16 seconds
Started Sep 09 06:10:51 AM UTC 24
Finished Sep 09 06:10:59 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2945406639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.adc_ctrl_stress_all_with_rand_reset.2945406639
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.3266467076
Short name T632
Test name
Test status
Simulation time 417878883 ps
CPU time 1.28 seconds
Started Sep 09 06:12:06 AM UTC 24
Finished Sep 09 06:12:09 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266467076 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3266467076
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.1088625005
Short name T247
Test name
Test status
Simulation time 549625573555 ps
CPU time 304.97 seconds
Started Sep 09 06:11:35 AM UTC 24
Finished Sep 09 06:16:43 AM UTC 24
Peak memory 211792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088625005 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.1088625005
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.2627772315
Short name T199
Test name
Test status
Simulation time 334452145305 ps
CPU time 110.23 seconds
Started Sep 09 06:11:41 AM UTC 24
Finished Sep 09 06:13:33 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627772315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2627772315
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.2677486616
Short name T340
Test name
Test status
Simulation time 326668541090 ps
CPU time 1082.18 seconds
Started Sep 09 06:11:23 AM UTC 24
Finished Sep 09 06:29:37 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677486616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2677486616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.881199243
Short name T713
Test name
Test status
Simulation time 322346717316 ps
CPU time 687.69 seconds
Started Sep 09 06:11:29 AM UTC 24
Finished Sep 09 06:23:03 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881199243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.881199243
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.2425367030
Short name T738
Test name
Test status
Simulation time 330837588006 ps
CPU time 871.3 seconds
Started Sep 09 06:11:09 AM UTC 24
Finished Sep 09 06:25:50 AM UTC 24
Peak memory 212600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425367030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2425367030
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.4177482665
Short name T737
Test name
Test status
Simulation time 332789337169 ps
CPU time 855.07 seconds
Started Sep 09 06:11:20 AM UTC 24
Finished Sep 09 06:25:44 AM UTC 24
Peak memory 212680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177482665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.4177482665
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.1316852287
Short name T354
Test name
Test status
Simulation time 367783453833 ps
CPU time 1072.87 seconds
Started Sep 09 06:11:31 AM UTC 24
Finished Sep 09 06:29:34 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316852287 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.1316852287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1794762702
Short name T653
Test name
Test status
Simulation time 379783458932 ps
CPU time 261.32 seconds
Started Sep 09 06:11:34 AM UTC 24
Finished Sep 09 06:15:58 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794762702 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.1794762702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.4198512997
Short name T684
Test name
Test status
Simulation time 116208101651 ps
CPU time 453.95 seconds
Started Sep 09 06:11:53 AM UTC 24
Finished Sep 09 06:19:31 AM UTC 24
Peak memory 212020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198512997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4198512997
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.1383298701
Short name T642
Test name
Test status
Simulation time 44262346653 ps
CPU time 134.56 seconds
Started Sep 09 06:11:49 AM UTC 24
Finished Sep 09 06:14:06 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383298701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1383298701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.2107554235
Short name T630
Test name
Test status
Simulation time 2960037928 ps
CPU time 3.77 seconds
Started Sep 09 06:11:44 AM UTC 24
Finished Sep 09 06:11:49 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107554235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2107554235
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.4279665508
Short name T626
Test name
Test status
Simulation time 5755788955 ps
CPU time 24.48 seconds
Started Sep 09 06:11:04 AM UTC 24
Finished Sep 09 06:11:30 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279665508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4279665508
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.2232388547
Short name T686
Test name
Test status
Simulation time 169480174629 ps
CPU time 470.53 seconds
Started Sep 09 06:12:04 AM UTC 24
Finished Sep 09 06:20:00 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232388547 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.2232388547
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.2626402919
Short name T37
Test name
Test status
Simulation time 405121452 ps
CPU time 3.08 seconds
Started Sep 09 05:20:59 AM UTC 24
Finished Sep 09 05:21:03 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626402919 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2626402919
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.1285334883
Short name T148
Test name
Test status
Simulation time 352270758573 ps
CPU time 698.05 seconds
Started Sep 09 05:20:41 AM UTC 24
Finished Sep 09 05:32:26 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285334883 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.1285334883
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.3147386005
Short name T133
Test name
Test status
Simulation time 207234111663 ps
CPU time 671.14 seconds
Started Sep 09 05:20:46 AM UTC 24
Finished Sep 09 05:32:04 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147386005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3147386005
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.2323602062
Short name T146
Test name
Test status
Simulation time 165263075022 ps
CPU time 227.82 seconds
Started Sep 09 05:20:29 AM UTC 24
Finished Sep 09 05:24:20 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323602062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2323602062
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.607526176
Short name T405
Test name
Test status
Simulation time 331331741693 ps
CPU time 779.16 seconds
Started Sep 09 05:20:31 AM UTC 24
Finished Sep 09 05:33:38 AM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607526176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.607526176
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.636526180
Short name T300
Test name
Test status
Simulation time 166458808513 ps
CPU time 541.48 seconds
Started Sep 09 05:20:23 AM UTC 24
Finished Sep 09 05:29:31 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636526180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.636526180
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3410463181
Short name T174
Test name
Test status
Simulation time 329522509486 ps
CPU time 182.96 seconds
Started Sep 09 05:20:24 AM UTC 24
Finished Sep 09 05:23:30 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410463181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.3410463181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2407035595
Short name T484
Test name
Test status
Simulation time 586810982212 ps
CPU time 1661.98 seconds
Started Sep 09 05:20:38 AM UTC 24
Finished Sep 09 05:48:36 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407035595 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.2407035595
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1686510970
Short name T53
Test name
Test status
Simulation time 97259642073 ps
CPU time 461.71 seconds
Started Sep 09 05:20:53 AM UTC 24
Finished Sep 09 05:28:40 AM UTC 24
Peak memory 211888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686510970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1686510970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.1008717356
Short name T38
Test name
Test status
Simulation time 34994169118 ps
CPU time 20.52 seconds
Started Sep 09 05:20:52 AM UTC 24
Finished Sep 09 05:21:14 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008717356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1008717356
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1023288637
Short name T36
Test name
Test status
Simulation time 3692521248 ps
CPU time 2.99 seconds
Started Sep 09 05:20:50 AM UTC 24
Finished Sep 09 05:20:54 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023288637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1023288637
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.1438280795
Short name T84
Test name
Test status
Simulation time 4655267957 ps
CPU time 24.61 seconds
Started Sep 09 05:20:58 AM UTC 24
Finished Sep 09 05:21:24 AM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438280795 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1438280795
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.893337934
Short name T35
Test name
Test status
Simulation time 5582518505 ps
CPU time 29.8 seconds
Started Sep 09 05:20:21 AM UTC 24
Finished Sep 09 05:20:52 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893337934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.893337934
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3891593194
Short name T184
Test name
Test status
Simulation time 488625746143 ps
CPU time 640.43 seconds
Started Sep 09 05:20:55 AM UTC 24
Finished Sep 09 05:31:42 AM UTC 24
Peak memory 211660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891593194 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.3891593194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3321518026
Short name T16
Test name
Test status
Simulation time 4158312202 ps
CPU time 9.12 seconds
Started Sep 09 05:20:54 AM UTC 24
Finished Sep 09 05:21:04 AM UTC 24
Peak memory 221680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3321518026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.adc_ctrl_stress_all_with_rand_reset.3321518026
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.3065983466
Short name T640
Test name
Test status
Simulation time 528700634 ps
CPU time 1.31 seconds
Started Sep 09 06:13:38 AM UTC 24
Finished Sep 09 06:13:41 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065983466 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3065983466
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.2119019215
Short name T649
Test name
Test status
Simulation time 166461529295 ps
CPU time 151.31 seconds
Started Sep 09 06:12:37 AM UTC 24
Finished Sep 09 06:15:10 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119019215 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.2119019215
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.2850651164
Short name T286
Test name
Test status
Simulation time 194946516685 ps
CPU time 533.77 seconds
Started Sep 09 06:12:55 AM UTC 24
Finished Sep 09 06:21:54 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850651164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2850651164
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.923791535
Short name T680
Test name
Test status
Simulation time 170355705905 ps
CPU time 413.86 seconds
Started Sep 09 06:12:15 AM UTC 24
Finished Sep 09 06:19:14 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923791535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.923791535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1928427201
Short name T667
Test name
Test status
Simulation time 330376265736 ps
CPU time 293.13 seconds
Started Sep 09 06:12:17 AM UTC 24
Finished Sep 09 06:17:14 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928427201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.1928427201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.1618842124
Short name T699
Test name
Test status
Simulation time 166651921992 ps
CPU time 514.78 seconds
Started Sep 09 06:12:11 AM UTC 24
Finished Sep 09 06:20:52 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618842124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1618842124
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.1902124618
Short name T716
Test name
Test status
Simulation time 503580598720 ps
CPU time 665.39 seconds
Started Sep 09 06:12:12 AM UTC 24
Finished Sep 09 06:23:25 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902124618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.1902124618
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.2796010261
Short name T334
Test name
Test status
Simulation time 468302969805 ps
CPU time 1279.77 seconds
Started Sep 09 06:12:24 AM UTC 24
Finished Sep 09 06:33:56 AM UTC 24
Peak memory 212816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796010261 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.2796010261
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4191682324
Short name T731
Test name
Test status
Simulation time 195961444324 ps
CPU time 721.79 seconds
Started Sep 09 06:12:33 AM UTC 24
Finished Sep 09 06:24:42 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191682324 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.4191682324
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.2572437294
Short name T651
Test name
Test status
Simulation time 36434843943 ps
CPU time 153.76 seconds
Started Sep 09 06:13:06 AM UTC 24
Finished Sep 09 06:15:42 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572437294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2572437294
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.940919943
Short name T637
Test name
Test status
Simulation time 3592681835 ps
CPU time 14.8 seconds
Started Sep 09 06:13:03 AM UTC 24
Finished Sep 09 06:13:19 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940919943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.940919943
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.1484087058
Short name T636
Test name
Test status
Simulation time 5641428441 ps
CPU time 25.27 seconds
Started Sep 09 06:12:09 AM UTC 24
Finished Sep 09 06:12:36 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484087058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1484087058
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.3389248229
Short name T670
Test name
Test status
Simulation time 328553623572 ps
CPU time 249.4 seconds
Started Sep 09 06:13:34 AM UTC 24
Finished Sep 09 06:17:47 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389248229 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.3389248229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.771025039
Short name T654
Test name
Test status
Simulation time 502203865 ps
CPU time 1.9 seconds
Started Sep 09 06:15:57 AM UTC 24
Finished Sep 09 06:16:00 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771025039 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.771025039
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.3865030970
Short name T746
Test name
Test status
Simulation time 446505067097 ps
CPU time 705.97 seconds
Started Sep 09 06:14:36 AM UTC 24
Finished Sep 09 06:26:29 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865030970 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.3865030970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.2799345535
Short name T296
Test name
Test status
Simulation time 491696442538 ps
CPU time 1175.14 seconds
Started Sep 09 06:14:07 AM UTC 24
Finished Sep 09 06:33:53 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799345535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2799345535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3544419320
Short name T672
Test name
Test status
Simulation time 497430604853 ps
CPU time 211.18 seconds
Started Sep 09 06:14:28 AM UTC 24
Finished Sep 09 06:18:02 AM UTC 24
Peak memory 211592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544419320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.3544419320
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.2562401105
Short name T675
Test name
Test status
Simulation time 163458632546 ps
CPU time 292.29 seconds
Started Sep 09 06:13:42 AM UTC 24
Finished Sep 09 06:18:39 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562401105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2562401105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.3470059468
Short name T783
Test name
Test status
Simulation time 491850982097 ps
CPU time 1371.13 seconds
Started Sep 09 06:13:50 AM UTC 24
Finished Sep 09 06:36:54 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470059468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.3470059468
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.3986182695
Short name T662
Test name
Test status
Simulation time 174410410352 ps
CPU time 129.29 seconds
Started Sep 09 06:14:29 AM UTC 24
Finished Sep 09 06:16:40 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986182695 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.3986182695
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1735663432
Short name T781
Test name
Test status
Simulation time 394881074720 ps
CPU time 1255.87 seconds
Started Sep 09 06:14:33 AM UTC 24
Finished Sep 09 06:35:42 AM UTC 24
Peak memory 212824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735663432 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.1735663432
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.2943180454
Short name T709
Test name
Test status
Simulation time 102199051844 ps
CPU time 424.08 seconds
Started Sep 09 06:15:19 AM UTC 24
Finished Sep 09 06:22:28 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943180454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2943180454
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.3679443654
Short name T669
Test name
Test status
Simulation time 36941725758 ps
CPU time 145.15 seconds
Started Sep 09 06:15:11 AM UTC 24
Finished Sep 09 06:17:39 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679443654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3679443654
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.2079775858
Short name T650
Test name
Test status
Simulation time 5237227956 ps
CPU time 13.9 seconds
Started Sep 09 06:15:03 AM UTC 24
Finished Sep 09 06:15:18 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079775858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2079775858
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.3828895962
Short name T641
Test name
Test status
Simulation time 6021555502 ps
CPU time 6.71 seconds
Started Sep 09 06:13:41 AM UTC 24
Finished Sep 09 06:13:49 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828895962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3828895962
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.3214456376
Short name T792
Test name
Test status
Simulation time 455882616293 ps
CPU time 1697.18 seconds
Started Sep 09 06:15:46 AM UTC 24
Finished Sep 09 06:44:18 AM UTC 24
Peak memory 223068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214456376 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.3214456376
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1113057997
Short name T657
Test name
Test status
Simulation time 8254806351 ps
CPU time 29.49 seconds
Started Sep 09 06:15:44 AM UTC 24
Finished Sep 09 06:16:14 AM UTC 24
Peak memory 221752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1113057997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.adc_ctrl_stress_all_with_rand_reset.1113057997
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.943975867
Short name T666
Test name
Test status
Simulation time 527782482 ps
CPU time 1.53 seconds
Started Sep 09 06:17:11 AM UTC 24
Finished Sep 09 06:17:13 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943975867 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.943975867
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.4230251354
Short name T277
Test name
Test status
Simulation time 171636043951 ps
CPU time 330.32 seconds
Started Sep 09 06:16:30 AM UTC 24
Finished Sep 09 06:22:05 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230251354 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.4230251354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.2158828793
Short name T674
Test name
Test status
Simulation time 169646109401 ps
CPU time 107.97 seconds
Started Sep 09 06:16:39 AM UTC 24
Finished Sep 09 06:18:29 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158828793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2158828793
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.3036675623
Short name T712
Test name
Test status
Simulation time 329055741916 ps
CPU time 402.25 seconds
Started Sep 09 06:16:13 AM UTC 24
Finished Sep 09 06:23:00 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036675623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3036675623
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3941046676
Short name T736
Test name
Test status
Simulation time 166904542379 ps
CPU time 556.62 seconds
Started Sep 09 06:16:15 AM UTC 24
Finished Sep 09 06:25:38 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941046676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.3941046676
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.19918234
Short name T759
Test name
Test status
Simulation time 481845510111 ps
CPU time 760.47 seconds
Started Sep 09 06:15:59 AM UTC 24
Finished Sep 09 06:28:47 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19918234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.19918234
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.3905366114
Short name T701
Test name
Test status
Simulation time 325679910826 ps
CPU time 326.86 seconds
Started Sep 09 06:16:01 AM UTC 24
Finished Sep 09 06:21:32 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905366114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.3905366114
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.484046524
Short name T353
Test name
Test status
Simulation time 522380579954 ps
CPU time 1336.32 seconds
Started Sep 09 06:16:15 AM UTC 24
Finished Sep 09 06:38:45 AM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484046524 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.484046524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3343471677
Short name T749
Test name
Test status
Simulation time 200493777810 ps
CPU time 648.24 seconds
Started Sep 09 06:16:18 AM UTC 24
Finished Sep 09 06:27:14 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343471677 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.3343471677
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.3090248142
Short name T735
Test name
Test status
Simulation time 117486173945 ps
CPU time 514.43 seconds
Started Sep 09 06:16:45 AM UTC 24
Finished Sep 09 06:25:24 AM UTC 24
Peak memory 211780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090248142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3090248142
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.1661284982
Short name T663
Test name
Test status
Simulation time 32329217719 ps
CPU time 12.45 seconds
Started Sep 09 06:16:41 AM UTC 24
Finished Sep 09 06:16:55 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661284982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1661284982
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.2450649369
Short name T664
Test name
Test status
Simulation time 5084961788 ps
CPU time 20.89 seconds
Started Sep 09 06:16:40 AM UTC 24
Finished Sep 09 06:17:02 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450649369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2450649369
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.2696210629
Short name T655
Test name
Test status
Simulation time 6008913179 ps
CPU time 13.36 seconds
Started Sep 09 06:15:58 AM UTC 24
Finished Sep 09 06:16:12 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696210629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2696210629
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.2359475826
Short name T753
Test name
Test status
Simulation time 93932940752 ps
CPU time 646.18 seconds
Started Sep 09 06:17:04 AM UTC 24
Finished Sep 09 06:27:57 AM UTC 24
Peak memory 211792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359475826 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.2359475826
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2934972885
Short name T671
Test name
Test status
Simulation time 165389191339 ps
CPU time 53.68 seconds
Started Sep 09 06:16:56 AM UTC 24
Finished Sep 09 06:17:51 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2934972885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.adc_ctrl_stress_all_with_rand_reset.2934972885
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.1716958022
Short name T682
Test name
Test status
Simulation time 335447422 ps
CPU time 1.59 seconds
Started Sep 09 06:19:15 AM UTC 24
Finished Sep 09 06:19:18 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716958022 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1716958022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.441690084
Short name T726
Test name
Test status
Simulation time 163231088548 ps
CPU time 355.43 seconds
Started Sep 09 06:18:16 AM UTC 24
Finished Sep 09 06:24:16 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441690084 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.441690084
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.696416018
Short name T181
Test name
Test status
Simulation time 326099781892 ps
CPU time 130.97 seconds
Started Sep 09 06:17:39 AM UTC 24
Finished Sep 09 06:19:53 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696416018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.696416018
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2804260678
Short name T723
Test name
Test status
Simulation time 500867630668 ps
CPU time 355.09 seconds
Started Sep 09 06:17:48 AM UTC 24
Finished Sep 09 06:23:47 AM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804260678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.2804260678
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.1642609100
Short name T696
Test name
Test status
Simulation time 161848325372 ps
CPU time 192.14 seconds
Started Sep 09 06:17:23 AM UTC 24
Finished Sep 09 06:20:38 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642609100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.1642609100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.694736931
Short name T790
Test name
Test status
Simulation time 600375399974 ps
CPU time 1443.36 seconds
Started Sep 09 06:18:02 AM UTC 24
Finished Sep 09 06:42:19 AM UTC 24
Peak memory 212876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694736931 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.694736931
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.1112479159
Short name T756
Test name
Test status
Simulation time 120223550376 ps
CPU time 576.06 seconds
Started Sep 09 06:18:45 AM UTC 24
Finished Sep 09 06:28:27 AM UTC 24
Peak memory 211892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112479159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1112479159
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.2569392443
Short name T679
Test name
Test status
Simulation time 32632061049 ps
CPU time 24.8 seconds
Started Sep 09 06:18:41 AM UTC 24
Finished Sep 09 06:19:07 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569392443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2569392443
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.1395331682
Short name T677
Test name
Test status
Simulation time 4757725389 ps
CPU time 3.74 seconds
Started Sep 09 06:18:40 AM UTC 24
Finished Sep 09 06:18:44 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395331682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1395331682
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.1892944948
Short name T668
Test name
Test status
Simulation time 6022640569 ps
CPU time 6.84 seconds
Started Sep 09 06:17:14 AM UTC 24
Finished Sep 09 06:17:22 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892944948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1892944948
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.3548472653
Short name T248
Test name
Test status
Simulation time 176843381643 ps
CPU time 666.61 seconds
Started Sep 09 06:19:08 AM UTC 24
Finished Sep 09 06:30:22 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548472653 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.3548472653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3741816938
Short name T681
Test name
Test status
Simulation time 29862255169 ps
CPU time 13.88 seconds
Started Sep 09 06:19:02 AM UTC 24
Finished Sep 09 06:19:17 AM UTC 24
Peak memory 211732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3741816938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.adc_ctrl_stress_all_with_rand_reset.3741816938
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.420371461
Short name T694
Test name
Test status
Simulation time 352514688 ps
CPU time 1.58 seconds
Started Sep 09 06:20:28 AM UTC 24
Finished Sep 09 06:20:31 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420371461 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.420371461
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.2643129804
Short name T748
Test name
Test status
Simulation time 160230017065 ps
CPU time 399.91 seconds
Started Sep 09 06:20:01 AM UTC 24
Finished Sep 09 06:26:46 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643129804 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.2643129804
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.346032132
Short name T793
Test name
Test status
Simulation time 547049490256 ps
CPU time 1466.82 seconds
Started Sep 09 06:20:04 AM UTC 24
Finished Sep 09 06:44:45 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346032132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.346032132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.579745093
Short name T727
Test name
Test status
Simulation time 493179443613 ps
CPU time 283.78 seconds
Started Sep 09 06:19:32 AM UTC 24
Finished Sep 09 06:24:20 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579745093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.579745093
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1899517516
Short name T728
Test name
Test status
Simulation time 496233427159 ps
CPU time 284.84 seconds
Started Sep 09 06:19:32 AM UTC 24
Finished Sep 09 06:24:21 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899517516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.1899517516
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.2327032930
Short name T720
Test name
Test status
Simulation time 164684401702 ps
CPU time 255.73 seconds
Started Sep 09 06:19:19 AM UTC 24
Finished Sep 09 06:23:39 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327032930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2327032930
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.2435708219
Short name T732
Test name
Test status
Simulation time 484158684211 ps
CPU time 320.44 seconds
Started Sep 09 06:19:24 AM UTC 24
Finished Sep 09 06:24:49 AM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435708219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.2435708219
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.2481562994
Short name T706
Test name
Test status
Simulation time 175141818591 ps
CPU time 150.9 seconds
Started Sep 09 06:19:38 AM UTC 24
Finished Sep 09 06:22:12 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481562994 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.2481562994
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1754338856
Short name T797
Test name
Test status
Simulation time 596466428071 ps
CPU time 1722.02 seconds
Started Sep 09 06:19:54 AM UTC 24
Finished Sep 09 06:48:53 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754338856 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.1754338856
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.2226149350
Short name T769
Test name
Test status
Simulation time 121135568760 ps
CPU time 580.49 seconds
Started Sep 09 06:20:15 AM UTC 24
Finished Sep 09 06:30:01 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226149350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2226149350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.1347689123
Short name T698
Test name
Test status
Simulation time 42514696899 ps
CPU time 39.66 seconds
Started Sep 09 06:20:11 AM UTC 24
Finished Sep 09 06:20:52 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347689123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1347689123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.1713759457
Short name T690
Test name
Test status
Simulation time 4959838813 ps
CPU time 6.34 seconds
Started Sep 09 06:20:07 AM UTC 24
Finished Sep 09 06:20:14 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713759457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1713759457
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.1484246844
Short name T683
Test name
Test status
Simulation time 5698802267 ps
CPU time 3.84 seconds
Started Sep 09 06:19:18 AM UTC 24
Finished Sep 09 06:19:23 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484246844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1484246844
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.1493196791
Short name T273
Test name
Test status
Simulation time 664975296917 ps
CPU time 1057.58 seconds
Started Sep 09 06:20:28 AM UTC 24
Finished Sep 09 06:38:16 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493196791 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.1493196791
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3273815990
Short name T695
Test name
Test status
Simulation time 16327390143 ps
CPU time 15.67 seconds
Started Sep 09 06:20:20 AM UTC 24
Finished Sep 09 06:20:37 AM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3273815990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.adc_ctrl_stress_all_with_rand_reset.3273815990
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.1972208539
Short name T704
Test name
Test status
Simulation time 284808825 ps
CPU time 2 seconds
Started Sep 09 06:21:47 AM UTC 24
Finished Sep 09 06:21:50 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972208539 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1972208539
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.4035235262
Short name T347
Test name
Test status
Simulation time 495825302356 ps
CPU time 1410.49 seconds
Started Sep 09 06:21:17 AM UTC 24
Finished Sep 09 06:45:01 AM UTC 24
Peak memory 212512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035235262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4035235262
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.3199878185
Short name T356
Test name
Test status
Simulation time 497937754284 ps
CPU time 1259.49 seconds
Started Sep 09 06:20:39 AM UTC 24
Finished Sep 09 06:41:51 AM UTC 24
Peak memory 212820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199878185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3199878185
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1254623810
Short name T796
Test name
Test status
Simulation time 497519858494 ps
CPU time 1620.84 seconds
Started Sep 09 06:20:50 AM UTC 24
Finished Sep 09 06:48:06 AM UTC 24
Peak memory 212584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254623810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.1254623810
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.3967529213
Short name T722
Test name
Test status
Simulation time 326749507040 ps
CPU time 189.75 seconds
Started Sep 09 06:20:33 AM UTC 24
Finished Sep 09 06:23:46 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967529213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3967529213
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.1464096041
Short name T718
Test name
Test status
Simulation time 164401053349 ps
CPU time 173.32 seconds
Started Sep 09 06:20:37 AM UTC 24
Finished Sep 09 06:23:33 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464096041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.1464096041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.3178840330
Short name T717
Test name
Test status
Simulation time 215646336525 ps
CPU time 156.85 seconds
Started Sep 09 06:20:51 AM UTC 24
Finished Sep 09 06:23:30 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178840330 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.3178840330
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2411114719
Short name T778
Test name
Test status
Simulation time 599863551360 ps
CPU time 757.43 seconds
Started Sep 09 06:20:53 AM UTC 24
Finished Sep 09 06:33:39 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411114719 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.2411114719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.1320355080
Short name T770
Test name
Test status
Simulation time 126462290317 ps
CPU time 509.16 seconds
Started Sep 09 06:21:32 AM UTC 24
Finished Sep 09 06:30:06 AM UTC 24
Peak memory 212084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320355080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1320355080
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.1096044951
Short name T705
Test name
Test status
Simulation time 22226240670 ps
CPU time 29.98 seconds
Started Sep 09 06:21:28 AM UTC 24
Finished Sep 09 06:21:59 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096044951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1096044951
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.3828292269
Short name T703
Test name
Test status
Simulation time 4208199324 ps
CPU time 18.78 seconds
Started Sep 09 06:21:27 AM UTC 24
Finished Sep 09 06:21:47 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828292269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3828292269
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.3767422997
Short name T697
Test name
Test status
Simulation time 5893133708 ps
CPU time 17.26 seconds
Started Sep 09 06:20:31 AM UTC 24
Finished Sep 09 06:20:50 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767422997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3767422997
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.3803330993
Short name T708
Test name
Test status
Simulation time 17691433667 ps
CPU time 37.82 seconds
Started Sep 09 06:21:46 AM UTC 24
Finished Sep 09 06:22:26 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803330993 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.3803330993
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1762368686
Short name T702
Test name
Test status
Simulation time 807934244 ps
CPU time 4.42 seconds
Started Sep 09 06:21:40 AM UTC 24
Finished Sep 09 06:21:46 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1762368686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.adc_ctrl_stress_all_with_rand_reset.1762368686
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.731044880
Short name T715
Test name
Test status
Simulation time 334424094 ps
CPU time 1.24 seconds
Started Sep 09 06:23:09 AM UTC 24
Finished Sep 09 06:23:12 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731044880 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.731044880
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.221173893
Short name T789
Test name
Test status
Simulation time 496992740006 ps
CPU time 1165.91 seconds
Started Sep 09 06:22:26 AM UTC 24
Finished Sep 09 06:42:04 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221173893 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.221173893
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.2287100643
Short name T745
Test name
Test status
Simulation time 193390571507 ps
CPU time 237.45 seconds
Started Sep 09 06:22:28 AM UTC 24
Finished Sep 09 06:26:29 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287100643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2287100643
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.975722814
Short name T782
Test name
Test status
Simulation time 334095977003 ps
CPU time 850.51 seconds
Started Sep 09 06:22:06 AM UTC 24
Finished Sep 09 06:36:25 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975722814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.975722814
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3427540297
Short name T775
Test name
Test status
Simulation time 165478130441 ps
CPU time 642.08 seconds
Started Sep 09 06:22:12 AM UTC 24
Finished Sep 09 06:33:01 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427540297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.3427540297
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.3954691264
Short name T747
Test name
Test status
Simulation time 166377152492 ps
CPU time 272.39 seconds
Started Sep 09 06:22:01 AM UTC 24
Finished Sep 09 06:26:37 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954691264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.3954691264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.719293778
Short name T758
Test name
Test status
Simulation time 182588995715 ps
CPU time 376.07 seconds
Started Sep 09 06:22:13 AM UTC 24
Finished Sep 09 06:28:34 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719293778 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.719293778
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2908945457
Short name T798
Test name
Test status
Simulation time 590695187863 ps
CPU time 1598.67 seconds
Started Sep 09 06:22:20 AM UTC 24
Finished Sep 09 06:49:14 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908945457 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.2908945457
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.3023900580
Short name T771
Test name
Test status
Simulation time 99520962977 ps
CPU time 492.55 seconds
Started Sep 09 06:22:47 AM UTC 24
Finished Sep 09 06:31:05 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023900580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3023900580
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.3783948391
Short name T714
Test name
Test status
Simulation time 28777455261 ps
CPU time 21.5 seconds
Started Sep 09 06:22:46 AM UTC 24
Finished Sep 09 06:23:09 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783948391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3783948391
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.4268233672
Short name T711
Test name
Test status
Simulation time 5048870326 ps
CPU time 11.75 seconds
Started Sep 09 06:22:32 AM UTC 24
Finished Sep 09 06:22:45 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268233672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4268233672
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.167058838
Short name T707
Test name
Test status
Simulation time 5907656825 ps
CPU time 26.82 seconds
Started Sep 09 06:21:51 AM UTC 24
Finished Sep 09 06:22:19 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167058838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.167058838
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.3248104281
Short name T791
Test name
Test status
Simulation time 660475514646 ps
CPU time 1226.89 seconds
Started Sep 09 06:23:04 AM UTC 24
Finished Sep 09 06:43:44 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248104281 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.3248104281
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2389218259
Short name T719
Test name
Test status
Simulation time 58852450639 ps
CPU time 34.36 seconds
Started Sep 09 06:23:00 AM UTC 24
Finished Sep 09 06:23:36 AM UTC 24
Peak memory 221892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2389218259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.adc_ctrl_stress_all_with_rand_reset.2389218259
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.2019211894
Short name T729
Test name
Test status
Simulation time 313216554 ps
CPU time 1.18 seconds
Started Sep 09 06:24:22 AM UTC 24
Finished Sep 09 06:24:24 AM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019211894 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2019211894
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.3340341786
Short name T772
Test name
Test status
Simulation time 167943690848 ps
CPU time 446.49 seconds
Started Sep 09 06:23:41 AM UTC 24
Finished Sep 09 06:31:13 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340341786 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.3340341786
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.1350027613
Short name T788
Test name
Test status
Simulation time 331321582247 ps
CPU time 1012.24 seconds
Started Sep 09 06:23:47 AM UTC 24
Finished Sep 09 06:40:50 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350027613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1350027613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.680288464
Short name T776
Test name
Test status
Simulation time 166139322917 ps
CPU time 571.37 seconds
Started Sep 09 06:23:31 AM UTC 24
Finished Sep 09 06:33:09 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680288464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.680288464
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3587322094
Short name T752
Test name
Test status
Simulation time 493130554706 ps
CPU time 248.69 seconds
Started Sep 09 06:23:34 AM UTC 24
Finished Sep 09 06:27:46 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587322094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.3587322094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.1168919431
Short name T787
Test name
Test status
Simulation time 320364716626 ps
CPU time 933.08 seconds
Started Sep 09 06:23:25 AM UTC 24
Finished Sep 09 06:39:07 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168919431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1168919431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.1754552516
Short name T762
Test name
Test status
Simulation time 163010090884 ps
CPU time 336.64 seconds
Started Sep 09 06:23:26 AM UTC 24
Finished Sep 09 06:29:07 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754552516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.1754552516
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.1263564482
Short name T799
Test name
Test status
Simulation time 549970852615 ps
CPU time 1559.27 seconds
Started Sep 09 06:23:37 AM UTC 24
Finished Sep 09 06:49:52 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263564482 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.1263564482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2785726608
Short name T730
Test name
Test status
Simulation time 199838413536 ps
CPU time 43.73 seconds
Started Sep 09 06:23:40 AM UTC 24
Finished Sep 09 06:24:25 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785726608 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.2785726608
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.2481816139
Short name T766
Test name
Test status
Simulation time 75365477416 ps
CPU time 333.35 seconds
Started Sep 09 06:23:57 AM UTC 24
Finished Sep 09 06:29:34 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481816139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2481816139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.25661346
Short name T734
Test name
Test status
Simulation time 33936688087 ps
CPU time 62.07 seconds
Started Sep 09 06:23:52 AM UTC 24
Finished Sep 09 06:24:56 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25661346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.25661346
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.1975536780
Short name T724
Test name
Test status
Simulation time 4180634164 ps
CPU time 1.88 seconds
Started Sep 09 06:23:48 AM UTC 24
Finished Sep 09 06:23:51 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975536780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1975536780
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.1026833100
Short name T721
Test name
Test status
Simulation time 5938565291 ps
CPU time 26.68 seconds
Started Sep 09 06:23:13 AM UTC 24
Finished Sep 09 06:23:40 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026833100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1026833100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.2852703317
Short name T800
Test name
Test status
Simulation time 718488531452 ps
CPU time 2836.27 seconds
Started Sep 09 06:24:20 AM UTC 24
Finished Sep 09 07:12:05 AM UTC 24
Peak memory 225116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852703317 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.2852703317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.4055872983
Short name T358
Test name
Test status
Simulation time 21123555412 ps
CPU time 37.72 seconds
Started Sep 09 06:24:17 AM UTC 24
Finished Sep 09 06:24:57 AM UTC 24
Peak memory 221944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4055872983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.adc_ctrl_stress_all_with_rand_reset.4055872983
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.41368073
Short name T743
Test name
Test status
Simulation time 355409912 ps
CPU time 2.37 seconds
Started Sep 09 06:26:07 AM UTC 24
Finished Sep 09 06:26:10 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41368073 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.41368073
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.191381675
Short name T349
Test name
Test status
Simulation time 532568822220 ps
CPU time 258.29 seconds
Started Sep 09 06:25:25 AM UTC 24
Finished Sep 09 06:29:47 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191381675 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.191381675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2521282140
Short name T765
Test name
Test status
Simulation time 166769420794 ps
CPU time 219.99 seconds
Started Sep 09 06:25:38 AM UTC 24
Finished Sep 09 06:29:21 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521282140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2521282140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.2149137660
Short name T346
Test name
Test status
Simulation time 502149467268 ps
CPU time 1536.02 seconds
Started Sep 09 06:24:50 AM UTC 24
Finished Sep 09 06:50:41 AM UTC 24
Peak memory 212540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149137660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2149137660
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1669351333
Short name T779
Test name
Test status
Simulation time 483778513555 ps
CPU time 525.86 seconds
Started Sep 09 06:24:50 AM UTC 24
Finished Sep 09 06:33:41 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669351333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.1669351333
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.2579284032
Short name T760
Test name
Test status
Simulation time 165226647550 ps
CPU time 267.34 seconds
Started Sep 09 06:24:26 AM UTC 24
Finished Sep 09 06:28:57 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579284032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2579284032
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.33194877
Short name T757
Test name
Test status
Simulation time 324846077759 ps
CPU time 220.88 seconds
Started Sep 09 06:24:43 AM UTC 24
Finished Sep 09 06:28:27 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33194877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.33194877
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.3280543941
Short name T794
Test name
Test status
Simulation time 368902911758 ps
CPU time 1233.95 seconds
Started Sep 09 06:24:57 AM UTC 24
Finished Sep 09 06:45:44 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280543941 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.3280543941
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3148984013
Short name T786
Test name
Test status
Simulation time 597267586686 ps
CPU time 795.93 seconds
Started Sep 09 06:24:58 AM UTC 24
Finished Sep 09 06:38:22 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148984013 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.3148984013
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.2339125229
Short name T773
Test name
Test status
Simulation time 82351514358 ps
CPU time 341.44 seconds
Started Sep 09 06:25:51 AM UTC 24
Finished Sep 09 06:31:36 AM UTC 24
Peak memory 211700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339125229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2339125229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.2307903258
Short name T750
Test name
Test status
Simulation time 43398961736 ps
CPU time 92.26 seconds
Started Sep 09 06:25:51 AM UTC 24
Finished Sep 09 06:27:25 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307903258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2307903258
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.364454251
Short name T739
Test name
Test status
Simulation time 2928968924 ps
CPU time 3.89 seconds
Started Sep 09 06:25:44 AM UTC 24
Finished Sep 09 06:25:50 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364454251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.364454251
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.43724191
Short name T733
Test name
Test status
Simulation time 5658899249 ps
CPU time 23.33 seconds
Started Sep 09 06:24:25 AM UTC 24
Finished Sep 09 06:24:49 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43724191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.43724191
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.931070868
Short name T795
Test name
Test status
Simulation time 415916038000 ps
CPU time 1210.76 seconds
Started Sep 09 06:26:03 AM UTC 24
Finished Sep 09 06:46:25 AM UTC 24
Peak memory 222824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931070868 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.931070868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.302215721
Short name T742
Test name
Test status
Simulation time 2635707659 ps
CPU time 6.82 seconds
Started Sep 09 06:25:58 AM UTC 24
Finished Sep 09 06:26:06 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=302215721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
48.adc_ctrl_stress_all_with_rand_reset.302215721
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.866380491
Short name T755
Test name
Test status
Simulation time 499537339 ps
CPU time 1.37 seconds
Started Sep 09 06:28:07 AM UTC 24
Finished Sep 09 06:28:10 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866380491 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.866380491
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.602279665
Short name T774
Test name
Test status
Simulation time 492088079384 ps
CPU time 331.52 seconds
Started Sep 09 06:26:29 AM UTC 24
Finished Sep 09 06:32:05 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602279665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.602279665
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2782025826
Short name T754
Test name
Test status
Simulation time 166839878575 ps
CPU time 93.14 seconds
Started Sep 09 06:26:30 AM UTC 24
Finished Sep 09 06:28:05 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782025826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.2782025826
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.28103354
Short name T228
Test name
Test status
Simulation time 488416408249 ps
CPU time 169.3 seconds
Started Sep 09 06:26:14 AM UTC 24
Finished Sep 09 06:29:06 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28103354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.28103354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.1097400610
Short name T764
Test name
Test status
Simulation time 164296482436 ps
CPU time 170.2 seconds
Started Sep 09 06:26:18 AM UTC 24
Finished Sep 09 06:29:11 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097400610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.1097400610
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.413948046
Short name T780
Test name
Test status
Simulation time 184658362233 ps
CPU time 476.01 seconds
Started Sep 09 06:26:37 AM UTC 24
Finished Sep 09 06:34:38 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413948046 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.413948046
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.842801753
Short name T784
Test name
Test status
Simulation time 197540961285 ps
CPU time 616.8 seconds
Started Sep 09 06:26:46 AM UTC 24
Finished Sep 09 06:37:10 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842801753 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.842801753
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.1910206121
Short name T777
Test name
Test status
Simulation time 68543548159 ps
CPU time 346.78 seconds
Started Sep 09 06:27:47 AM UTC 24
Finished Sep 09 06:33:38 AM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910206121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1910206121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.997518566
Short name T761
Test name
Test status
Simulation time 26239067431 ps
CPU time 77.6 seconds
Started Sep 09 06:27:41 AM UTC 24
Finished Sep 09 06:29:00 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997518566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.997518566
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.1299800977
Short name T751
Test name
Test status
Simulation time 5141376552 ps
CPU time 6 seconds
Started Sep 09 06:27:33 AM UTC 24
Finished Sep 09 06:27:40 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299800977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1299800977
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.946180835
Short name T744
Test name
Test status
Simulation time 5851952663 ps
CPU time 5.12 seconds
Started Sep 09 06:26:11 AM UTC 24
Finished Sep 09 06:26:17 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946180835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.946180835
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1011018699
Short name T768
Test name
Test status
Simulation time 166813267246 ps
CPU time 90.34 seconds
Started Sep 09 06:28:06 AM UTC 24
Finished Sep 09 06:29:39 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011018699 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.1011018699
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2689569404
Short name T767
Test name
Test status
Simulation time 170459206816 ps
CPU time 97.17 seconds
Started Sep 09 06:27:57 AM UTC 24
Finished Sep 09 06:29:36 AM UTC 24
Peak memory 222000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2689569404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.adc_ctrl_stress_all_with_rand_reset.2689569404
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.1158828012
Short name T168
Test name
Test status
Simulation time 423270482 ps
CPU time 3.01 seconds
Started Sep 09 05:22:47 AM UTC 24
Finished Sep 09 05:22:51 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158828012 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1158828012
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.2899373971
Short name T183
Test name
Test status
Simulation time 170912925233 ps
CPU time 584.5 seconds
Started Sep 09 05:21:45 AM UTC 24
Finished Sep 09 05:31:36 AM UTC 24
Peak memory 211732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899373971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2899373971
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.3971314601
Short name T322
Test name
Test status
Simulation time 503036731722 ps
CPU time 1494.86 seconds
Started Sep 09 05:21:22 AM UTC 24
Finished Sep 09 05:46:33 AM UTC 24
Peak memory 212616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971314601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3971314601
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.633134849
Short name T153
Test name
Test status
Simulation time 156956175839 ps
CPU time 132.61 seconds
Started Sep 09 05:21:25 AM UTC 24
Finished Sep 09 05:23:40 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633134849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.633134849
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.3719744930
Short name T143
Test name
Test status
Simulation time 497526118900 ps
CPU time 516.62 seconds
Started Sep 09 05:21:05 AM UTC 24
Finished Sep 09 05:29:48 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719744930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3719744930
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.1267091291
Short name T129
Test name
Test status
Simulation time 485470727881 ps
CPU time 89.74 seconds
Started Sep 09 05:21:15 AM UTC 24
Finished Sep 09 05:22:46 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267091291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.1267091291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.3517760426
Short name T158
Test name
Test status
Simulation time 352678380976 ps
CPU time 431.02 seconds
Started Sep 09 05:21:27 AM UTC 24
Finished Sep 09 05:28:43 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517760426 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.3517760426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3525025391
Short name T425
Test name
Test status
Simulation time 399777178932 ps
CPU time 1046.41 seconds
Started Sep 09 05:21:29 AM UTC 24
Finished Sep 09 05:39:05 AM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525025391 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.3525025391
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2074908537
Short name T54
Test name
Test status
Simulation time 76575286099 ps
CPU time 368.27 seconds
Started Sep 09 05:22:18 AM UTC 24
Finished Sep 09 05:28:31 AM UTC 24
Peak memory 211832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074908537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2074908537
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.204778632
Short name T155
Test name
Test status
Simulation time 24239902968 ps
CPU time 96.39 seconds
Started Sep 09 05:22:17 AM UTC 24
Finished Sep 09 05:23:56 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204778632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.204778632
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.1752385875
Short name T167
Test name
Test status
Simulation time 2913495527 ps
CPU time 11.55 seconds
Started Sep 09 05:22:13 AM UTC 24
Finished Sep 09 05:22:26 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752385875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1752385875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.3488227746
Short name T381
Test name
Test status
Simulation time 5876981965 ps
CPU time 23.3 seconds
Started Sep 09 05:21:04 AM UTC 24
Finished Sep 09 05:21:29 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488227746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3488227746
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3978489425
Short name T218
Test name
Test status
Simulation time 529689637433 ps
CPU time 790.41 seconds
Started Sep 09 05:22:45 AM UTC 24
Finished Sep 09 05:36:03 AM UTC 24
Peak memory 223336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978489425 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.3978489425
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.4156909167
Short name T156
Test name
Test status
Simulation time 477167625 ps
CPU time 1.32 seconds
Started Sep 09 05:24:37 AM UTC 24
Finished Sep 09 05:24:39 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156909167 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4156909167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.1301841989
Short name T186
Test name
Test status
Simulation time 162988445626 ps
CPU time 508.51 seconds
Started Sep 09 05:23:37 AM UTC 24
Finished Sep 09 05:32:12 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301841989 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.1301841989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2646084167
Short name T229
Test name
Test status
Simulation time 165149174406 ps
CPU time 138.49 seconds
Started Sep 09 05:23:41 AM UTC 24
Finished Sep 09 05:26:01 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646084167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2646084167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.149117748
Short name T382
Test name
Test status
Simulation time 159780261573 ps
CPU time 158.06 seconds
Started Sep 09 05:23:28 AM UTC 24
Finished Sep 09 05:26:09 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149117748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.149117748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.2937328878
Short name T497
Test name
Test status
Simulation time 499890607388 ps
CPU time 1682.86 seconds
Started Sep 09 05:23:12 AM UTC 24
Finished Sep 09 05:51:32 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937328878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.2937328878
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2180373342
Short name T137
Test name
Test status
Simulation time 385338446857 ps
CPU time 272.27 seconds
Started Sep 09 05:23:30 AM UTC 24
Finished Sep 09 05:28:06 AM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180373342 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.2180373342
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1748285482
Short name T261
Test name
Test status
Simulation time 392620522176 ps
CPU time 88.35 seconds
Started Sep 09 05:23:35 AM UTC 24
Finished Sep 09 05:25:06 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748285482 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.1748285482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.3583913988
Short name T205
Test name
Test status
Simulation time 42153012501 ps
CPU time 196.02 seconds
Started Sep 09 05:23:55 AM UTC 24
Finished Sep 09 05:27:14 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583913988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3583913988
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.1774944850
Short name T154
Test name
Test status
Simulation time 3022628608 ps
CPU time 11.18 seconds
Started Sep 09 05:23:42 AM UTC 24
Finished Sep 09 05:23:54 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774944850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1774944850
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2679761308
Short name T169
Test name
Test status
Simulation time 5991076051 ps
CPU time 3.55 seconds
Started Sep 09 05:22:52 AM UTC 24
Finished Sep 09 05:22:56 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679761308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2679761308
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.4238171469
Short name T225
Test name
Test status
Simulation time 102548514392 ps
CPU time 657.58 seconds
Started Sep 09 05:24:36 AM UTC 24
Finished Sep 09 05:35:40 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238171469 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.4238171469
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.3922694258
Short name T201
Test name
Test status
Simulation time 489715057 ps
CPU time 2.98 seconds
Started Sep 09 05:26:33 AM UTC 24
Finished Sep 09 05:26:37 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922694258 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3922694258
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1545028286
Short name T318
Test name
Test status
Simulation time 484789162044 ps
CPU time 1642.8 seconds
Started Sep 09 05:25:17 AM UTC 24
Finished Sep 09 05:52:57 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545028286 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.1545028286
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.204801634
Short name T344
Test name
Test status
Simulation time 342501260856 ps
CPU time 1064.19 seconds
Started Sep 09 05:25:36 AM UTC 24
Finished Sep 09 05:43:31 AM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204801634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.204801634
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3670954287
Short name T396
Test name
Test status
Simulation time 481279507949 ps
CPU time 328.07 seconds
Started Sep 09 05:25:07 AM UTC 24
Finished Sep 09 05:30:39 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670954287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.3670954287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.405882904
Short name T188
Test name
Test status
Simulation time 162276108977 ps
CPU time 455.14 seconds
Started Sep 09 05:24:49 AM UTC 24
Finished Sep 09 05:32:30 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405882904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.405882904
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.4160316742
Short name T395
Test name
Test status
Simulation time 158291310530 ps
CPU time 337.14 seconds
Started Sep 09 05:24:56 AM UTC 24
Finished Sep 09 05:30:37 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160316742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.4160316742
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1847968537
Short name T235
Test name
Test status
Simulation time 211427631761 ps
CPU time 200.44 seconds
Started Sep 09 05:25:14 AM UTC 24
Finished Sep 09 05:28:37 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847968537 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.1847968537
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1453332328
Short name T391
Test name
Test status
Simulation time 198803458486 ps
CPU time 246.2 seconds
Started Sep 09 05:25:17 AM UTC 24
Finished Sep 09 05:29:27 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453332328 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.1453332328
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.3246348469
Short name T213
Test name
Test status
Simulation time 137624070228 ps
CPU time 840.97 seconds
Started Sep 09 05:26:09 AM UTC 24
Finished Sep 09 05:40:19 AM UTC 24
Peak memory 212824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246348469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3246348469
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.3691762281
Short name T200
Test name
Test status
Simulation time 44752282212 ps
CPU time 24.82 seconds
Started Sep 09 05:26:07 AM UTC 24
Finished Sep 09 05:26:33 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691762281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3691762281
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.3270713918
Short name T7
Test name
Test status
Simulation time 5100156865 ps
CPU time 3.28 seconds
Started Sep 09 05:26:02 AM UTC 24
Finished Sep 09 05:26:06 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270713918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3270713918
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.4032482648
Short name T157
Test name
Test status
Simulation time 5908876497 ps
CPU time 7.4 seconds
Started Sep 09 05:24:40 AM UTC 24
Finished Sep 09 05:24:49 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032482648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4032482648
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.4059231601
Short name T172
Test name
Test status
Simulation time 317981079800 ps
CPU time 690.12 seconds
Started Sep 09 05:26:29 AM UTC 24
Finished Sep 09 05:38:06 AM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059231601 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.4059231601
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3246344999
Short name T44
Test name
Test status
Simulation time 8757050758 ps
CPU time 23.41 seconds
Started Sep 09 05:26:15 AM UTC 24
Finished Sep 09 05:26:40 AM UTC 24
Peak memory 222056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3246344999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.adc_ctrl_stress_all_with_rand_reset.3246344999
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.608781151
Short name T385
Test name
Test status
Simulation time 464564284 ps
CPU time 1.77 seconds
Started Sep 09 05:28:07 AM UTC 24
Finished Sep 09 05:28:10 AM UTC 24
Peak memory 210344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608781151 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.608781151
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.204403927
Short name T132
Test name
Test status
Simulation time 344688243674 ps
CPU time 272.1 seconds
Started Sep 09 05:26:58 AM UTC 24
Finished Sep 09 05:31:34 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204403927 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.204403927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.1519832221
Short name T185
Test name
Test status
Simulation time 181206546890 ps
CPU time 266.44 seconds
Started Sep 09 05:27:14 AM UTC 24
Finished Sep 09 05:31:44 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519832221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1519832221
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.261603798
Short name T438
Test name
Test status
Simulation time 492302755586 ps
CPU time 829.38 seconds
Started Sep 09 05:26:46 AM UTC 24
Finished Sep 09 05:40:44 AM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261603798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.261603798
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.21296509
Short name T299
Test name
Test status
Simulation time 160013839806 ps
CPU time 402.27 seconds
Started Sep 09 05:26:40 AM UTC 24
Finished Sep 09 05:33:26 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21296509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.21296509
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.2102240097
Short name T416
Test name
Test status
Simulation time 159753748108 ps
CPU time 576.88 seconds
Started Sep 09 05:26:41 AM UTC 24
Finished Sep 09 05:36:24 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102240097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.2102240097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.1978826496
Short name T260
Test name
Test status
Simulation time 212946080719 ps
CPU time 598.49 seconds
Started Sep 09 05:26:46 AM UTC 24
Finished Sep 09 05:36:51 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978826496 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.1978826496
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.117725768
Short name T417
Test name
Test status
Simulation time 200269013030 ps
CPU time 584.87 seconds
Started Sep 09 05:26:54 AM UTC 24
Finished Sep 09 05:36:46 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117725768 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.117725768
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2173666236
Short name T211
Test name
Test status
Simulation time 99680676567 ps
CPU time 582.1 seconds
Started Sep 09 05:27:25 AM UTC 24
Finished Sep 09 05:37:13 AM UTC 24
Peak memory 211888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173666236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2173666236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.290840244
Short name T386
Test name
Test status
Simulation time 37015119625 ps
CPU time 72.37 seconds
Started Sep 09 05:27:18 AM UTC 24
Finished Sep 09 05:28:32 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290840244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.290840244
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.1951863928
Short name T383
Test name
Test status
Simulation time 3224797083 ps
CPU time 6.65 seconds
Started Sep 09 05:27:17 AM UTC 24
Finished Sep 09 05:27:25 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951863928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1951863928
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1958721449
Short name T203
Test name
Test status
Simulation time 5589160977 ps
CPU time 5.4 seconds
Started Sep 09 05:26:38 AM UTC 24
Finished Sep 09 05:26:45 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958721449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1958721449
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3569329456
Short name T197
Test name
Test status
Simulation time 342270227014 ps
CPU time 684.11 seconds
Started Sep 09 05:28:03 AM UTC 24
Finished Sep 09 05:39:34 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569329456 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.3569329456
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2897166535
Short name T45
Test name
Test status
Simulation time 32632607429 ps
CPU time 32.38 seconds
Started Sep 09 05:27:38 AM UTC 24
Finished Sep 09 05:28:11 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2897166535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.adc_ctrl_stress_all_with_rand_reset.2897166535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.4119838800
Short name T390
Test name
Test status
Simulation time 325978568 ps
CPU time 2.13 seconds
Started Sep 09 05:29:17 AM UTC 24
Finished Sep 09 05:29:20 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119838800 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.4119838800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2799522879
Short name T243
Test name
Test status
Simulation time 187283640943 ps
CPU time 268.17 seconds
Started Sep 09 05:28:37 AM UTC 24
Finished Sep 09 05:33:09 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799522879 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.2799522879
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.694321090
Short name T165
Test name
Test status
Simulation time 366612603124 ps
CPU time 893.57 seconds
Started Sep 09 05:28:37 AM UTC 24
Finished Sep 09 05:43:40 AM UTC 24
Peak memory 212612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694321090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.694321090
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.3241439469
Short name T244
Test name
Test status
Simulation time 162688383967 ps
CPU time 138.45 seconds
Started Sep 09 05:28:25 AM UTC 24
Finished Sep 09 05:30:46 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241439469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3241439469
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.620648518
Short name T402
Test name
Test status
Simulation time 499939796905 ps
CPU time 271.11 seconds
Started Sep 09 05:28:32 AM UTC 24
Finished Sep 09 05:33:07 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620648518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.620648518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2878899074
Short name T446
Test name
Test status
Simulation time 325110713995 ps
CPU time 853.7 seconds
Started Sep 09 05:28:17 AM UTC 24
Finished Sep 09 05:42:40 AM UTC 24
Peak memory 212732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878899074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.2878899074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.2891012399
Short name T503
Test name
Test status
Simulation time 567296318751 ps
CPU time 1396.17 seconds
Started Sep 09 05:28:33 AM UTC 24
Finished Sep 09 05:52:03 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891012399 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.2891012399
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2374747352
Short name T430
Test name
Test status
Simulation time 613093256416 ps
CPU time 664.52 seconds
Started Sep 09 05:28:35 AM UTC 24
Finished Sep 09 05:39:47 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374747352 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.2374747352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.87002781
Short name T219
Test name
Test status
Simulation time 113201390977 ps
CPU time 553.82 seconds
Started Sep 09 05:28:59 AM UTC 24
Finished Sep 09 05:38:19 AM UTC 24
Peak memory 211888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87002781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.87002781
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.512655661
Short name T389
Test name
Test status
Simulation time 42079505549 ps
CPU time 26.95 seconds
Started Sep 09 05:28:44 AM UTC 24
Finished Sep 09 05:29:12 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512655661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.512655661
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3779672487
Short name T388
Test name
Test status
Simulation time 4126521374 ps
CPU time 15.86 seconds
Started Sep 09 05:28:40 AM UTC 24
Finished Sep 09 05:28:57 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779672487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3779672487
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.1750860877
Short name T387
Test name
Test status
Simulation time 5872361620 ps
CPU time 25.31 seconds
Started Sep 09 05:28:10 AM UTC 24
Finished Sep 09 05:28:37 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750860877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1750860877
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.4292231958
Short name T214
Test name
Test status
Simulation time 281371087669 ps
CPU time 821.97 seconds
Started Sep 09 05:29:13 AM UTC 24
Finished Sep 09 05:43:04 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292231958 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.4292231958
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.602831242
Short name T26
Test name
Test status
Simulation time 7002793044 ps
CPU time 11.97 seconds
Started Sep 09 05:29:03 AM UTC 24
Finished Sep 09 05:29:16 AM UTC 24
Peak memory 221612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=602831242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
9.adc_ctrl_stress_all_with_rand_reset.602831242
Directory /workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%