Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1194554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1165628

1

T1

67

T2

5

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2068485	1			T1	81		T2	1		T3	1
values[0x0]	145893	1			T1	35		T2	5		T3	2
values[0x1]	145804	1			T1	28		T2	5		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	957433	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1402749

1

T1

79

T2

5

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9094	1			T12	7		T56	1		T15	13
valid_sources[0x01]	19919	1			T56	4		T13	2		T15	123
valid_sources[0x02]	14288	1			T8	1		T11	1		T15	40
valid_sources[0x03]	12785	1			T12	4		T56	1		T57	1
valid_sources[0x04]	6758	1			T8	1		T10	1		T12	1
valid_sources[0x05]	10905	1			T8	1		T10	1		T12	1
valid_sources[0x06]	6715	1			T12	1		T15	48		T65	1
valid_sources[0x07]	6464	1			T13	8		T15	38		T17	4
valid_sources[0x08]	6493	1			T10	1		T12	27		T56	1
valid_sources[0x09]	7233	1			T8	1		T13	4		T15	48
valid_sources[0x0a]	14051	1			T12	1		T112	2		T15	42
valid_sources[0x0b]	33482	1			T12	2		T15	33		T17	39
valid_sources[0x0c]	7640	1			T13	2		T15	118		T17	9
valid_sources[0x0d]	7487	1			T10	1		T12	1		T56	1
valid_sources[0x0e]	10544	1			T10	1		T56	3		T15	66
valid_sources[0x0f]	19332	1			T8	1		T10	1		T11	1
valid_sources[0x10]	7436	1			T21	1		T8	2		T10	2
valid_sources[0x11]	6544	1			T11	1		T59	5		T15	60
valid_sources[0x12]	8764	1			T10	1		T112	2		T15	75
valid_sources[0x13]	11473	1			T56	2		T112	2		T15	31
valid_sources[0x14]	6428	1			T10	1		T12	5		T13	6
valid_sources[0x15]	7865	1			T12	6		T15	36		T16	6
valid_sources[0x16]	6498	1			T12	1		T13	11		T15	44
valid_sources[0x17]	12247	1			T10	3		T15	142		T17	9
valid_sources[0x18]	7415	1			T7	20		T10	1		T15	32
valid_sources[0x19]	10828	1			T10	2		T12	1		T112	1
valid_sources[0x1a]	7609	1			T10	1		T12	5		T149	11
valid_sources[0x1b]	11644	1			T10	2		T12	2		T15	88
valid_sources[0x1c]	6650	1			T8	1		T12	1		T57	1
valid_sources[0x1d]	6953	1			T6	52		T12	6		T112	3
valid_sources[0x1e]	14066	1			T149	4		T15	30		T16	5
valid_sources[0x1f]	6807	1			T15	51		T17	7		T19	5
valid_sources[0x20]	14823	1			T23	1		T10	1		T11	1
valid_sources[0x21]	6489	1			T11	1		T15	19		T16	2
valid_sources[0x22]	8986	1			T5	144		T12	3		T56	3
valid_sources[0x23]	6771	1			T7	15		T15	30		T17	1
valid_sources[0x24]	11803	1			T10	1		T11	1		T15	53
valid_sources[0x25]	11177	1			T12	6		T56	7		T13	6
valid_sources[0x26]	7768	1			T11	2		T12	10		T13	2
valid_sources[0x27]	6372	1			T12	1		T13	5		T112	1
valid_sources[0x28]	8389	1			T11	1		T57	1		T15	77
valid_sources[0x29]	10415	1			T10	1		T57	1		T112	3
valid_sources[0x2a]	7592	1			T112	2		T15	51		T16	1
valid_sources[0x2b]	9448	1			T12	23		T13	9		T112	2
valid_sources[0x2c]	6837	1			T10	1		T12	1		T59	1
valid_sources[0x2d]	7829	1			T12	83		T56	3		T15	12
valid_sources[0x2e]	6994	1			T56	3		T60	1		T13	5
valid_sources[0x2f]	7505	1			T10	2		T112	5		T15	64
valid_sources[0x30]	6772	1			T10	1		T15	18		T17	12
valid_sources[0x31]	7363	1			T15	41		T16	5		T17	9
valid_sources[0x32]	7732	1			T56	1		T13	15		T149	4
valid_sources[0x33]	14000	1			T56	3		T13	8		T15	46
valid_sources[0x34]	10839	1			T57	1		T15	27		T17	24
valid_sources[0x35]	11478	1			T12	1		T57	1		T112	2
valid_sources[0x36]	7076	1			T12	5		T15	23		T16	1
valid_sources[0x37]	7341	1			T10	1		T12	3		T56	1
valid_sources[0x38]	7071	1			T8	1		T10	3		T58	31
valid_sources[0x39]	6487	1			T8	1		T10	1		T11	2
valid_sources[0x3a]	6636	1			T12	1		T56	1		T13	2
valid_sources[0x3b]	6932	1			T56	2		T15	63		T17	4
valid_sources[0x3c]	11290	1			T8	2		T15	30		T17	8
valid_sources[0x3d]	7759	1			T112	2		T15	60		T16	8
valid_sources[0x3e]	6429	1			T8	1		T10	1		T12	3
valid_sources[0x3f]	11046	1			T10	2		T13	3		T15	109
valid_sources[0x40]	7772	1			T10	1		T13	1		T15	8
valid_sources[0x41]	11226	1			T12	8		T15	104		T66	2
valid_sources[0x42]	11572	1			T10	1		T13	6		T14	15
valid_sources[0x43]	10236	1			T8	1		T12	6		T15	51
valid_sources[0x44]	6650	1			T12	2		T59	1		T15	75
valid_sources[0x45]	8267	1			T7	15		T8	1		T10	1
valid_sources[0x46]	6450	1			T12	1		T24	52		T14	8
valid_sources[0x47]	8998	1			T12	1		T15	21		T17	1
valid_sources[0x48]	7384	1			T7	19		T15	46		T17	33
valid_sources[0x49]	7116	1			T12	3		T59	2		T112	3
valid_sources[0x4a]	15053	1			T10	1		T12	3		T15	45
valid_sources[0x4b]	8680	1			T21	1		T12	15		T15	30
valid_sources[0x4c]	10756	1			T12	5		T15	99		T17	41
valid_sources[0x4d]	16541	1			T15	22		T17	41		T19	2
valid_sources[0x4e]	7023	1			T7	103		T56	1		T15	68
valid_sources[0x4f]	6788	1			T10	2		T15	64		T17	8
valid_sources[0x50]	7665	1			T11	1		T12	4		T56	4
valid_sources[0x51]	10815	1			T7	1		T12	3		T15	53
valid_sources[0x52]	7496	1			T12	6		T56	1		T57	1
valid_sources[0x53]	9396	1			T10	1		T13	1		T112	6
valid_sources[0x54]	10874	1			T10	2		T12	3		T56	1
valid_sources[0x55]	6684	1			T11	1		T56	1		T143	3
valid_sources[0x56]	10673	1			T10	2		T12	1		T15	75
valid_sources[0x57]	6722	1			T15	10		T17	1		T19	3
valid_sources[0x58]	6762	1			T10	1		T12	2		T13	10
valid_sources[0x59]	8256	1			T13	3		T15	105		T65	2
valid_sources[0x5a]	6300	1			T12	4		T13	3		T15	64
valid_sources[0x5b]	11040	1			T23	1		T12	5		T13	3
valid_sources[0x5c]	6618	1			T8	1		T9	15		T56	1
valid_sources[0x5d]	9048	1			T12	3		T56	3		T15	20
valid_sources[0x5e]	6275	1			T12	2		T56	1		T112	1
valid_sources[0x5f]	6911	1			T10	1		T12	5		T56	2
valid_sources[0x60]	10697	1			T10	1		T15	29		T17	13
valid_sources[0x61]	11883	1			T12	15		T56	1		T13	2
valid_sources[0x62]	9698	1			T10	2		T56	3		T59	1
valid_sources[0x63]	7372	1			T10	1		T15	65		T17	15
valid_sources[0x64]	12251	1			T12	2		T15	63		T17	16
valid_sources[0x65]	11930	1			T21	1		T59	1		T15	86
valid_sources[0x66]	9195	1			T15	48		T17	3		T19	8
valid_sources[0x67]	6402	1			T10	2		T12	2		T15	31
valid_sources[0x68]	7388	1			T21	1		T8	1		T12	1
valid_sources[0x69]	10555	1			T7	1		T12	3		T56	3
valid_sources[0x6a]	7280	1			T7	15		T10	1		T12	16
valid_sources[0x6b]	11604	1			T7	18		T56	1		T13	5
valid_sources[0x6c]	19351	1			T7	15		T8	3		T57	1
valid_sources[0x6d]	17980	1			T12	3		T56	1		T13	5
valid_sources[0x6e]	6610	1			T7	15		T10	1		T56	3
valid_sources[0x6f]	20015	1			T9	15		T10	1		T12	2
valid_sources[0x70]	9125	1			T12	2		T15	86		T17	6
valid_sources[0x71]	9440	1			T12	5		T15	40		T17	23
valid_sources[0x72]	6287	1			T10	1		T12	5		T13	2
valid_sources[0x73]	6825	1			T12	2		T112	1		T15	20
valid_sources[0x74]	11071	1			T12	5		T15	41		T65	2
valid_sources[0x75]	6681	1			T9	15		T10	1		T12	2
valid_sources[0x76]	10744	1			T12	5		T56	2		T13	1
valid_sources[0x77]	7690	1			T12	4		T56	1		T15	67
valid_sources[0x78]	8201	1			T7	95		T59	3		T15	48
valid_sources[0x79]	6691	1			T10	1		T12	2		T15	54
valid_sources[0x7a]	8188	1			T56	5		T57	1		T59	2
valid_sources[0x7b]	6860	1			T10	1		T12	1		T15	46
valid_sources[0x7c]	7098	1			T10	1		T13	5		T15	87
valid_sources[0x7d]	9343	1			T12	1		T15	12		T17	6
valid_sources[0x7e]	6522	1			T12	13		T56	4		T59	1
valid_sources[0x7f]	6660	1			T13	2		T149	1		T15	61
valid_sources[0x80]	9526	1			T11	2		T12	2		T112	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1029080

1

T1

48

T3

1

T5

42

values[0x0]

all_enables

biggest_size

79226

1

T1

13

T2

3

T3

1

values[0x1]

all_enables

biggest_size

57322

1

T1

6

T2

2

T4

8