Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30892	1			T14	4		T15	22		T17	6
auto[PWRUP]	100	1			T76	1		T71	1		T72	3
auto[ONEST_0]	76	1			T14	1		T76	2		T71	1
auto[ONEST_021]	13	1			T71	1		T190	2		T191	1
auto[ONEST_1]	96	1			T68	1		T69	1		T76	2
auto[ONEST_DONE]	11	1			T76	1		T192	1		T193	1
auto[LP_0]	136	1			T68	2		T69	4		T76	1
auto[LP_021]	25	1			T71	1		T72	1		T73	1
auto[LP_1]	130	1			T68	2		T69	1		T71	2
auto[LP_EVAL]	64	1			T68	1		T71	1		T72	2
auto[LP_SLP]	501	1			T68	6		T69	6		T76	4
auto[LP_PWRUP]	32	1			T68	2		T74	2		T75	1
auto[NP_0]	168	1			T76	6		T71	5		T72	2
auto[NP_021]	32	1			T68	1		T71	1		T192	1
auto[NP_1]	185	1			T68	3		T69	1		T71	2
auto[NP_EVAL]	35	1			T71	1		T192	1		T194	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T46

1

T195

1

T196

1

min

30319

1

T14

4

T15

22

T17

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30329	1			T14	4		T15	22		T17	6
pow[0x1]	12	1			T73	1		T75	1		T197	1
pow[0x2]	14	1			T71	1		T192	1		T73	1
pow[0x3]	46	1			T68	2		T69	1		T76	2
pow[0x4]	58	1			T76	1		T71	2		T75	2
pow[0x5]	149	1			T69	1		T76	5		T71	4
pow[0x6]	278	1			T68	3		T69	1		T76	1
pow[0x7]	541	1			T68	4		T69	5		T76	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T68

1

T69

2

T76

2

min

29862

1

T14

4

T15

22

T17

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29862	1			T14	4		T15	22		T17	6
pow[0x4]	1	1			T198	1		-	-		-	-
pow[0x7]	2	1			T199	1		T200	1		-	-
pow[0x8]	4	1			T75	1		T201	1		T202	1
pow[0x9]	14	1			T194	1		T193	1		T203	1
pow[0xa]	25	1			T72	1		T198	1		T204	1
pow[0xb]	49	1			T69	1		T76	1		T71	2
pow[0xc]	83	1			T69	2		T76	2		T71	2
pow[0xd]	147	1			T68	2		T76	1		T71	5
pow[0xe]	315	1			T68	5		T69	3		T76	3
pow[0xf]	631	1			T68	4		T69	5		T76	6