Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2216	1			T20	20		T7	11		T22	10
auto[PWRUP]	124	1			T7	1		T12	2		T68	1
auto[ONEST_0]	79	1			T16	1		T68	3		T69	2
auto[ONEST_021]	12	1			T13	1		T69	1		T347	1
auto[ONEST_1]	91	1			T69	1		T25	2		T192	1
auto[ONEST_DONE]	5	1			T14	1		T347	1		T75	1
auto[LP_0]	137	1			T68	2		T69	1		T76	3
auto[LP_021]	31	1			T69	1		T347	1		T198	1
auto[LP_1]	146	1			T68	1		T69	2		T71	1
auto[LP_EVAL]	48	1			T13	1		T14	1		T69	1
auto[LP_SLP]	551	1			T9	1		T12	2		T68	2
auto[LP_PWRUP]	22	1			T73	1		T75	1		T194	1
auto[NP_0]	219	1			T7	3		T9	1		T12	2
auto[NP_021]	56	1			T16	1		T68	1		T62	1
auto[NP_1]	176	1			T9	1		T16	1		T61	1
auto[NP_EVAL]	30	1			T69	1		T46	1		T75	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T75

2

T348

2

T202

2

min

1752

1

T20

20

T7

15

T22

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1771	1			T20	20		T7	15		T22	10
pow[0x1]	12	1			T12	1		T71	1		T192	1
pow[0x2]	15	1			T68	1		T63	1		T75	1
pow[0x3]	45	1			T69	1		T46	1		T74	1
pow[0x4]	66	1			T68	1		T71	2		T192	1
pow[0x5]	148	1			T68	1		T69	2		T76	1
pow[0x6]	271	1			T14	1		T68	5		T69	8
pow[0x7]	514	1			T68	4		T69	7		T76	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

179

1

T68

3

T69

2

T76

1

min

1213

1

T20

20

T7

13

T22

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1223	1			T20	20		T7	14		T22	10
pow[0x1]	9	1			T7	1		T14	1		T16	1
pow[0x2]	17	1			T12	1		T13	1		T62	1
pow[0x3]	11	1			T62	1		T267	1		T259	4
pow[0x4]	15	1			T9	2		T12	1		T16	1
pow[0x5]	5	1			T68	1		T214	1		T349	1
pow[0x6]	1	1			T350	1		-	-		-	-
pow[0x7]	4	1			T76	1		T351	1		T352	2
pow[0x8]	7	1			T68	1		T75	1		T353	1
pow[0x9]	2	1			T198	1		T191	1		-	-
pow[0xa]	22	1			T69	1		T71	1		T347	2
pow[0xb]	45	1			T69	3		T76	1		T71	2
pow[0xc]	76	1			T68	1		T76	2		T71	3
pow[0xd]	161	1			T68	1		T69	1		T71	1
pow[0xe]	309	1			T68	5		T69	4		T76	2
pow[0xf]	611	1			T68	5		T69	9		T76	6