Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	32167157	32093102	0	0
FsmStateHwReset_A	1038	1038	0	0
FsmStateSwReset_A	32167157	6669	0	0
LpSampleCntHwReset_A	1038	1038	0	0
LpSampleCntSwReset_A	32167157	6669	0	0
NpSampleCntHwReset_A	1038	1038	0	0
NpSampleCntSwReset_A	32167157	6669	0	0
PwrupTimerCntHwReset_A	1038	1038	0	0
PwrupTimerCntSwReset_A	32167157	6669	0	0
WakeupTimerCntHwReset_A	1038	1038	0	0
WakeupTimerCntSwReset_A	32167157	6669	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32167157	32093102	0	0
T1	1182	1121	0	0
T2	78	1	0	0
T3	100	1	0	0
T4	621	534	0	0
T5	1145	1090	0	0
T6	8110	8034	0	0
T7	3848	3459	0	0
T8	743	676	0	0
T20	81	1	0	0
T21	60	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	11	11	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32167157	6669	0	0
T15	100164	22	0	0
T16	1282	0	0	0
T17	32061	6	0	0
T18	31807	5	0	0
T19	33328	6	0	0
T50	67033	17	0	0
T51	0	8	0	0
T52	0	10	0	0
T53	0	8	0	0
T55	577	0	0	0
T64	0	6	0	0
T65	8159	0	0	0
T66	86	0	0	0
T67	1153	0	0	0
T97	0	5	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	11	11	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32167157	6669	0	0
T15	100164	22	0	0
T16	1282	0	0	0
T17	32061	6	0	0
T18	31807	5	0	0
T19	33328	6	0	0
T50	67033	17	0	0
T51	0	8	0	0
T52	0	10	0	0
T53	0	8	0	0
T55	577	0	0	0
T64	0	6	0	0
T65	8159	0	0	0
T66	86	0	0	0
T67	1153	0	0	0
T97	0	5	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	11	11	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32167157	6669	0	0
T15	100164	22	0	0
T16	1282	0	0	0
T17	32061	6	0	0
T18	31807	5	0	0
T19	33328	6	0	0
T50	67033	17	0	0
T51	0	8	0	0
T52	0	10	0	0
T53	0	8	0	0
T55	577	0	0	0
T64	0	6	0	0
T65	8159	0	0	0
T66	86	0	0	0
T67	1153	0	0	0
T97	0	5	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	11	11	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32167157	6669	0	0
T15	100164	22	0	0
T16	1282	0	0	0
T17	32061	6	0	0
T18	31807	5	0	0
T19	33328	6	0	0
T50	67033	17	0	0
T51	0	8	0	0
T52	0	10	0	0
T53	0	8	0	0
T55	577	0	0	0
T64	0	6	0	0
T65	8159	0	0	0
T66	86	0	0	0
T67	1153	0	0	0
T97	0	5	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	11	11	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32167157	6669	0	0
T15	100164	22	0	0
T16	1282	0	0	0
T17	32061	6	0	0
T18	31807	5	0	0
T19	33328	6	0	0
T50	67033	17	0	0
T51	0	8	0	0
T52	0	10	0	0
T53	0	8	0	0
T55	577	0	0	0
T64	0	6	0	0
T65	8159	0	0	0
T66	86	0	0	0
T67	1153	0	0	0
T97	0	5	0	0