Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2227	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2105	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2179	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1993	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2221	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2172	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2217	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2049	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2170	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2000	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2219	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2031	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2134	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1953	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1932	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2087	0	0
adc_en_ctl_rd_A	2147483647	1829	0	0
adc_fsm_rst_rd_A	2147483647	1664	0	0
adc_intr_ctl_rd_A	2147483647	1996	0	0
adc_lp_sample_ctl_rd_A	2147483647	1684	0	0
adc_pd_ctl_rd_A	2147483647	1997	0	0
adc_sample_ctl_rd_A	2147483647	1695	0	0
adc_wakeup_ctl_rd_A	2147483647	1760	0	0
intr_enable_rd_A	2147483647	2189	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T25	279718	32	0	0
T26	0	18	0	0
T27	0	22	0	0
T28	0	37	0	0
T29	0	14	0	0
T30	0	26	0	0
T31	0	2	0	0
T32	0	17	0	0
T33	0	20	0	0
T34	0	13	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T25	279718	34	0	0
T26	0	23	0	0
T27	0	11	0	0
T28	0	33	0	0
T29	0	11	0	0
T30	0	17	0	0
T31	0	22	0	0
T32	0	10	0	0
T33	0	20	0	0
T34	0	8	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2179	0	0
T25	279718	43	0	0
T26	0	12	0	0
T27	0	34	0	0
T28	0	54	0	0
T29	0	13	0	0
T30	0	10	0	0
T31	0	8	0	0
T32	0	19	0	0
T33	0	18	0	0
T34	0	17	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1993	0	0
T25	279718	21	0	0
T26	0	14	0	0
T27	0	9	0	0
T28	0	39	0	0
T29	0	6	0	0
T30	0	20	0	0
T31	0	16	0	0
T32	0	19	0	0
T33	0	10	0	0
T34	0	19	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2221	0	0
T25	279718	41	0	0
T26	0	18	0	0
T27	0	24	0	0
T28	0	30	0	0
T29	0	7	0	0
T30	0	22	0	0
T31	0	9	0	0
T32	0	24	0	0
T33	0	4	0	0
T34	0	18	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2172	0	0
T25	279718	25	0	0
T26	0	31	0	0
T27	0	13	0	0
T28	0	43	0	0
T29	0	11	0	0
T30	0	19	0	0
T31	0	11	0	0
T32	0	6	0	0
T33	0	22	0	0
T34	0	18	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2217	0	0
T25	279718	43	0	0
T26	0	26	0	0
T27	0	16	0	0
T28	0	32	0	0
T29	0	5	0	0
T30	0	12	0	0
T31	0	10	0	0
T32	0	18	0	0
T33	0	9	0	0
T34	0	8	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2049	0	0
T25	279718	39	0	0
T26	0	19	0	0
T27	0	21	0	0
T28	0	43	0	0
T29	0	11	0	0
T30	0	26	0	0
T31	0	11	0	0
T32	0	9	0	0
T33	0	19	0	0
T34	0	7	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2170	0	0
T25	279718	42	0	0
T26	0	28	0	0
T27	0	21	0	0
T28	0	42	0	0
T29	0	5	0	0
T30	0	13	0	0
T32	0	26	0	0
T33	0	8	0	0
T34	0	28	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0
T44	0	24	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2000	0	0
T25	279718	41	0	0
T26	0	27	0	0
T27	0	19	0	0
T28	0	29	0	0
T29	0	13	0	0
T30	0	5	0	0
T31	0	13	0	0
T32	0	20	0	0
T33	0	19	0	0
T34	0	29	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2219	0	0
T25	279718	36	0	0
T26	0	18	0	0
T27	0	21	0	0
T28	0	49	0	0
T29	0	6	0	0
T30	0	16	0	0
T31	0	8	0	0
T32	0	16	0	0
T33	0	27	0	0
T34	0	31	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2031	0	0
T25	279718	32	0	0
T26	0	23	0	0
T27	0	26	0	0
T28	0	27	0	0
T29	0	15	0	0
T30	0	19	0	0
T31	0	5	0	0
T32	0	23	0	0
T33	0	20	0	0
T34	0	21	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2134	0	0
T25	279718	44	0	0
T26	0	20	0	0
T27	0	29	0	0
T28	0	29	0	0
T29	0	14	0	0
T30	0	22	0	0
T31	0	10	0	0
T32	0	20	0	0
T33	0	16	0	0
T34	0	18	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1953	0	0
T25	279718	41	0	0
T26	0	23	0	0
T27	0	23	0	0
T28	0	44	0	0
T29	0	3	0	0
T30	0	19	0	0
T31	0	3	0	0
T32	0	2	0	0
T33	0	21	0	0
T34	0	11	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1932	0	0
T25	279718	48	0	0
T26	0	12	0	0
T27	0	24	0	0
T28	0	25	0	0
T29	0	6	0	0
T30	0	6	0	0
T31	0	30	0	0
T32	0	8	0	0
T33	0	23	0	0
T34	0	15	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2087	0	0
T25	279718	57	0	0
T26	0	10	0	0
T27	0	14	0	0
T28	0	38	0	0
T29	0	17	0	0
T30	0	27	0	0
T31	0	4	0	0
T32	0	13	0	0
T33	0	19	0	0
T34	0	11	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1829	0	0
T25	279718	38	0	0
T26	0	34	0	0
T27	0	21	0	0
T28	0	25	0	0
T29	0	8	0	0
T30	0	14	0	0
T31	0	12	0	0
T32	0	12	0	0
T33	0	39	0	0
T34	0	30	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1664	0	0
T25	279718	22	0	0
T26	0	24	0	0
T27	0	11	0	0
T28	0	40	0	0
T29	0	22	0	0
T30	0	6	0	0
T31	0	21	0	0
T32	0	5	0	0
T33	0	24	0	0
T34	0	28	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1996	0	0
T25	279718	48	0	0
T26	0	15	0	0
T27	0	24	0	0
T28	0	44	0	0
T30	0	8	0	0
T32	0	9	0	0
T33	0	7	0	0
T34	0	12	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0
T44	0	17	0	0
T45	0	15	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1684	0	0
T25	279718	31	0	0
T26	0	10	0	0
T27	0	16	0	0
T28	0	30	0	0
T30	0	19	0	0
T31	0	4	0	0
T32	0	8	0	0
T33	0	55	0	0
T34	0	21	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0
T44	0	16	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1997	0	0
T25	279718	49	0	0
T26	0	24	0	0
T27	0	16	0	0
T28	0	34	0	0
T29	0	17	0	0
T30	0	14	0	0
T31	0	23	0	0
T32	0	10	0	0
T33	0	21	0	0
T34	0	17	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1695	0	0
T25	279718	41	0	0
T26	0	2	0	0
T27	0	18	0	0
T28	0	45	0	0
T29	0	9	0	0
T30	0	8	0	0
T31	0	12	0	0
T32	0	24	0	0
T33	0	25	0	0
T34	0	19	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760	0	0
T25	279718	34	0	0
T26	0	19	0	0
T27	0	18	0	0
T28	0	29	0	0
T29	0	14	0	0
T30	0	16	0	0
T31	0	10	0	0
T32	0	4	0	0
T33	0	20	0	0
T34	0	20	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2189	0	0
T25	279718	39	0	0
T26	0	17	0	0
T27	0	23	0	0
T28	0	51	0	0
T29	0	3	0	0
T30	0	25	0	0
T35	570181	0	0	0
T36	589738	0	0	0
T37	199971	0	0	0
T38	141017	0	0	0
T39	460164	0	0	0
T40	166042	0	0	0
T41	171035	0	0	0
T42	182387	0	0	0
T43	492471	0	0	0
T46	0	32	0	0
T47	0	16	0	0
T48	0	11	0	0
T49	0	22	0	0