Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1141683	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1117476

1

T1

5

T2

63

T3

64

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1985432	1			T1	1		T2	81		T3	81
values[0x0]	136350	1			T1	5		T2	37		T3	39
values[0x1]	137377	1			T1	4		T2	26		T3	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	913958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1345201

1

T1

6

T2

70

T3

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9698	1			T5	15		T8	1		T10	1
valid_sources[0x01]	9545	1			T8	3		T11	4		T49	3
valid_sources[0x02]	8669	1			T1	2		T3	1		T8	1
valid_sources[0x03]	6735	1			T3	1		T11	2		T55	1
valid_sources[0x04]	6940	1			T3	1		T12	1		T44	6
valid_sources[0x05]	8886	1			T2	1		T3	1		T5	4
valid_sources[0x06]	6902	1			T5	3		T18	3		T51	1
valid_sources[0x07]	11187	1			T3	1		T5	18		T8	5
valid_sources[0x08]	6666	1			T6	1		T8	3		T11	1
valid_sources[0x09]	7809	1			T11	6		T14	8		T351	1
valid_sources[0x0a]	7125	1			T1	1		T5	10		T6	1
valid_sources[0x0b]	17919	1			T3	1		T5	4		T11	4
valid_sources[0x0c]	10754	1			T6	1		T11	1		T51	2
valid_sources[0x0d]	6826	1			T2	4		T11	11		T49	1
valid_sources[0x0e]	11130	1			T11	6		T51	1		T60	1
valid_sources[0x0f]	12017	1			T2	1		T9	1		T11	2
valid_sources[0x10]	19752	1			T2	4		T5	2		T11	3
valid_sources[0x11]	6826	1			T11	11		T12	2		T110	1
valid_sources[0x12]	12076	1			T2	5		T5	9		T7	3
valid_sources[0x13]	6894	1			T5	11		T8	8		T11	14
valid_sources[0x14]	6844	1			T2	1		T3	1		T5	12
valid_sources[0x15]	6731	1			T5	7		T7	1		T11	2
valid_sources[0x16]	7475	1			T2	2		T3	2		T5	8
valid_sources[0x17]	7869	1			T3	1		T5	3		T11	2
valid_sources[0x18]	6773	1			T11	5		T12	3		T110	1
valid_sources[0x19]	10903	1			T5	9		T8	6		T60	1
valid_sources[0x1a]	9574	1			T11	1		T14	4		T15	15
valid_sources[0x1b]	6207	1			T3	2		T5	1		T6	1
valid_sources[0x1c]	7329	1			T5	6		T11	6		T51	1
valid_sources[0x1d]	6597	1			T8	8		T12	1		T351	1
valid_sources[0x1e]	9686	1			T3	1		T5	9		T8	7
valid_sources[0x1f]	7471	1			T3	2		T8	1		T11	4
valid_sources[0x20]	6701	1			T2	1		T8	9		T11	5
valid_sources[0x21]	10996	1			T13	4283		T351	2		T17	14
valid_sources[0x22]	6806	1			T8	9		T12	2		T110	1
valid_sources[0x23]	6730	1			T5	12		T8	2		T11	3
valid_sources[0x24]	6978	1			T1	1		T2	3		T11	5
valid_sources[0x25]	20140	1			T3	1		T11	8		T51	2
valid_sources[0x26]	6450	1			T5	1		T8	1		T12	1
valid_sources[0x27]	11133	1			T2	1		T11	3		T12	2
valid_sources[0x28]	14662	1			T2	6		T3	1		T8	7
valid_sources[0x29]	6557	1			T2	1		T5	2		T8	7
valid_sources[0x2a]	15331	1			T12	3		T17	11		T45	5
valid_sources[0x2b]	6910	1			T5	18		T6	1		T18	3
valid_sources[0x2c]	6949	1			T11	4		T12	4		T14	1
valid_sources[0x2d]	10568	1			T5	6		T11	4		T12	4
valid_sources[0x2e]	6933	1			T3	3		T60	1		T12	2
valid_sources[0x2f]	9749	1			T8	3		T11	5		T12	2
valid_sources[0x30]	6818	1			T2	2		T3	2		T5	2
valid_sources[0x31]	6518	1			T11	4		T14	5		T167	2
valid_sources[0x32]	6783	1			T5	15		T11	2		T55	1
valid_sources[0x33]	13191	1			T3	3		T11	4		T12	5
valid_sources[0x34]	6409	1			T7	3		T11	5		T12	6
valid_sources[0x35]	12596	1			T5	15		T6	1		T8	4
valid_sources[0x36]	6774	1			T3	3		T11	1		T49	1
valid_sources[0x37]	11893	1			T7	1		T8	1		T11	2
valid_sources[0x38]	7863	1			T2	2		T5	9		T8	6
valid_sources[0x39]	7893	1			T2	2		T5	7		T8	5
valid_sources[0x3a]	6730	1			T5	6		T8	1		T11	3
valid_sources[0x3b]	6784	1			T5	12		T6	1		T12	2
valid_sources[0x3c]	6801	1			T12	1		T166	1		T44	2
valid_sources[0x3d]	6783	1			T2	2		T6	2		T11	2
valid_sources[0x3e]	7642	1			T2	1		T8	5		T12	2
valid_sources[0x3f]	6362	1			T5	5		T11	2		T12	2
valid_sources[0x40]	6830	1			T11	2		T351	2		T17	14
valid_sources[0x41]	6753	1			T11	2		T110	3		T14	6
valid_sources[0x42]	11221	1			T3	1		T5	1		T8	1
valid_sources[0x43]	6615	1			T11	4		T50	55		T12	2
valid_sources[0x44]	6656	1			T18	2		T8	13		T11	9
valid_sources[0x45]	9575	1			T5	16		T9	56		T11	6
valid_sources[0x46]	6797	1			T2	2		T12	1		T44	2
valid_sources[0x47]	7014	1			T2	4		T5	14		T8	4
valid_sources[0x48]	10773	1			T5	6		T6	1		T11	3
valid_sources[0x49]	7418	1			T8	1		T11	2		T51	1
valid_sources[0x4a]	6392	1			T11	4		T49	1		T12	1
valid_sources[0x4b]	6820	1			T3	1		T5	1		T7	1
valid_sources[0x4c]	6589	1			T2	1		T11	8		T12	1
valid_sources[0x4d]	6963	1			T7	1		T10	7		T11	6
valid_sources[0x4e]	13812	1			T3	1		T9	4		T11	2
valid_sources[0x4f]	6673	1			T5	2		T8	8		T9	15
valid_sources[0x50]	9175	1			T3	3		T6	1		T11	1
valid_sources[0x51]	11205	1			T3	1		T5	5		T11	5
valid_sources[0x52]	6981	1			T5	16		T8	1		T11	2
valid_sources[0x53]	6564	1			T8	1		T17	12		T45	1
valid_sources[0x54]	8048	1			T5	11		T6	1		T11	7
valid_sources[0x55]	11234	1			T11	12		T351	1		T17	18
valid_sources[0x56]	25020	1			T3	2		T10	23		T11	1
valid_sources[0x57]	6777	1			T3	1		T5	2		T8	1
valid_sources[0x58]	8794	1			T8	1		T11	7		T12	2
valid_sources[0x59]	6633	1			T3	4		T5	3		T8	2
valid_sources[0x5a]	10710	1			T11	5		T12	1		T110	1
valid_sources[0x5b]	10983	1			T5	9		T6	1		T18	1
valid_sources[0x5c]	6888	1			T8	8		T11	1		T51	1
valid_sources[0x5d]	7767	1			T2	3		T7	2		T8	6
valid_sources[0x5e]	15330	1			T11	6		T12	2		T351	3
valid_sources[0x5f]	6722	1			T2	1		T3	1		T8	3
valid_sources[0x60]	12410	1			T8	1		T11	21		T12	4
valid_sources[0x61]	7057	1			T5	2		T8	3		T11	11
valid_sources[0x62]	6993	1			T3	2		T8	6		T11	1
valid_sources[0x63]	6842	1			T5	14		T7	1		T8	4
valid_sources[0x64]	15551	1			T11	2		T110	2		T16	2
valid_sources[0x65]	6444	1			T8	6		T11	4		T12	4
valid_sources[0x66]	8781	1			T5	22		T8	1		T11	2
valid_sources[0x67]	11943	1			T8	11		T11	1		T12	6
valid_sources[0x68]	6781	1			T5	18		T11	9		T110	2
valid_sources[0x69]	13748	1			T5	13		T6	2		T8	1
valid_sources[0x6a]	15658	1			T2	3		T11	3		T12	1
valid_sources[0x6b]	7407	1			T4	58		T8	5		T11	2
valid_sources[0x6c]	6648	1			T2	3		T5	8		T8	5
valid_sources[0x6d]	7961	1			T1	1		T8	3		T19	3
valid_sources[0x6e]	6963	1			T3	1		T9	15		T11	1
valid_sources[0x6f]	7142	1			T6	1		T8	5		T11	1
valid_sources[0x70]	6760	1			T11	1		T12	2		T44	1
valid_sources[0x71]	11788	1			T5	16		T8	2		T11	2
valid_sources[0x72]	10706	1			T5	4		T8	3		T11	4
valid_sources[0x73]	6710	1			T5	2		T11	10		T166	1
valid_sources[0x74]	6865	1			T11	2		T51	1		T12	2
valid_sources[0x75]	6632	1			T5	1		T8	1		T11	8
valid_sources[0x76]	9167	1			T2	1		T5	13		T6	1
valid_sources[0x77]	6567	1			T8	2		T11	5		T12	3
valid_sources[0x78]	7093	1			T5	11		T11	3		T12	2
valid_sources[0x79]	8738	1			T5	17		T6	1		T11	9
valid_sources[0x7a]	11120	1			T2	3		T5	8		T8	2
valid_sources[0x7b]	7238	1			T5	5		T8	1		T11	3
valid_sources[0x7c]	7058	1			T2	1		T11	18		T12	2
valid_sources[0x7d]	6699	1			T8	6		T11	10		T49	1
valid_sources[0x7e]	6686	1			T11	5		T12	1		T110	1
valid_sources[0x7f]	6726	1			T5	13		T7	1		T11	10
valid_sources[0x80]	7765	1			T5	17		T6	1		T18	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

988534

1

T1

1

T2

43

T3

39

values[0x0]

all_enables

biggest_size

74910

1

T1

4

T2

14

T3

17

values[0x1]

all_enables

biggest_size

54032

1

T2

6

T3

8

T4

14