Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27573	1			T5	6		T11	7		T13	4
auto[PWRUP]	105	1			T57	1		T59	2		T163	1
auto[ONEST_0]	81	1			T57	1		T58	1		T163	1
auto[ONEST_021]	17	1			T61	2		T63	2		T207	1
auto[ONEST_1]	69	1			T58	4		T59	1		T163	1
auto[ONEST_DONE]	2	1			T208	1		T209	1		-	-
auto[LP_0]	124	1			T52	1		T57	1		T58	4
auto[LP_021]	29	1			T57	2		T163	1		T62	1
auto[LP_1]	126	1			T57	2		T58	2		T59	1
auto[LP_EVAL]	45	1			T57	1		T61	1		T210	3
auto[LP_SLP]	450	1			T57	3		T58	9		T59	8
auto[LP_PWRUP]	25	1			T58	1		T163	1		T62	1
auto[NP_0]	130	1			T57	1		T58	1		T59	2
auto[NP_021]	28	1			T58	1		T61	2		T184	1
auto[NP_1]	127	1			T57	1		T58	1		T59	2
auto[NP_EVAL]	24	1			T58	1		T59	1		T163	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T207

1

T211

1

T212

1

min

27058

1

T5

6

T11

7

T13

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27062	1			T5	6		T11	7		T13	4
pow[0x1]	9	1			T59	1		T208	1		T63	1
pow[0x2]	18	1			T57	1		T61	1		T213	1
pow[0x3]	32	1			T59	1		T61	1		T62	2
pow[0x4]	54	1			T58	1		T59	1		T163	1
pow[0x5]	136	1			T52	1		T57	1		T58	1
pow[0x6]	242	1			T57	3		T58	3		T59	7
pow[0x7]	496	1			T57	9		T58	7		T59	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

178

1

T57

1

T58

7

T59

4

min

26607

1

T5

6

T11

7

T13

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26607	1			T5	6		T11	7		T13	4
pow[0x2]	1	1			T214	1		-	-		-	-
pow[0x6]	1	1			T215	1		-	-		-	-
pow[0x7]	3	1			T210	1		T216	1		T217	1
pow[0x8]	3	1			T63	1		T218	2		-	-
pow[0x9]	5	1			T219	1		T220	1		T221	1
pow[0xa]	11	1			T210	1		T222	1		T223	1
pow[0xb]	35	1			T52	1		T58	1		T61	2
pow[0xc]	55	1			T58	2		T59	2		T163	1
pow[0xd]	130	1			T59	1		T163	1		T62	3
pow[0xe]	277	1			T57	2		T58	6		T59	5
pow[0xf]	578	1			T57	4		T58	8		T59	11