Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2112	1			T8	12		T9	6		T19	20
auto[PWRUP]	127	1			T52	1		T57	4		T53	1
auto[ONEST_0]	77	1			T9	1		T44	1		T57	2
auto[ONEST_021]	18	1			T58	1		T222	1		T207	1
auto[ONEST_1]	84	1			T12	1		T21	1		T52	1
auto[ONEST_DONE]	4	1			T24	1		T341	1		T342	1
auto[LP_0]	110	1			T52	1		T58	3		T163	2
auto[LP_021]	25	1			T12	1		T58	1		T163	3
auto[LP_1]	104	1			T57	1		T58	1		T59	1
auto[LP_EVAL]	39	1			T57	1		T58	2		T163	1
auto[LP_SLP]	445	1			T8	2		T39	2		T57	4
auto[LP_PWRUP]	34	1			T57	1		T59	1		T61	1
auto[NP_0]	180	1			T8	1		T9	1		T12	1
auto[NP_021]	42	1			T62	2		T343	1		T258	1
auto[NP_1]	172	1			T12	1		T44	2		T57	1
auto[NP_EVAL]	28	1			T8	1		T9	1		T53	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T57

1

T61

1

T41

2

min

1699

1

T8

13

T9

9

T19

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1715	1			T8	15		T9	9		T19	20
pow[0x1]	10	1			T57	1		T53	1		T344	1
pow[0x2]	24	1			T12	1		T21	1		T57	1
pow[0x3]	36	1			T57	1		T58	1		T163	1
pow[0x4]	57	1			T57	2		T58	1		T59	2
pow[0x5]	111	1			T16	1		T21	1		T57	2
pow[0x6]	242	1			T57	5		T58	3		T59	3
pow[0x7]	489	1			T57	3		T58	5		T59	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

164

1

T57

3

T58

5

T59

2

min

1281

1

T8

14

T9

7

T19

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1287	1			T8	14		T9	7		T19	20
pow[0x1]	13	1			T8	1		T44	1		T54	1
pow[0x2]	19	1			T52	2		T53	1		T137	1
pow[0x3]	17	1			T9	2		T12	1		T16	1
pow[0x4]	15	1			T12	1		T254	1		T90	3
pow[0x5]	2	1			T345	1		T346	1		-	-
pow[0x6]	1	1			T108	1		-	-		-	-
pow[0x7]	4	1			T62	1		T347	1		T348	1
pow[0x8]	5	1			T208	1		T349	1		T350	1
pow[0x9]	15	1			T57	1		T210	1		T211	1
pow[0xa]	16	1			T41	1		T223	1		T207	1
pow[0xb]	28	1			T57	1		T58	1		T59	1
pow[0xc]	58	1			T21	1		T57	1		T58	2
pow[0xd]	131	1			T57	1		T58	4		T59	3
pow[0xe]	252	1			T57	4		T58	2		T59	3
pow[0xf]	560	1			T16	1		T21	1		T57	10