Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

55                      
56         8/8              assign aon_filter_ctl[0][k] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
57                            min_v: reg2hw_i.adc_chn0_filter_ctl[k].min_v.q,
58                            max_v: reg2hw_i.adc_chn0_filter_ctl[k].max_v.q,
59                            cond:  reg2hw_i.adc_chn0_filter_ctl[k].cond.q,
60                            en:    reg2hw_i.adc_chn0_filter_ctl[k].en.q
61                          };
62                      
63         8/8              assign aon_filter_ctl[1][k] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
64                            min_v: reg2hw_i.adc_chn1_filter_ctl[k].min_v.q,
65                            max_v: reg2hw_i.adc_chn1_filter_ctl[k].max_v.q,
66                            cond:  reg2hw_i.adc_chn1_filter_ctl[k].cond.q,
67                            en:    reg2hw_i.adc_chn1_filter_ctl[k].en.q
68                          };
69                        end // block: gen_filter_ctl_sync
70                      
71                        // Recent adc channel values
72         1/1            assign adc_chn_val_o[0].adc_chn_value.de = chn0_val_we;
           Tests:       T1 T2 T3 
73         1/1            assign adc_chn_val_o[0].adc_chn_value.d  = chn0_val;
           Tests:       T1 T2 T3 
74         1/1            assign adc_chn_val_o[1].adc_chn_value.de = chn1_val_we;
           Tests:       T1 T2 T3 
75         1/1            assign adc_chn_val_o[1].adc_chn_value.d  = chn1_val;
           Tests:       T1 T2 T3 
76                      
77                        // Interrupt based adc channel values
78                        // The value of the adc is captured whenever an interrupt triggers.
79                        // There are two cases:
80                        // completion of one shot mode
81                        // match detection from the filters
82                        logic chn_val_intr_we;
83         1/1            assign chn_val_intr_we = reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done :
           Tests:       T1 T2 T3 
84                                                 reg2hw_i.adc_en_ctl.adc_enable.q   ? |match_pulse : '0;
85                      
86         1/1            assign adc_chn_val_o[0].adc_chn_value_intr.de = chn_val_intr_we;
           Tests:       T1 T2 T3 
87         1/1            assign adc_chn_val_o[0].adc_chn_value_intr.d  = chn0_val;
           Tests:       T1 T2 T3 
88         1/1            assign adc_chn_val_o[1].adc_chn_value_intr.de = chn_val_intr_we;
           Tests:       T1 T2 T3 
89         1/1            assign adc_chn_val_o[1].adc_chn_value_intr.d  = chn1_val;
           Tests:       T1 T2 T3 
90                      
91                        //Connect the ports for future extension
92                        assign adc_chn_val_o[0].adc_chn_value_ext.de = 1'b0;
93                        assign adc_chn_val_o[0].adc_chn_value_ext.d  = 2'b0;
94                        assign adc_chn_val_o[1].adc_chn_value_ext.de = 1'b0;
95                        assign adc_chn_val_o[1].adc_chn_value_ext.d  = 2'b0;
96                      
97                        assign adc_chn_val_o[0].adc_chn_value_intr_ext.de = 1'b0;
98                        assign adc_chn_val_o[0].adc_chn_value_intr_ext.d  = 2'b0;
99                        assign adc_chn_val_o[1].adc_chn_value_intr_ext.de = 1'b0;
100                       assign adc_chn_val_o[1].adc_chn_value_intr_ext.d  = 2'b0;
101                     
102                       // Evaluate if there is a match from chn0 and chn1 samples
103                       for (genvar k = 0 ; k < NumAdcFilter ; k++) begin : gen_filter_match
104        8/8              assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
105                                 (aon_filter_ctl[0][k].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][k].max_v) :
106                                 (aon_filter_ctl[0][k].min_v >  chn0_val) || (chn0_val >  aon_filter_ctl[0][k].max_v);
107        8/8              assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
108                                 (aon_filter_ctl[1][k].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][k].max_v) :
109                                 (aon_filter_ctl[1][k].min_v >  chn1_val) || (chn1_val >  aon_filter_ctl[1][k].max_v);
110                     
111                         // If the filter on a particular channel is NOT enabled, it does not participate in the final
112                         // match decision.  This means the match value should have no impact on the final result.
113                         // For example, if channel 0's filter is enabled, but channel 1's is not, the match result
114                         // is determined solely based on whether channel 0's filter shows a match.
115                         // On the other hand, if all channel's filters are enabled, then a match is seen only when
116                         // both filters match.
117        8/8              assign match[k] = |{aon_filter_ctl[0][k].en, aon_filter_ctl[1][k].en} &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
118                                           (!aon_filter_ctl[0][k].en | (chn0_match[k] & aon_filter_ctl[0][k].en)) &
119                                           (!aon_filter_ctl[1][k].en | (chn1_match[k] & aon_filter_ctl[1][k].en)) ;
120                     
121        8/8              assign match_pulse[k] = adc_ctrl_done && match[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
122                     
123                        // Explicitly create assertions for all the matching conditions.
124                        // These assertions are unwieldy and not suitable for expansion to more channels.
125                        // They should be adjusted eventually.
126                        `ASSERT(MatchCheck00_A, !aon_filter_ctl[0][k].en & !aon_filter_ctl[1][k].en |->
127                                !match[k], clk_aon_i, !rst_aon_ni)
128                        `ASSERT(MatchCheck01_A, !aon_filter_ctl[0][k].en & aon_filter_ctl[1][k].en  |->
129                                match[k] == chn1_match[k], clk_aon_i, !rst_aon_ni)
130                        `ASSERT(MatchCheck10_A, aon_filter_ctl[0][k].en & !aon_filter_ctl[1][k].en  |->
131                                match[k] == chn0_match[k], clk_aon_i, !rst_aon_ni)
132                        `ASSERT(MatchCheck11_A, aon_filter_ctl[0][k].en & aon_filter_ctl[1][k].en   |->
133                                match[k] == (chn0_match[k] & chn1_match[k]), clk_aon_i, !rst_aon_ni)
134                       end
135                     
136                       // adc filter status
137        1/1            assign aon_filter_status_o.match.d  = match_pulse | reg2hw_i.filter_status.match.q;
           Tests:       T1 T2 T3 
138        1/1            assign aon_filter_status_o.match.de = |match_pulse;
           Tests:       T1 T2 T3 
139                       // transition status
140        1/1            assign aon_filter_status_o.trans.d  = aon_fsm_trans | reg2hw_i.filter_status.trans.q;
           Tests:       T1 T2 T3 
141        1/1            assign aon_filter_status_o.trans.de = aon_fsm_trans;
           Tests:       T1 T2 T3 
142                     
143                       // generate wakeup to external power manager if filter status
144                       // and wakeup enable are set.
145        1/1            assign wkup_req_o = |(reg2hw_i.filter_status.match.q &
           Tests:       T1 T2 T3 
146                                             reg2hw_i.adc_wakeup_ctl.match_en.q) ||
147                                            (reg2hw_i.filter_status.trans.q &
148                                             reg2hw_i.adc_wakeup_ctl.trans_en.q);
149                     
150                       //instantiate the main state machine
151                       adc_ctrl_fsm u_adc_ctrl_fsm (
152                         .clk_aon_i,
153                         .rst_aon_ni,
154                         // configuration and settings from reg interface
155                         .cfg_fsm_rst_i(reg2hw_i.adc_fsm_rst.q),
156                         .cfg_adc_enable_i(reg2hw_i.adc_en_ctl.adc_enable.q),
157                         .cfg_oneshot_mode_i(reg2hw_i.adc_en_ctl.oneshot_mode.q),
158                         .cfg_lp_mode_i(reg2hw_i.adc_pd_ctl.lp_mode.q),
159                         .cfg_pwrup_time_i(reg2hw_i.adc_pd_ctl.pwrup_time.q),
160                         .cfg_wakeup_time_i(reg2hw_i.adc_pd_ctl.wakeup_time.q),
161                         .cfg_lp_sample_cnt_i(reg2hw_i.adc_lp_sample_ctl.q),
162                         .cfg_np_sample_cnt_i(reg2hw_i.adc_sample_ctl.q),
163                         //
164                         .adc_ctrl_match_i(match),
165                         .adc_d_i(adc_i.data),
166                         .adc_d_val_i(adc_i.data_valid),
167                         .adc_pd_o(adc_o.pd),
168                         .adc_chn_sel_o(adc_o.channel_sel),
169                         .chn0_val_we_o(chn0_val_we),
170                         .chn1_val_we_o(chn1_val_we),
171                         .chn0_val_o(chn0_val),
172                         .chn1_val_o(chn1_val),
173                         .adc_ctrl_done_o(adc_ctrl_done),
174                         .oneshot_done_o(oneshot_done),
175                         .aon_fsm_state_o,
176                         .aon_fsm_trans_o(aon_fsm_trans)
177                       );
178                     
179                       // synchronzie from clk_aon into cfg domain
180                       logic cfg_oneshot_done;
181                       prim_pulse_sync u_oneshot_done_sync (
182                         .clk_src_i(clk_aon_i),
183                         .rst_src_ni(rst_aon_ni),
184                         .src_pulse_i(oneshot_done),
185                         .clk_dst_i(clk_i),
186                         .rst_dst_ni(rst_ni),
187                         .dst_pulse_o(cfg_oneshot_done)
188                       );
189                     
190                       //Instantiate the interrupt module
191                       adc_ctrl_intr u_adc_ctrl_intr (
192                         .clk_i,
193                         .rst_ni,
194                         .clk_aon_i,
195                         .rst_aon_ni,
196                         .aon_filter_match_i(match_pulse),
197                         .aon_fsm_trans_i(aon_fsm_trans),
198                         .cfg_oneshot_done_i(cfg_oneshot_done),
199                         .cfg_intr_en_i(reg2hw_i.adc_intr_ctl.match_en.q),
200                         .cfg_intr_trans_en_i(reg2hw_i.adc_intr_ctl.trans_en.q),
201                         .cfg_oneshot_done_en_i(reg2hw_i.adc_intr_ctl.oneshot_en.q),
202                         .intr_state_i(reg2hw_i.intr_state),
203                         .intr_enable_i(reg2hw_i.intr_enable),
204                         .intr_test_i(reg2hw_i.intr_test),
205                         .intr_state_o,
206                         .adc_intr_status_i(reg2hw_i.adc_intr_status),
207                         .adc_intr_status_o,
208                         .intr_o
209                       );
210                     
211                       // unused register inputs
212                       logic unused_cfgs;
213        1/1            assign unused_cfgs = ^reg2hw_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T8,T9,T44
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T12
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T46,T85
0	1	Covered	T17,T46,T85
1	0	Covered	T8,T9,T44

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T8,T17,T45
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T45,T46
0	1	Covered	T17,T45,T46
1	0	Covered	T8,T17,T45

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T12,T17
0	1	Covered	T5,T17,T45
1	0	Covered	T5,T9,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T9,T11,T44
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T46,T85
0	1	Covered	T46,T85,T56
1	0	Covered	T9,T11,T44

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T5,T9,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T17
0	1	Covered	T5,T11,T17
1	0	Covered	T5,T9,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T9,T12,T17
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T45,T46
0	1	Covered	T17,T45,T46
1	0	Covered	T9,T12,T17

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T17,T85
0	1	Covered	T5,T17,T85
1	0	Covered	T5,T9,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T5,T9,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T13
0	1	Covered	T5,T11,T13
1	0	Covered	T5,T9,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T9,T11,T44
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T12
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T17,T56
0	1	Covered	T11,T17,T56
1	0	Covered	T9,T11,T44

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T5,T8,T9
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T45,T46
0	1	Covered	T5,T45,T46
1	0	Covered	T5,T8,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T5,T9,T16
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T17,T45
0	1	Covered	T5,T17,T45
1	0	Covered	T5,T9,T16

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T9,T11,T44
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T12
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T46,T85
0	1	Covered	T11,T46,T85
1	0	Covered	T9,T11,T44

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T5,T9,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T17
0	1	Covered	T5,T11,T17
1	0	Covered	T5,T9,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T9,T12,T17
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T45,T46
0	1	Covered	T17,T45,T46
1	0	Covered	T9,T12,T17

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T17,T85
0	1	Covered	T5,T17,T85
1	0	Covered	T5,T9,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T5,T9,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T13
0	1	Covered	T5,T11,T13
1	0	Covered	T5,T9,T11

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T11,T13,T14
1	1	1	Covered	T8,T9,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T8,T9,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T9,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T8,T9,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T9,T11

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T8,T9,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T8,T9,T13
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T9,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T14,T15
1	1	0	Covered	T11,T12,T13
1	1	1	Covered	T11,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T44
0	1	Covered	T11,T13,T14
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T44
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T12
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T44,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T14
0	1	Covered	T44,T13,T14
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T44,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T14
0	1	Covered	T44,T13,T14
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T44,T13,T14

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T9,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T44,T13
0	1	Covered	T9,T13,T14
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T44,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T44,T13
0	1	Covered	T9,T13,T14
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T44,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T13,T14

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T11,T13
1	1	0	Covered	T5,T8,T11
1	1	1	Covered	T5,T11,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T13
0	1	Covered	T5,T8,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T11
0	1	Covered	T5,T11,T13
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T11,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T12,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T11,T13,T14
1	1	1	Covered	T9,T11,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T9,T11,T13
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T9,T11,T13
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T9,T12,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T13
1	0	Covered	T5,T11,T12
1	1	Covered	T8,T9,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T8,T9
1	1	Covered	T11,T12,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T44,T13,T14
1	0	Covered	T5,T8,T9
1	1	Covered	T13,T14,T15

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T14
1	0	Covered	T5,T8,T11
1	1	Covered	T9,T13,T14

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T13
1	0	Covered	T8,T9,T11
1	1	Covered	T5,T11,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T8,T9
1	1	Covered	T12,T13,T14

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T13
1	0	Covered	T5,T8,T12
1	1	Covered	T9,T11,T13

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T12
1	0	Covered	T5,T9,T12

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T16,T37
1	0	Covered	T5,T8,T9

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T16
1	0	Covered	T9,T12,T15
1	1	Covered	T5,T16,T37

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

83           assign chn_val_intr_we = reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done :
                                                                         -1-  
                                                                         ==>  
84                                    reg2hw_i.adc_en_ctl.adc_enable.q   ? |match_pulse : '0;
                                                                         -2-  
                                                                         ==>  
                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T9,T44

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T11,T44

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T17,T45

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T9

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T12

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T16

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T11,T44

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T11,T44

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T11

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T11

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T12,T17

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T12,T17

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T12

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T12

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T11

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T11

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32651896	32375057	0	0
gen_filter_match[0].MatchCheck00_A	32651896	8975223	0	0
gen_filter_match[0].MatchCheck01_A	32651896	2697979	0	0
gen_filter_match[0].MatchCheck10_A	32651896	3256670	0	0
gen_filter_match[0].MatchCheck11_A	32651896	17445185	0	0
gen_filter_match[1].MatchCheck00_A	32651896	10239469	0	0
gen_filter_match[1].MatchCheck01_A	32651896	1162437	0	0
gen_filter_match[1].MatchCheck10_A	32651896	1799199	0	0
gen_filter_match[1].MatchCheck11_A	32651896	19173952	0	0
gen_filter_match[2].MatchCheck00_A	32651896	11263129	0	0
gen_filter_match[2].MatchCheck01_A	32651896	420765	0	0
gen_filter_match[2].MatchCheck10_A	32651896	583639	0	0
gen_filter_match[2].MatchCheck11_A	32651896	20107524	0	0
gen_filter_match[3].MatchCheck00_A	32651896	11816859	0	0
gen_filter_match[3].MatchCheck01_A	32651896	346564	0	0
gen_filter_match[3].MatchCheck10_A	32651896	457109	0	0
gen_filter_match[3].MatchCheck11_A	32651896	19754525	0	0
gen_filter_match[4].MatchCheck00_A	32651896	12455269	0	0
gen_filter_match[4].MatchCheck01_A	32651896	13	0	0
gen_filter_match[4].MatchCheck10_A	32651896	33829	0	0
gen_filter_match[4].MatchCheck11_A	32651896	19885946	0	0
gen_filter_match[5].MatchCheck00_A	32651896	11347240	0	0
gen_filter_match[5].MatchCheck01_A	32651896	13	0	0
gen_filter_match[5].MatchCheck10_A	32651896	81	0	0
gen_filter_match[5].MatchCheck11_A	32651896	21027723	0	0
gen_filter_match[6].MatchCheck00_A	32651896	11415486	0	0
gen_filter_match[6].MatchCheck01_A	32651896	34575	0	0
gen_filter_match[6].MatchCheck10_A	32651896	94	0	0
gen_filter_match[6].MatchCheck11_A	32651896	20924902	0	0
gen_filter_match[7].MatchCheck00_A	32651896	11520433	0	0
gen_filter_match[7].MatchCheck01_A	32651896	97858	0	0
gen_filter_match[7].MatchCheck10_A	32651896	71719	0	0
gen_filter_match[7].MatchCheck11_A	32651896	20685047	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	32375057	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	51907	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	412	0	0
T9	1256	852	0	0
T18	63	5	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	8975223	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	51907	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	337	0	0
T9	1256	33	0	0
T18	63	5	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	2697979	0	0
T21	682	0	0	0
T31	5672	0	0	0
T32	31972	0	0	0
T33	570	0	0	0
T34	32793	0	0	0
T35	97512	32551	0	0
T36	33949	0	0	0
T37	79641	0	0	0
T38	103	0	0	0
T52	0	4027	0	0
T139	0	53610	0	0
T141	66017	33202	0	0
T142	0	65983	0	0
T143	0	32576	0	0
T144	0	33149	0	0
T145	0	33272	0	0
T146	0	70266	0	0
T147	0	32627	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	3256670	0	0
T11	32574	3	0	0
T12	21387	0	0	0
T17	0	33297	0	0
T37	0	2	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0
T55	1461	0	0	0
T60	4220	0	0	0
T64	1076	0	0	0
T83	1577	0	0	0
T85	0	33813	0	0
T137	0	1247	0	0
T140	0	68983	0	0
T148	0	32619	0	0
T149	0	33615	0	0
T150	0	1	0	0
T151	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	17445185	0	0
T8	1109	75	0	0
T9	1256	819	0	0
T10	1144	0	0	0
T11	32574	32505	0	0
T12	0	20258	0	0
T13	0	32457	0	0
T14	0	31960	0	0
T15	0	39871	0	0
T16	0	989	0	0
T17	0	36647	0	0
T19	1577	0	0	0
T20	1690	0	0	0
T46	0	32314	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	10239469	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	51907	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	106	0	0
T9	1256	33	0	0
T18	63	5	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	1162437	0	0
T9	1256	819	0	0
T10	1144	0	0	0
T11	32574	0	0	0
T19	1577	0	0	0
T20	1690	0	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0
T55	1461	0	0	0
T105	0	1	0	0
T147	0	1	0	0
T152	0	33079	0	0
T153	0	34482	0	0
T154	0	32296	0	0
T155	0	70438	0	0
T156	0	1050	0	0
T157	0	1582	0	0
T158	0	33131	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	1799199	0	0
T17	70040	36648	0	0
T37	0	2	0	0
T45	36974	34435	0	0
T46	32381	0	0	0
T47	64877	0	0	0
T56	33641	0	0	0
T84	1575	0	0	0
T85	67546	0	0	0
T111	602	0	0	0
T139	0	1	0	0
T141	0	32715	0	0
T145	0	34335	0	0
T150	0	1	0	0
T152	33153	0	0	0
T159	0	37311	0	0
T160	0	32244	0	0
T161	0	42489	0	0
T162	82	0	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	19173952	0	0
T8	1109	306	0	0
T9	1256	0	0	0
T10	1144	0	0	0
T11	32574	0	0	0
T13	0	32457	0	0
T14	0	31960	0	0
T15	0	39871	0	0
T16	0	904	0	0
T17	0	33296	0	0
T19	1577	0	0	0
T20	1690	0	0	0
T32	0	31891	0	0
T34	0	32718	0	0
T35	0	32551	0	0
T47	0	64815	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	11263129	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	51907	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	106	0	0
T9	1256	852	0	0
T18	63	5	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	420765	0	0
T12	21387	19905	0	0
T13	32536	0	0	0
T14	32033	0	0	0
T15	39967	0	0	0
T32	0	31891	0	0
T44	510	0	0	0
T53	0	1619	0	0
T65	6901	0	0	0
T83	1577	0	0	0
T105	0	1	0	0
T110	1194	0	0	0
T139	0	1	0	0
T147	0	1	0	0
T151	0	31746	0	0
T163	0	31861	0	0
T164	0	35929	0	0
T165	0	2	0	0
T166	74	0	0	0
T167	736	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	583639	0	0
T11	32574	2	0	0
T12	21387	0	0	0
T37	0	2	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0
T55	1461	0	0	0
T60	4220	0	0	0
T64	1076	0	0	0
T83	1577	0	0	0
T85	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T159	0	1	0	0
T164	0	35037	0	0
T168	0	1	0	0
T169	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	20107524	0	0
T8	1109	306	0	0
T9	1256	0	0	0
T10	1144	0	0	0
T11	32574	32505	0	0
T13	0	32457	0	0
T14	0	31960	0	0
T15	0	39871	0	0
T16	0	904	0	0
T19	1577	0	0	0
T20	1690	0	0	0
T44	0	178	0	0
T45	0	34435	0	0
T46	0	32314	0	0
T47	0	64815	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	11816859	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	51907	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	106	0	0
T9	1256	852	0	0
T18	63	5	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	346564	0	0
T145	102063	0	0	0
T168	0	1	0	0
T170	72785	1	0	0
T171	0	32374	0	0
T172	0	37527	0	0
T173	0	36831	0	0
T174	0	32401	0	0
T175	0	30257	0	0
T176	0	32565	0	0
T177	0	33464	0	0
T178	0	37540	0	0
T179	1149	0	0	0
T180	38557	0	0	0
T181	32732	0	0	0
T182	33859	0	0	0
T183	37123	0	0	0
T184	17678	0	0	0
T185	66725	0	0	0
T186	5619	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	457109	0	0
T21	682	0	0	0
T31	5672	0	0	0
T32	31972	0	0	0
T37	0	2	0	0
T56	33641	1	0	0
T85	67546	1	0	0
T111	602	0	0	0
T141	66017	0	0	0
T143	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0
T150	0	1	0	0
T152	33153	0	0	0
T162	82	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T187	0	1	0	0
T188	1134	0	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	19754525	0	0
T8	1109	306	0	0
T9	1256	0	0	0
T10	1144	0	0	0
T11	32574	0	0	0
T13	0	32457	0	0
T14	0	31960	0	0
T15	0	39871	0	0
T19	1577	0	0	0
T20	1690	0	0	0
T32	0	31891	0	0
T44	0	178	0	0
T47	0	64815	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0
T56	0	33569	0	0
T85	0	33812	0	0
T141	0	32715	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	12455269	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	51907	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	106	0	0
T9	1256	33	0	0
T18	63	5	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	13	0	0
T21	682	0	0	0
T31	5672	0	0	0
T32	31972	0	0	0
T56	33641	0	0	0
T85	67546	1	0	0
T111	602	0	0	0
T141	66017	0	0	0
T148	0	1	0	0
T152	33153	0	0	0
T153	0	1	0	0
T162	82	0	0	0
T165	0	2	0	0
T178	0	1	0	0
T188	1134	0	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	33829	0	0
T21	682	0	0	0
T31	5672	0	0	0
T32	31972	0	0	0
T37	0	2	0	0
T56	33641	0	0	0
T85	67546	1	0	0
T111	602	0	0	0
T139	0	1	0	0
T141	66017	0	0	0
T143	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T152	33153	0	0	0
T153	0	2	0	0
T159	0	1	0	0
T162	82	0	0	0
T182	0	33763	0	0
T188	1134	0	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	19885946	0	0
T8	1109	306	0	0
T9	1256	819	0	0
T10	1144	0	0	0
T11	32574	0	0	0
T13	0	32457	0	0
T14	0	31960	0	0
T15	0	39871	0	0
T16	0	904	0	0
T19	1577	0	0	0
T20	1690	0	0	0
T44	0	178	0	0
T45	0	34435	0	0
T46	0	32314	0	0
T47	0	64815	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	11347240	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	3	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	106	0	0
T9	1256	852	0	0
T18	63	5	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	13	0	0
T142	66085	0	0	0
T143	34669	0	0	0
T153	120820	1	0	0
T165	0	2	0	0
T168	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T189	0	1	0	0
T191	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	2	0	0
T196	32480	0	0	0
T197	65307	0	0	0
T198	8637	0	0	0
T199	963	0	0	0
T200	64323	0	0	0
T201	33496	0	0	0
T202	67	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	81	0	0
T11	32574	2	0	0
T12	21387	0	0	0
T17	0	1	0	0
T37	0	2	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0
T55	1461	0	0	0
T60	4220	0	0	0
T64	1076	0	0	0
T83	1577	0	0	0
T85	0	1	0	0
T139	0	1	0	0
T143	0	1	0	0
T148	0	1	0	0
T153	0	1	0	0
T159	0	1	0	0
T197	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	21027723	0	0
T5	51986	51904	0	0
T6	6109	0	0	0
T7	960	0	0	0
T8	1109	306	0	0
T9	1256	0	0	0
T10	1144	0	0	0
T11	32574	32504	0	0
T13	0	32457	0	0
T14	0	31960	0	0
T15	0	39871	0	0
T17	0	36646	0	0
T18	63	0	0	0
T19	1577	0	0	0
T20	1690	0	0	0
T45	0	34435	0	0
T47	0	64815	0	0
T85	0	67447	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	11415486	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	51907	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	412	0	0
T9	1256	852	0	0
T18	63	5	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	34575	0	0
T17	70040	1	0	0
T45	36974	0	0	0
T46	32381	0	0	0
T47	64877	0	0	0
T56	33641	0	0	0
T84	1575	0	0	0
T85	67546	0	0	0
T111	602	0	0	0
T148	0	1	0	0
T152	33153	0	0	0
T153	0	1	0	0
T162	82	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T192	0	1	0	0
T195	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	94	0	0
T17	70040	1	0	0
T37	0	3	0	0
T45	36974	1	0	0
T46	32381	0	0	0
T47	64877	0	0	0
T53	0	2	0	0
T56	33641	0	0	0
T84	1575	0	0	0
T85	67546	0	0	0
T111	602	0	0	0
T145	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T152	33153	0	0	0
T153	0	1	0	0
T162	82	0	0	0
T170	0	1	0	0
T197	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	20924902	0	0
T12	21387	19905	0	0
T13	32536	32457	0	0
T14	32033	31960	0	0
T15	39967	39871	0	0
T17	0	33296	0	0
T34	0	32718	0	0
T35	0	97441	0	0
T44	510	0	0	0
T45	0	34434	0	0
T47	0	64815	0	0
T65	6901	0	0	0
T83	1577	0	0	0
T110	1194	0	0	0
T141	0	33202	0	0
T166	74	0	0	0
T167	736	0	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	11520433	0	0
T1	111	13	0	0
T2	1155	1055	0	0
T3	1150	1095	0	0
T4	1057	979	0	0
T5	51986	51907	0	0
T6	6109	6016	0	0
T7	960	901	0	0
T8	1109	412	0	0
T9	1256	33	0	0
T18	63	5	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	97858	0	0
T17	70040	1	0	0
T45	36974	0	0	0
T46	32381	0	0	0
T47	64877	0	0	0
T56	33641	0	0	0
T84	1575	0	0	0
T85	67546	0	0	0
T105	0	1	0	0
T111	602	0	0	0
T145	0	1	0	0
T148	0	1	0	0
T152	33153	0	0	0
T162	82	0	0	0
T165	0	2	0	0
T189	0	1	0	0
T196	0	32399	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	71719	0	0
T11	32574	3	0	0
T12	21387	0	0	0
T17	0	1	0	0
T37	0	2	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0
T55	1461	0	0	0
T56	0	1	0	0
T60	4220	0	0	0
T64	1076	0	0	0
T83	1577	0	0	0
T85	0	1	0	0
T139	0	1	0	0
T148	0	1	0	0
T159	0	1	0	0
T197	0	1	0	0
T206	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32651896	20685047	0	0
T9	1256	819	0	0
T10	1144	0	0	0
T11	32574	32503	0	0
T13	0	32457	0	0
T14	0	31960	0	0
T15	0	39871	0	0
T16	0	904	0	0
T17	0	33296	0	0
T19	1577	0	0	0
T20	1690	0	0	0
T47	0	64815	0	0
T48	59	0	0	0
T49	688	0	0	0
T50	1169	0	0	0
T51	4393	0	0	0
T55	1461	0	0	0
T56	0	33569	0	0
T85	0	33812	0	0