Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1598	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1331	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1584	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1506	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1413	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1563	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1392	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1448	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1470	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1486	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1268	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1672	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1460	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1573	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1348	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1525	0	0
adc_en_ctl_rd_A	2147483647	1236	0	0
adc_fsm_rst_rd_A	2147483647	943	0	0
adc_intr_ctl_rd_A	2147483647	1514	0	0
adc_lp_sample_ctl_rd_A	2147483647	1073	0	0
adc_pd_ctl_rd_A	2147483647	1278	0	0
adc_sample_ctl_rd_A	2147483647	1028	0	0
adc_wakeup_ctl_rd_A	2147483647	1218	0	0
intr_enable_rd_A	2147483647	1629	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1598	0	0
T21	338469	13	0	0
T22	0	12	0	0
T23	0	23	0	0
T24	0	16	0	0
T25	0	38	0	0
T26	0	14	0	0
T27	0	29	0	0
T28	0	9	0	0
T29	0	20	0	0
T30	0	32	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1331	0	0
T21	338469	15	0	0
T22	0	18	0	0
T23	0	19	0	0
T24	0	6	0	0
T25	0	40	0	0
T26	0	18	0	0
T27	0	26	0	0
T28	0	13	0	0
T29	0	16	0	0
T30	0	33	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1584	0	0
T21	338469	19	0	0
T22	0	15	0	0
T23	0	34	0	0
T24	0	36	0	0
T25	0	32	0	0
T26	0	41	0	0
T27	0	28	0	0
T28	0	34	0	0
T29	0	8	0	0
T30	0	16	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1506	0	0
T21	338469	28	0	0
T22	0	16	0	0
T23	0	7	0	0
T24	0	20	0	0
T25	0	36	0	0
T26	0	24	0	0
T27	0	43	0	0
T28	0	20	0	0
T29	0	24	0	0
T30	0	16	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1413	0	0
T21	338469	22	0	0
T22	0	13	0	0
T23	0	14	0	0
T24	0	3	0	0
T25	0	41	0	0
T26	0	10	0	0
T27	0	14	0	0
T28	0	22	0	0
T29	0	23	0	0
T30	0	35	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1563	0	0
T21	338469	24	0	0
T22	0	24	0	0
T23	0	18	0	0
T24	0	23	0	0
T25	0	30	0	0
T26	0	22	0	0
T27	0	12	0	0
T28	0	17	0	0
T29	0	15	0	0
T30	0	18	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1392	0	0
T21	338469	16	0	0
T22	0	14	0	0
T23	0	20	0	0
T24	0	24	0	0
T25	0	25	0	0
T26	0	26	0	0
T27	0	18	0	0
T28	0	24	0	0
T29	0	12	0	0
T30	0	12	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1448	0	0
T21	338469	24	0	0
T22	0	13	0	0
T23	0	13	0	0
T24	0	14	0	0
T25	0	52	0	0
T26	0	25	0	0
T27	0	17	0	0
T28	0	25	0	0
T29	0	21	0	0
T30	0	8	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1470	0	0
T21	338469	4	0	0
T22	0	20	0	0
T23	0	15	0	0
T24	0	22	0	0
T25	0	38	0	0
T26	0	8	0	0
T27	0	15	0	0
T28	0	22	0	0
T29	0	13	0	0
T30	0	28	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1486	0	0
T21	338469	33	0	0
T22	0	10	0	0
T23	0	2	0	0
T24	0	16	0	0
T25	0	37	0	0
T26	0	30	0	0
T27	0	17	0	0
T28	0	16	0	0
T29	0	14	0	0
T30	0	27	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1268	0	0
T21	338469	30	0	0
T22	0	17	0	0
T23	0	20	0	0
T24	0	15	0	0
T25	0	35	0	0
T26	0	29	0	0
T27	0	14	0	0
T28	0	8	0	0
T29	0	15	0	0
T30	0	15	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1672	0	0
T21	338469	27	0	0
T22	0	21	0	0
T23	0	24	0	0
T24	0	15	0	0
T25	0	27	0	0
T26	0	17	0	0
T28	0	15	0	0
T29	0	25	0	0
T30	0	26	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0
T40	0	5	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1460	0	0
T21	338469	38	0	0
T22	0	26	0	0
T23	0	10	0	0
T24	0	21	0	0
T25	0	45	0	0
T26	0	11	0	0
T27	0	13	0	0
T28	0	17	0	0
T29	0	17	0	0
T30	0	19	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1573	0	0
T21	338469	14	0	0
T22	0	17	0	0
T23	0	6	0	0
T24	0	25	0	0
T25	0	39	0	0
T26	0	21	0	0
T27	0	20	0	0
T28	0	17	0	0
T29	0	20	0	0
T30	0	26	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1348	0	0
T21	338469	21	0	0
T22	0	3	0	0
T23	0	13	0	0
T24	0	5	0	0
T25	0	40	0	0
T26	0	19	0	0
T27	0	15	0	0
T28	0	16	0	0
T29	0	11	0	0
T30	0	10	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1525	0	0
T21	338469	4	0	0
T22	0	18	0	0
T23	0	14	0	0
T24	0	22	0	0
T25	0	34	0	0
T26	0	17	0	0
T27	0	30	0	0
T28	0	16	0	0
T29	0	24	0	0
T30	0	21	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1236	0	0
T21	338469	18	0	0
T22	0	18	0	0
T23	0	53	0	0
T24	0	23	0	0
T25	0	39	0	0
T26	0	24	0	0
T27	0	29	0	0
T28	0	21	0	0
T29	0	19	0	0
T30	0	28	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	943	0	0
T21	338469	24	0	0
T22	0	26	0	0
T23	0	38	0	0
T24	0	22	0	0
T25	0	28	0	0
T26	0	11	0	0
T27	0	4	0	0
T28	0	13	0	0
T29	0	29	0	0
T30	0	28	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1514	0	0
T21	338469	24	0	0
T22	0	14	0	0
T23	0	33	0	0
T24	0	14	0	0
T25	0	39	0	0
T26	0	23	0	0
T27	0	9	0	0
T28	0	13	0	0
T29	0	21	0	0
T30	0	18	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073	0	0
T21	338469	16	0	0
T22	0	19	0	0
T23	0	19	0	0
T24	0	29	0	0
T25	0	44	0	0
T26	0	19	0	0
T27	0	13	0	0
T28	0	26	0	0
T29	0	19	0	0
T30	0	15	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1278	0	0
T21	338469	42	0	0
T22	0	12	0	0
T23	0	14	0	0
T24	0	14	0	0
T25	0	48	0	0
T26	0	17	0	0
T27	0	14	0	0
T28	0	20	0	0
T29	0	12	0	0
T30	0	17	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1028	0	0
T21	338469	11	0	0
T22	0	3	0	0
T23	0	12	0	0
T24	0	21	0	0
T25	0	45	0	0
T26	0	31	0	0
T27	0	12	0	0
T28	0	16	0	0
T29	0	22	0	0
T30	0	12	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1218	0	0
T21	338469	10	0	0
T22	0	22	0	0
T23	0	24	0	0
T24	0	20	0	0
T25	0	41	0	0
T26	0	32	0	0
T27	0	18	0	0
T28	0	28	0	0
T29	0	23	0	0
T30	0	19	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
T34	803467	0	0	0
T35	975139	0	0	0
T36	424379	0	0	0
T37	318566	0	0	0
T38	12567	0	0	0
T39	345124	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1629	0	0
T21	338469	38	0	0
T22	0	15	0	0
T23	0	24	0	0
T24	0	37	0	0
T25	0	32	0	0
T26	0	23	0	0
T27	0	46	0	0
T31	138986	0	0	0
T32	783354	0	0	0
T33	142834	0	0	0
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