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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.07 96.67 100.00 100.00 98.82 98.33 90.99


Total test records in report: 919
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T802 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.2114856547 Sep 18 07:41:15 AM UTC 24 Sep 18 08:05:50 AM UTC 24 514846136666 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.2789387635 Sep 18 07:40:33 AM UTC 24 Sep 18 08:06:03 AM UTC 24 501928409006 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.7010599 Sep 18 07:39:31 AM UTC 24 Sep 18 08:06:35 AM UTC 24 549092815348 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1553395707 Sep 18 07:41:55 AM UTC 24 Sep 18 09:16:42 AM UTC 24 1875980569845 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.4288243346 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:07 AM UTC 24 324627870 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1196713385 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:07 AM UTC 24 705345719 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.962504263 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:08 AM UTC 24 378571473 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1510910813 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:08 AM UTC 24 420714412 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2050064560 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:08 AM UTC 24 369986200 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.924684861 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:09 AM UTC 24 683371406 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1753266524 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:09 AM UTC 24 908551924 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1139391189 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:09 AM UTC 24 1083086013 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1856086318 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:10 AM UTC 24 726748259 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3204227951 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:10 AM UTC 24 465171041 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2047786209 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:24 AM UTC 24 406206834 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.71162938 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:10 AM UTC 24 395601981 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3785369775 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:10 AM UTC 24 399919091 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2708537187 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:11 AM UTC 24 606245176 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2198825403 Sep 18 06:10:08 AM UTC 24 Sep 18 06:10:11 AM UTC 24 410499189 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.946850235 Sep 18 06:10:09 AM UTC 24 Sep 18 06:10:11 AM UTC 24 476161430 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.939473860 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:12 AM UTC 24 979488677 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2011868505 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:13 AM UTC 24 1285496550 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3885625297 Sep 18 06:10:09 AM UTC 24 Sep 18 06:10:13 AM UTC 24 548324285 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1594606551 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:13 AM UTC 24 1088726381 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2725540583 Sep 18 06:10:10 AM UTC 24 Sep 18 06:10:13 AM UTC 24 951503269 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.415870527 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:13 AM UTC 24 8303998511 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3663360327 Sep 18 06:10:10 AM UTC 24 Sep 18 06:10:14 AM UTC 24 370859259 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1550841101 Sep 18 06:10:11 AM UTC 24 Sep 18 06:10:14 AM UTC 24 430211191 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3320899943 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:14 AM UTC 24 4442139309 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2219938358 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:24 AM UTC 24 1654159704 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.391685307 Sep 18 06:10:26 AM UTC 24 Sep 18 06:10:29 AM UTC 24 654160220 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3612883893 Sep 18 06:10:11 AM UTC 24 Sep 18 06:10:15 AM UTC 24 496474671 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2455928831 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:15 AM UTC 24 919261945 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2117186944 Sep 18 06:10:11 AM UTC 24 Sep 18 06:10:15 AM UTC 24 557271987 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1040591034 Sep 18 06:10:10 AM UTC 24 Sep 18 06:10:15 AM UTC 24 1346563585 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3963411584 Sep 18 06:10:11 AM UTC 24 Sep 18 06:10:15 AM UTC 24 2474544269 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3719179468 Sep 18 06:10:13 AM UTC 24 Sep 18 06:10:15 AM UTC 24 537537222 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4053283166 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:15 AM UTC 24 4434379243 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.775724227 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:16 AM UTC 24 4245209427 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3605256598 Sep 18 06:10:13 AM UTC 24 Sep 18 06:10:16 AM UTC 24 1105581383 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.173079279 Sep 18 06:10:14 AM UTC 24 Sep 18 06:10:17 AM UTC 24 541419493 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.466712819 Sep 18 06:10:13 AM UTC 24 Sep 18 06:10:17 AM UTC 24 365931763 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1614958472 Sep 18 06:10:14 AM UTC 24 Sep 18 06:10:17 AM UTC 24 366414198 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2606744874 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:17 AM UTC 24 11721981566 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3062822897 Sep 18 06:10:14 AM UTC 24 Sep 18 06:10:17 AM UTC 24 432951418 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3054956067 Sep 18 06:10:13 AM UTC 24 Sep 18 06:10:18 AM UTC 24 4351512136 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.300787964 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:18 AM UTC 24 593388250 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4057336014 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:18 AM UTC 24 4014494792 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3988336440 Sep 18 06:10:14 AM UTC 24 Sep 18 06:10:19 AM UTC 24 833457722 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.726036901 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:19 AM UTC 24 432433254 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.2659704481 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:19 AM UTC 24 443376672 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.964482483 Sep 18 06:10:17 AM UTC 24 Sep 18 06:10:19 AM UTC 24 366854652 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.135952083 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:19 AM UTC 24 448244626 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1962015240 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:19 AM UTC 24 535961651 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1502178981 Sep 18 06:10:17 AM UTC 24 Sep 18 06:10:20 AM UTC 24 396743298 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2400405515 Sep 18 06:10:17 AM UTC 24 Sep 18 06:10:20 AM UTC 24 431848897 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3017663895 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:20 AM UTC 24 1854375526 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1673602254 Sep 18 06:10:19 AM UTC 24 Sep 18 06:10:21 AM UTC 24 364420122 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.3303762336 Sep 18 06:10:18 AM UTC 24 Sep 18 06:10:21 AM UTC 24 359385157 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2822053209 Sep 18 06:10:18 AM UTC 24 Sep 18 06:10:22 AM UTC 24 557913286 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.989063287 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:22 AM UTC 24 4108251494 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3929193987 Sep 18 06:10:09 AM UTC 24 Sep 18 06:10:22 AM UTC 24 4064731555 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.423082018 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:23 AM UTC 24 477894964 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1666623654 Sep 18 06:10:14 AM UTC 24 Sep 18 06:10:23 AM UTC 24 8743447027 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2092973076 Sep 18 06:10:17 AM UTC 24 Sep 18 06:10:23 AM UTC 24 8382256306 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2390222587 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:23 AM UTC 24 516235303 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2450837652 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:23 AM UTC 24 2265164093 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3557653511 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:23 AM UTC 24 583309872 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.351787180 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:23 AM UTC 24 515714530 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2471735844 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:24 AM UTC 24 491421437 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3285896874 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:24 AM UTC 24 376291130 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3864178935 Sep 18 06:10:22 AM UTC 24 Sep 18 06:10:25 AM UTC 24 481845370 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2544443802 Sep 18 06:10:16 AM UTC 24 Sep 18 06:10:26 AM UTC 24 8024552206 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2298105445 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:26 AM UTC 24 3251634336 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1554734249 Sep 18 06:10:25 AM UTC 24 Sep 18 06:10:29 AM UTC 24 745467594 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.336412744 Sep 18 06:10:18 AM UTC 24 Sep 18 06:10:26 AM UTC 24 4493074523 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.898661028 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:27 AM UTC 24 4384983835 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.925345790 Sep 18 06:10:23 AM UTC 24 Sep 18 06:10:27 AM UTC 24 447907995 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2243419788 Sep 18 06:10:24 AM UTC 24 Sep 18 06:10:27 AM UTC 24 378460449 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2026039169 Sep 18 06:10:24 AM UTC 24 Sep 18 06:10:28 AM UTC 24 522859344 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.390785994 Sep 18 06:10:23 AM UTC 24 Sep 18 06:10:28 AM UTC 24 772818066 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2037048538 Sep 18 06:10:24 AM UTC 24 Sep 18 06:10:28 AM UTC 24 345389866 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2867944123 Sep 18 06:10:24 AM UTC 24 Sep 18 06:10:28 AM UTC 24 522080405 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2181351685 Sep 18 06:10:05 AM UTC 24 Sep 18 06:10:29 AM UTC 24 8311382709 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2839209050 Sep 18 06:10:26 AM UTC 24 Sep 18 06:10:29 AM UTC 24 392739960 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4077285719 Sep 18 06:10:25 AM UTC 24 Sep 18 06:10:29 AM UTC 24 432422094 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2701268348 Sep 18 06:10:19 AM UTC 24 Sep 18 06:10:29 AM UTC 24 2176415440 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1455812345 Sep 18 06:10:24 AM UTC 24 Sep 18 06:10:30 AM UTC 24 490603190 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2156849591 Sep 18 06:10:25 AM UTC 24 Sep 18 06:10:30 AM UTC 24 2760209585 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1154592886 Sep 18 06:10:26 AM UTC 24 Sep 18 06:10:30 AM UTC 24 2328621131 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.201667275 Sep 18 06:10:22 AM UTC 24 Sep 18 06:10:30 AM UTC 24 4577896088 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3161796312 Sep 18 06:10:24 AM UTC 24 Sep 18 06:10:31 AM UTC 24 2800348780 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.845283150 Sep 18 06:10:27 AM UTC 24 Sep 18 06:10:31 AM UTC 24 407110072 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3637645387 Sep 18 06:10:27 AM UTC 24 Sep 18 06:10:31 AM UTC 24 428756346 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1903128167 Sep 18 06:10:28 AM UTC 24 Sep 18 06:10:31 AM UTC 24 477433392 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2747250473 Sep 18 06:10:28 AM UTC 24 Sep 18 06:10:31 AM UTC 24 449375033 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3740514560 Sep 18 06:10:28 AM UTC 24 Sep 18 06:10:31 AM UTC 24 599538513 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.257037111 Sep 18 06:10:30 AM UTC 24 Sep 18 06:10:32 AM UTC 24 420542961 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4221716385 Sep 18 06:10:29 AM UTC 24 Sep 18 06:10:32 AM UTC 24 688766339 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.890903684 Sep 18 06:10:29 AM UTC 24 Sep 18 06:10:32 AM UTC 24 495953629 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2415246898 Sep 18 06:10:29 AM UTC 24 Sep 18 06:10:33 AM UTC 24 2743556168 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1905287286 Sep 18 06:10:27 AM UTC 24 Sep 18 06:10:33 AM UTC 24 10685739578 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3087858281 Sep 18 06:10:25 AM UTC 24 Sep 18 06:10:33 AM UTC 24 9285669267 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3237287352 Sep 18 06:10:29 AM UTC 24 Sep 18 06:10:33 AM UTC 24 531685939 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.1705251271 Sep 18 06:10:31 AM UTC 24 Sep 18 06:10:33 AM UTC 24 495117468 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.3801650437 Sep 18 06:10:40 AM UTC 24 Sep 18 06:10:42 AM UTC 24 330219806 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.4263407669 Sep 18 06:10:40 AM UTC 24 Sep 18 06:10:43 AM UTC 24 498707932 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3885823113 Sep 18 06:10:31 AM UTC 24 Sep 18 06:10:34 AM UTC 24 343208355 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1302947692 Sep 18 06:10:31 AM UTC 24 Sep 18 06:10:34 AM UTC 24 466588743 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1286511 Sep 18 06:10:32 AM UTC 24 Sep 18 06:10:34 AM UTC 24 503428939 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3124389479 Sep 18 06:10:11 AM UTC 24 Sep 18 06:10:34 AM UTC 24 8236582341 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2521156507 Sep 18 06:10:28 AM UTC 24 Sep 18 06:10:35 AM UTC 24 5060129786 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1521296332 Sep 18 06:10:31 AM UTC 24 Sep 18 06:10:35 AM UTC 24 513214234 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.877443356 Sep 18 06:10:32 AM UTC 24 Sep 18 06:10:35 AM UTC 24 546687518 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1187383295 Sep 18 06:10:32 AM UTC 24 Sep 18 06:10:35 AM UTC 24 590491836 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1268759042 Sep 18 06:10:33 AM UTC 24 Sep 18 06:10:35 AM UTC 24 766624866 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.3261238805 Sep 18 06:10:33 AM UTC 24 Sep 18 06:10:36 AM UTC 24 495634218 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2580621707 Sep 18 06:10:17 AM UTC 24 Sep 18 06:10:36 AM UTC 24 4910417533 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2056748564 Sep 18 06:10:31 AM UTC 24 Sep 18 06:10:36 AM UTC 24 4067502792 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2214198134 Sep 18 06:10:31 AM UTC 24 Sep 18 06:10:36 AM UTC 24 1131138043 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1600337365 Sep 18 06:10:33 AM UTC 24 Sep 18 06:10:36 AM UTC 24 374792184 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1441035486 Sep 18 06:10:32 AM UTC 24 Sep 18 06:10:36 AM UTC 24 525409977 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2604694810 Sep 18 06:10:35 AM UTC 24 Sep 18 06:10:37 AM UTC 24 530078775 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3347427706 Sep 18 06:10:32 AM UTC 24 Sep 18 06:10:37 AM UTC 24 4191938266 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3859396659 Sep 18 06:10:35 AM UTC 24 Sep 18 06:10:37 AM UTC 24 448241436 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2314344972 Sep 18 06:10:23 AM UTC 24 Sep 18 06:10:37 AM UTC 24 8207914759 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1250372162 Sep 18 06:10:40 AM UTC 24 Sep 18 06:10:43 AM UTC 24 416497374 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3531563933 Sep 18 06:10:24 AM UTC 24 Sep 18 06:10:37 AM UTC 24 4020946514 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.572373286 Sep 18 06:10:35 AM UTC 24 Sep 18 06:10:38 AM UTC 24 576007184 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2079403252 Sep 18 06:10:35 AM UTC 24 Sep 18 06:10:38 AM UTC 24 530402460 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3207472550 Sep 18 06:10:35 AM UTC 24 Sep 18 06:10:38 AM UTC 24 661924153 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.730289000 Sep 18 06:10:36 AM UTC 24 Sep 18 06:10:38 AM UTC 24 478760082 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.335886399 Sep 18 06:10:36 AM UTC 24 Sep 18 06:10:38 AM UTC 24 594965193 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.1000775811 Sep 18 06:10:36 AM UTC 24 Sep 18 06:10:38 AM UTC 24 475531902 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.519442667 Sep 18 06:10:31 AM UTC 24 Sep 18 06:10:38 AM UTC 24 3869911399 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1239280097 Sep 18 06:10:36 AM UTC 24 Sep 18 06:10:38 AM UTC 24 389209757 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1039849783 Sep 18 06:10:36 AM UTC 24 Sep 18 06:10:38 AM UTC 24 290933883 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.457748074 Sep 18 06:10:32 AM UTC 24 Sep 18 06:10:39 AM UTC 24 4752804914 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1109636321 Sep 18 06:10:37 AM UTC 24 Sep 18 06:10:39 AM UTC 24 547679878 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.917606903 Sep 18 06:10:37 AM UTC 24 Sep 18 06:10:39 AM UTC 24 441227566 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.2273795852 Sep 18 06:10:37 AM UTC 24 Sep 18 06:10:39 AM UTC 24 421649029 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.1329826096 Sep 18 06:10:37 AM UTC 24 Sep 18 06:10:39 AM UTC 24 420344986 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2190515600 Sep 18 06:10:37 AM UTC 24 Sep 18 06:10:40 AM UTC 24 525792732 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1542379075 Sep 18 06:10:37 AM UTC 24 Sep 18 06:10:40 AM UTC 24 323500426 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.872962974 Sep 18 06:10:35 AM UTC 24 Sep 18 06:10:40 AM UTC 24 2309339299 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2431009078 Sep 18 06:10:20 AM UTC 24 Sep 18 06:10:45 AM UTC 24 8423663661 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.3880703294 Sep 18 06:10:38 AM UTC 24 Sep 18 06:10:40 AM UTC 24 512114188 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.722649411 Sep 18 06:10:37 AM UTC 24 Sep 18 06:10:41 AM UTC 24 509113703 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.3269308757 Sep 18 06:10:39 AM UTC 24 Sep 18 06:10:41 AM UTC 24 528485807 ps
T901 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.730143073 Sep 18 06:10:39 AM UTC 24 Sep 18 06:10:41 AM UTC 24 555932370 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.3543736927 Sep 18 06:10:39 AM UTC 24 Sep 18 06:10:41 AM UTC 24 463836959 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.316216517 Sep 18 06:10:38 AM UTC 24 Sep 18 06:10:41 AM UTC 24 483500894 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3462795191 Sep 18 06:10:39 AM UTC 24 Sep 18 06:10:41 AM UTC 24 315206279 ps
T905 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.1199940537 Sep 18 06:10:38 AM UTC 24 Sep 18 06:10:41 AM UTC 24 395587878 ps
T906 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.25628041 Sep 18 06:10:39 AM UTC 24 Sep 18 06:10:42 AM UTC 24 477061268 ps
T907 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.4026724936 Sep 18 06:10:40 AM UTC 24 Sep 18 06:10:42 AM UTC 24 514835185 ps
T908 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.73375197 Sep 18 06:10:40 AM UTC 24 Sep 18 06:10:42 AM UTC 24 343809179 ps
T909 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.605819254 Sep 18 06:10:39 AM UTC 24 Sep 18 06:10:42 AM UTC 24 525652388 ps
T910 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.3090911677 Sep 18 06:10:40 AM UTC 24 Sep 18 06:10:42 AM UTC 24 495381316 ps
T911 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.1987206640 Sep 18 06:10:40 AM UTC 24 Sep 18 06:10:42 AM UTC 24 483184723 ps
T912 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.480730951 Sep 18 06:10:40 AM UTC 24 Sep 18 06:10:42 AM UTC 24 355563180 ps
T913 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3823956955 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:46 AM UTC 24 53303018130 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3228532358 Sep 18 06:10:35 AM UTC 24 Sep 18 06:10:47 AM UTC 24 4093842374 ps
T914 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2032020612 Sep 18 06:10:33 AM UTC 24 Sep 18 06:10:54 AM UTC 24 4701175922 ps
T915 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.246944775 Sep 18 06:10:29 AM UTC 24 Sep 18 06:10:55 AM UTC 24 8422171754 ps
T916 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1206414744 Sep 18 06:10:33 AM UTC 24 Sep 18 06:10:56 AM UTC 24 8184438375 ps
T917 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.32905781 Sep 18 06:10:07 AM UTC 24 Sep 18 06:10:59 AM UTC 24 26948031360 ps
T918 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4165646928 Sep 18 06:10:10 AM UTC 24 Sep 18 06:11:05 AM UTC 24 24941522732 ps
T919 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3789753485 Sep 18 06:10:13 AM UTC 24 Sep 18 06:11:06 AM UTC 24 26967253923 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.327231827
Short name T8
Test name
Test status
Simulation time 5551616849 ps
CPU time 19.03 seconds
Started Sep 18 06:32:22 AM UTC 24
Finished Sep 18 06:32:42 AM UTC 24
Peak memory 221464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=327231827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
0.adc_ctrl_stress_all_with_rand_reset.327231827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3663094211
Short name T12
Test name
Test status
Simulation time 106938930534 ps
CPU time 36.4 seconds
Started Sep 18 06:32:46 AM UTC 24
Finished Sep 18 06:33:24 AM UTC 24
Peak memory 221352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3663094211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.adc_ctrl_stress_all_with_rand_reset.3663094211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.600727014
Short name T58
Test name
Test status
Simulation time 123598363324 ps
CPU time 493.56 seconds
Started Sep 18 06:32:46 AM UTC 24
Finished Sep 18 06:41:05 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600727014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.600727014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1155279543
Short name T17
Test name
Test status
Simulation time 350206065116 ps
CPU time 149.49 seconds
Started Sep 18 06:32:43 AM UTC 24
Finished Sep 18 06:35:15 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155279543 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.1155279543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.2593898149
Short name T145
Test name
Test status
Simulation time 510322296242 ps
CPU time 309.2 seconds
Started Sep 18 06:39:44 AM UTC 24
Finished Sep 18 06:44:57 AM UTC 24
Peak memory 210868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593898149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2593898149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1960262355
Short name T227
Test name
Test status
Simulation time 540304113538 ps
CPU time 770.3 seconds
Started Sep 18 06:32:21 AM UTC 24
Finished Sep 18 06:45:19 AM UTC 24
Peak memory 213496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960262355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1960262355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.1197597392
Short name T231
Test name
Test status
Simulation time 716132380409 ps
CPU time 492.11 seconds
Started Sep 18 06:43:30 AM UTC 24
Finished Sep 18 06:51:47 AM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197597392 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.1197597392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1241991076
Short name T141
Test name
Test status
Simulation time 330095926052 ps
CPU time 227.52 seconds
Started Sep 18 06:32:26 AM UTC 24
Finished Sep 18 06:36:16 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241991076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1241991076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.595187627
Short name T22
Test name
Test status
Simulation time 1295282763 ps
CPU time 6.19 seconds
Started Sep 18 06:46:42 AM UTC 24
Finished Sep 18 06:46:49 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=595187627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
12.adc_ctrl_stress_all_with_rand_reset.595187627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2101781502
Short name T155
Test name
Test status
Simulation time 531255263666 ps
CPU time 495.49 seconds
Started Sep 18 06:44:55 AM UTC 24
Finished Sep 18 06:53:16 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101781502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2101781502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3428260821
Short name T140
Test name
Test status
Simulation time 572258027170 ps
CPU time 414.99 seconds
Started Sep 18 06:32:28 AM UTC 24
Finished Sep 18 06:39:27 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428260821 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.3428260821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.1335722438
Short name T5
Test name
Test status
Simulation time 259938976323 ps
CPU time 306.24 seconds
Started Sep 18 06:33:47 AM UTC 24
Finished Sep 18 06:38:57 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335722438 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.1335722438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.939473860
Short name T77
Test name
Test status
Simulation time 979488677 ps
CPU time 3 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:12 AM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939473860 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.939473860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1828261983
Short name T247
Test name
Test status
Simulation time 558116320844 ps
CPU time 412 seconds
Started Sep 18 06:51:09 AM UTC 24
Finished Sep 18 06:58:06 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828261983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1828261983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2118321654
Short name T187
Test name
Test status
Simulation time 509490613166 ps
CPU time 340.37 seconds
Started Sep 18 06:41:06 AM UTC 24
Finished Sep 18 06:46:51 AM UTC 24
Peak memory 211052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118321654 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.2118321654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.36099642
Short name T19
Test name
Test status
Simulation time 7891037381 ps
CPU time 20.56 seconds
Started Sep 18 06:32:23 AM UTC 24
Finished Sep 18 06:32:45 AM UTC 24
Peak memory 242912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36099642 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.36099642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2622548252
Short name T105
Test name
Test status
Simulation time 514148252627 ps
CPU time 499.03 seconds
Started Sep 18 06:42:31 AM UTC 24
Finished Sep 18 06:50:57 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622548252 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.2622548252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3769853324
Short name T13
Test name
Test status
Simulation time 162688045355 ps
CPU time 90.16 seconds
Started Sep 18 06:32:37 AM UTC 24
Finished Sep 18 06:34:09 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769853324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.3769853324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.273933641
Short name T102
Test name
Test status
Simulation time 513947164929 ps
CPU time 995.59 seconds
Started Sep 18 06:34:09 AM UTC 24
Finished Sep 18 06:50:54 AM UTC 24
Peak memory 213492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273933641 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.273933641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.726036901
Short name T120
Test name
Test status
Simulation time 432433254 ps
CPU time 1.58 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:19 AM UTC 24
Peak memory 209556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726036901 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.726036901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3050862545
Short name T9
Test name
Test status
Simulation time 6288419693 ps
CPU time 12.05 seconds
Started Sep 18 06:32:30 AM UTC 24
Finished Sep 18 06:32:43 AM UTC 24
Peak memory 210900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3050862545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.adc_ctrl_stress_all_with_rand_reset.3050862545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1592695296
Short name T236
Test name
Test status
Simulation time 351739669496 ps
CPU time 611.96 seconds
Started Sep 18 06:33:06 AM UTC 24
Finished Sep 18 06:43:25 AM UTC 24
Peak memory 211012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592695296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1592695296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1113251725
Short name T233
Test name
Test status
Simulation time 371190375896 ps
CPU time 464.16 seconds
Started Sep 18 06:33:05 AM UTC 24
Finished Sep 18 06:40:54 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113251725 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.1113251725
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3522070097
Short name T144
Test name
Test status
Simulation time 343261735043 ps
CPU time 430.23 seconds
Started Sep 18 06:32:21 AM UTC 24
Finished Sep 18 06:39:36 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522070097 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.3522070097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2073464822
Short name T153
Test name
Test status
Simulation time 604105559233 ps
CPU time 274.24 seconds
Started Sep 18 06:33:03 AM UTC 24
Finished Sep 18 06:37:41 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073464822 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.2073464822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.3852455202
Short name T273
Test name
Test status
Simulation time 650523299817 ps
CPU time 1085.47 seconds
Started Sep 18 06:37:41 AM UTC 24
Finished Sep 18 06:55:57 AM UTC 24
Peak memory 213500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852455202 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.3852455202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1259129942
Short name T243
Test name
Test status
Simulation time 329130094563 ps
CPU time 144.7 seconds
Started Sep 18 06:50:13 AM UTC 24
Finished Sep 18 06:52:40 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259129942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1259129942
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3266422544
Short name T173
Test name
Test status
Simulation time 349116437583 ps
CPU time 477.3 seconds
Started Sep 18 06:46:09 AM UTC 24
Finished Sep 18 06:54:11 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266422544 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.3266422544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.4056717517
Short name T165
Test name
Test status
Simulation time 493239678989 ps
CPU time 99.89 seconds
Started Sep 18 06:53:16 AM UTC 24
Finished Sep 18 06:54:58 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056717517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4056717517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2090149175
Short name T205
Test name
Test status
Simulation time 488444705598 ps
CPU time 354.5 seconds
Started Sep 18 06:51:54 AM UTC 24
Finished Sep 18 06:57:53 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090149175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2090149175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.3318574864
Short name T290
Test name
Test status
Simulation time 573883307277 ps
CPU time 651.41 seconds
Started Sep 18 07:00:57 AM UTC 24
Finished Sep 18 07:11:55 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318574864 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.3318574864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.2206017200
Short name T255
Test name
Test status
Simulation time 405163120918 ps
CPU time 312.7 seconds
Started Sep 18 06:55:16 AM UTC 24
Finished Sep 18 07:00:33 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206017200 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.2206017200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.3612095827
Short name T280
Test name
Test status
Simulation time 548907309048 ps
CPU time 249.35 seconds
Started Sep 18 07:11:56 AM UTC 24
Finished Sep 18 07:16:08 AM UTC 24
Peak memory 210920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612095827 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.3612095827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1932512085
Short name T1
Test name
Test status
Simulation time 558605958 ps
CPU time 0.87 seconds
Started Sep 18 06:32:23 AM UTC 24
Finished Sep 18 06:32:25 AM UTC 24
Peak memory 209728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932512085 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1932512085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2181351685
Short name T338
Test name
Test status
Simulation time 8311382709 ps
CPU time 22.66 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:29 AM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181351685 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.2181351685
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.285163477
Short name T224
Test name
Test status
Simulation time 346748075946 ps
CPU time 840.62 seconds
Started Sep 18 06:35:32 AM UTC 24
Finished Sep 18 06:49:41 AM UTC 24
Peak memory 213364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285163477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.285163477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1545158252
Short name T159
Test name
Test status
Simulation time 378448607270 ps
CPU time 299.71 seconds
Started Sep 18 06:35:18 AM UTC 24
Finished Sep 18 06:40:22 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545158252 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.1545158252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.458192914
Short name T320
Test name
Test status
Simulation time 380366764823 ps
CPU time 1111.06 seconds
Started Sep 18 07:24:24 AM UTC 24
Finished Sep 18 07:43:07 AM UTC 24
Peak memory 213424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458192914 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.458192914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.4111425279
Short name T161
Test name
Test status
Simulation time 212759471879 ps
CPU time 533.08 seconds
Started Sep 18 06:34:19 AM UTC 24
Finished Sep 18 06:43:17 AM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111425279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4111425279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.2935416204
Short name T41
Test name
Test status
Simulation time 461913822703 ps
CPU time 993.97 seconds
Started Sep 18 06:32:30 AM UTC 24
Finished Sep 18 06:49:12 AM UTC 24
Peak memory 223996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935416204 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.2935416204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.3803844215
Short name T304
Test name
Test status
Simulation time 484830450755 ps
CPU time 362.69 seconds
Started Sep 18 07:11:21 AM UTC 24
Finished Sep 18 07:17:28 AM UTC 24
Peak memory 210808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803844215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3803844215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.3362864273
Short name T193
Test name
Test status
Simulation time 541654548581 ps
CPU time 388.01 seconds
Started Sep 18 07:21:25 AM UTC 24
Finished Sep 18 07:27:57 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362864273 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.3362864273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4238680581
Short name T73
Test name
Test status
Simulation time 37631471829 ps
CPU time 11.54 seconds
Started Sep 18 06:50:31 AM UTC 24
Finished Sep 18 06:50:43 AM UTC 24
Peak memory 221380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4238680581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.adc_ctrl_stress_all_with_rand_reset.4238680581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.4161581692
Short name T292
Test name
Test status
Simulation time 351443280936 ps
CPU time 822.65 seconds
Started Sep 18 07:29:35 AM UTC 24
Finished Sep 18 07:43:26 AM UTC 24
Peak memory 213360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161581692 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.4161581692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.696698470
Short name T225
Test name
Test status
Simulation time 333522036909 ps
CPU time 167.12 seconds
Started Sep 18 07:03:51 AM UTC 24
Finished Sep 18 07:06:41 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696698470 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.696698470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.829999864
Short name T252
Test name
Test status
Simulation time 164126345278 ps
CPU time 122.65 seconds
Started Sep 18 07:16:34 AM UTC 24
Finished Sep 18 07:18:39 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829999864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.829999864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1139391189
Short name T132
Test name
Test status
Simulation time 1083086013 ps
CPU time 3.17 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:09 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139391189 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.1139391189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.825462128
Short name T32
Test name
Test status
Simulation time 159867084745 ps
CPU time 238.63 seconds
Started Sep 18 06:32:44 AM UTC 24
Finished Sep 18 06:36:46 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825462128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.825462128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.3061805301
Short name T57
Test name
Test status
Simulation time 74463835641 ps
CPU time 393.15 seconds
Started Sep 18 06:33:19 AM UTC 24
Finished Sep 18 06:39:56 AM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061805301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3061805301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.4042303213
Short name T190
Test name
Test status
Simulation time 341226578305 ps
CPU time 292.23 seconds
Started Sep 18 07:08:06 AM UTC 24
Finished Sep 18 07:13:02 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042303213 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.4042303213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.4167688674
Short name T323
Test name
Test status
Simulation time 336272138401 ps
CPU time 826.31 seconds
Started Sep 18 07:10:30 AM UTC 24
Finished Sep 18 07:24:24 AM UTC 24
Peak memory 210876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167688674 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.4167688674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.1008146602
Short name T693
Test name
Test status
Simulation time 577282086333 ps
CPU time 1272.5 seconds
Started Sep 18 07:13:03 AM UTC 24
Finished Sep 18 07:34:28 AM UTC 24
Peak memory 213700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008146602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1008146602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.1969767277
Short name T266
Test name
Test status
Simulation time 331924866436 ps
CPU time 1021.94 seconds
Started Sep 18 07:18:29 AM UTC 24
Finished Sep 18 07:35:41 AM UTC 24
Peak memory 213344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969767277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1969767277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.3970438763
Short name T277
Test name
Test status
Simulation time 165377768965 ps
CPU time 550.89 seconds
Started Sep 18 07:32:33 AM UTC 24
Finished Sep 18 07:41:50 AM UTC 24
Peak memory 210880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970438763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3970438763
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.646195756
Short name T299
Test name
Test status
Simulation time 4260786589 ps
CPU time 4.88 seconds
Started Sep 18 07:14:37 AM UTC 24
Finished Sep 18 07:14:42 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=646195756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
30.adc_ctrl_stress_all_with_rand_reset.646195756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.3666468718
Short name T217
Test name
Test status
Simulation time 447233834107 ps
CPU time 1608.66 seconds
Started Sep 18 07:34:11 AM UTC 24
Finished Sep 18 08:01:16 AM UTC 24
Peak memory 225924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666468718 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.3666468718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.4103464115
Short name T237
Test name
Test status
Simulation time 344698765242 ps
CPU time 794.94 seconds
Started Sep 18 06:35:30 AM UTC 24
Finished Sep 18 06:48:52 AM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103464115 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.4103464115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.696954738
Short name T268
Test name
Test status
Simulation time 489586831579 ps
CPU time 1254.73 seconds
Started Sep 18 06:35:12 AM UTC 24
Finished Sep 18 06:56:19 AM UTC 24
Peak memory 213512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696954738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.696954738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.2247182071
Short name T208
Test name
Test status
Simulation time 99811668661 ps
CPU time 864.21 seconds
Started Sep 18 06:35:55 AM UTC 24
Finished Sep 18 06:50:29 AM UTC 24
Peak memory 213772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247182071 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.2247182071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3358891608
Short name T250
Test name
Test status
Simulation time 495528597535 ps
CPU time 1146.27 seconds
Started Sep 18 06:37:05 AM UTC 24
Finished Sep 18 06:56:22 AM UTC 24
Peak memory 213440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358891608 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.3358891608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.2915331575
Short name T170
Test name
Test status
Simulation time 363932306700 ps
CPU time 253.26 seconds
Started Sep 18 06:39:31 AM UTC 24
Finished Sep 18 06:43:48 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915331575 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.2915331575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2606744874
Short name T119
Test name
Test status
Simulation time 11721981566 ps
CPU time 10.81 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:17 AM UTC 24
Peak memory 211412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606744874 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.2606744874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2911343013
Short name T137
Test name
Test status
Simulation time 7480031282 ps
CPU time 11.57 seconds
Started Sep 18 06:43:26 AM UTC 24
Finished Sep 18 06:43:39 AM UTC 24
Peak memory 210624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2911343013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.adc_ctrl_stress_all_with_rand_reset.2911343013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.1695985663
Short name T284
Test name
Test status
Simulation time 406420382705 ps
CPU time 158.61 seconds
Started Sep 18 07:11:38 AM UTC 24
Finished Sep 18 07:14:19 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695985663 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.1695985663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.46851042
Short name T221
Test name
Test status
Simulation time 261973540074 ps
CPU time 864.36 seconds
Started Sep 18 07:14:38 AM UTC 24
Finished Sep 18 07:29:11 AM UTC 24
Peak memory 213636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46851042 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.46851042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1553395707
Short name T311
Test name
Test status
Simulation time 1875980569845 ps
CPU time 5632.11 seconds
Started Sep 18 07:41:55 AM UTC 24
Finished Sep 18 09:16:42 AM UTC 24
Peak memory 225988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553395707 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.1553395707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.501046149
Short name T39
Test name
Test status
Simulation time 3521669580 ps
CPU time 17.35 seconds
Started Sep 18 06:37:03 AM UTC 24
Finished Sep 18 06:37:22 AM UTC 24
Peak memory 221076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=501046149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.adc_ctrl_stress_all_with_rand_reset.501046149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1367754570
Short name T85
Test name
Test status
Simulation time 337739776935 ps
CPU time 200.94 seconds
Started Sep 18 06:32:20 AM UTC 24
Finished Sep 18 06:35:43 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367754570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1367754570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.3099854933
Short name T62
Test name
Test status
Simulation time 127035006550 ps
CPU time 570.37 seconds
Started Sep 18 06:32:21 AM UTC 24
Finished Sep 18 06:41:57 AM UTC 24
Peak memory 213804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099854933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3099854933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.2605165248
Short name T163
Test name
Test status
Simulation time 252622687442 ps
CPU time 518.12 seconds
Started Sep 18 06:32:22 AM UTC 24
Finished Sep 18 06:41:06 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605165248 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.2605165248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.3603922432
Short name T93
Test name
Test status
Simulation time 161918723223 ps
CPU time 214.66 seconds
Started Sep 18 06:53:07 AM UTC 24
Finished Sep 18 06:56:45 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603922432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3603922432
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.27768107
Short name T289
Test name
Test status
Simulation time 249266080684 ps
CPU time 961.73 seconds
Started Sep 18 06:56:20 AM UTC 24
Finished Sep 18 07:12:31 AM UTC 24
Peak memory 213760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27768107 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.27768107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3601123765
Short name T24
Test name
Test status
Simulation time 11785502458 ps
CPU time 25.97 seconds
Started Sep 18 07:04:37 AM UTC 24
Finished Sep 18 07:05:04 AM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3601123765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.adc_ctrl_stress_all_with_rand_reset.3601123765
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.3887694892
Short name T301
Test name
Test status
Simulation time 324708090464 ps
CPU time 795.26 seconds
Started Sep 18 07:14:48 AM UTC 24
Finished Sep 18 07:28:11 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887694892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3887694892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.850030674
Short name T286
Test name
Test status
Simulation time 327922080546 ps
CPU time 123.84 seconds
Started Sep 18 07:21:16 AM UTC 24
Finished Sep 18 07:23:22 AM UTC 24
Peak memory 210852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850030674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.850030674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.2683552349
Short name T265
Test name
Test status
Simulation time 332435022020 ps
CPU time 129.15 seconds
Started Sep 18 07:24:30 AM UTC 24
Finished Sep 18 07:26:41 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683552349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2683552349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3498013562
Short name T29
Test name
Test status
Simulation time 9021050900 ps
CPU time 5.34 seconds
Started Sep 18 07:27:18 AM UTC 24
Finished Sep 18 07:27:24 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3498013562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.adc_ctrl_stress_all_with_rand_reset.3498013562
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.2982567313
Short name T306
Test name
Test status
Simulation time 327563688924 ps
CPU time 198.01 seconds
Started Sep 18 07:31:11 AM UTC 24
Finished Sep 18 07:34:32 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982567313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2982567313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.308030568
Short name T308
Test name
Test status
Simulation time 521452607025 ps
CPU time 1388.76 seconds
Started Sep 18 07:31:13 AM UTC 24
Finished Sep 18 07:54:35 AM UTC 24
Peak memory 213280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308030568 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.308030568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.3799822653
Short name T272
Test name
Test status
Simulation time 494441571926 ps
CPU time 791.55 seconds
Started Sep 18 06:37:19 AM UTC 24
Finished Sep 18 06:50:39 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799822653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3799822653
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.924684861
Short name T74
Test name
Test status
Simulation time 683371406 ps
CPU time 2.52 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:09 AM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924684861 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.924684861
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3228532358
Short name T82
Test name
Test status
Simulation time 4093842374 ps
CPU time 10.96 seconds
Started Sep 18 06:10:35 AM UTC 24
Finished Sep 18 06:10:47 AM UTC 24
Peak memory 211440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228532358 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.3228532358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1185155308
Short name T6
Test name
Test status
Simulation time 30554359606 ps
CPU time 8.77 seconds
Started Sep 18 06:32:21 AM UTC 24
Finished Sep 18 06:32:31 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185155308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1185155308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1377660586
Short name T107
Test name
Test status
Simulation time 404944553805 ps
CPU time 1121.2 seconds
Started Sep 18 06:32:27 AM UTC 24
Finished Sep 18 06:51:19 AM UTC 24
Peak memory 213436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377660586 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.1377660586
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3744073577
Short name T108
Test name
Test status
Simulation time 100252992721 ps
CPU time 478.2 seconds
Started Sep 18 06:43:18 AM UTC 24
Finished Sep 18 06:51:21 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744073577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3744073577
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4090949108
Short name T258
Test name
Test status
Simulation time 79350756540 ps
CPU time 45.03 seconds
Started Sep 18 06:49:26 AM UTC 24
Finished Sep 18 06:50:12 AM UTC 24
Peak memory 221400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4090949108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.adc_ctrl_stress_all_with_rand_reset.4090949108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1660004818
Short name T177
Test name
Test status
Simulation time 373074502769 ps
CPU time 1197.23 seconds
Started Sep 18 06:52:28 AM UTC 24
Finished Sep 18 07:12:38 AM UTC 24
Peak memory 213444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660004818 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.1660004818
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.3396001614
Short name T251
Test name
Test status
Simulation time 377554599180 ps
CPU time 874.27 seconds
Started Sep 18 06:52:06 AM UTC 24
Finished Sep 18 07:06:49 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396001614 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.3396001614
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.4187799748
Short name T345
Test name
Test status
Simulation time 108687504239 ps
CPU time 562.33 seconds
Started Sep 18 06:57:22 AM UTC 24
Finished Sep 18 07:06:50 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187799748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4187799748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.3316458977
Short name T270
Test name
Test status
Simulation time 364968677209 ps
CPU time 1251.22 seconds
Started Sep 18 06:59:36 AM UTC 24
Finished Sep 18 07:20:39 AM UTC 24
Peak memory 213432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316458977 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.3316458977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.2720527473
Short name T274
Test name
Test status
Simulation time 504993723405 ps
CPU time 350.84 seconds
Started Sep 18 07:07:33 AM UTC 24
Finished Sep 18 07:13:28 AM UTC 24
Peak memory 210848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720527473 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.2720527473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.3215369465
Short name T215
Test name
Test status
Simulation time 112478326997 ps
CPU time 605.73 seconds
Started Sep 18 07:29:03 AM UTC 24
Finished Sep 18 07:39:15 AM UTC 24
Peak memory 211316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215369465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3215369465
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.2830018637
Short name T214
Test name
Test status
Simulation time 135132947278 ps
CPU time 667.09 seconds
Started Sep 18 07:32:40 AM UTC 24
Finished Sep 18 07:43:54 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830018637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2830018637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.3563209876
Short name T218
Test name
Test status
Simulation time 102235410884 ps
CPU time 422.7 seconds
Started Sep 18 07:38:21 AM UTC 24
Finished Sep 18 07:45:28 AM UTC 24
Peak memory 211404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563209876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3563209876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1196713385
Short name T129
Test name
Test status
Simulation time 705345719 ps
CPU time 1.29 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:07 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196713385 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.1196713385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.962504263
Short name T86
Test name
Test status
Simulation time 378571473 ps
CPU time 1.53 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:08 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=962504263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr
_mem_rw_with_rand_reset.962504263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1510910813
Short name T130
Test name
Test status
Simulation time 420714412 ps
CPU time 1.97 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:08 AM UTC 24
Peak memory 209848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510910813 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1510910813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.4288243346
Short name T804
Test name
Test status
Simulation time 324627870 ps
CPU time 0.89 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:07 AM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288243346 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4288243346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.775724227
Short name T69
Test name
Test status
Simulation time 4245209427 ps
CPU time 9.78 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:16 AM UTC 24
Peak memory 211504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775724227 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.775724227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2455928831
Short name T115
Test name
Test status
Simulation time 919261945 ps
CPU time 5.82 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:15 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455928831 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.2455928831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.32905781
Short name T917
Test name
Test status
Simulation time 26948031360 ps
CPU time 49.98 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:59 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32905781 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.32905781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1753266524
Short name T131
Test name
Test status
Simulation time 908551924 ps
CPU time 2.54 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:09 AM UTC 24
Peak memory 211008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753266524 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.1753266524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2708537187
Short name T81
Test name
Test status
Simulation time 606245176 ps
CPU time 1.76 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:11 AM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2708537187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cs
r_mem_rw_with_rand_reset.2708537187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3204227951
Short name T133
Test name
Test status
Simulation time 465171041 ps
CPU time 1.06 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:10 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204227951 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3204227951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2050064560
Short name T805
Test name
Test status
Simulation time 369986200 ps
CPU time 1.76 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:08 AM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050064560 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2050064560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4053283166
Short name T68
Test name
Test status
Simulation time 4434379243 ps
CPU time 6.44 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:15 AM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053283166 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.4053283166
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1856086318
Short name T75
Test name
Test status
Simulation time 726748259 ps
CPU time 3.28 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:10 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856086318 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1856086318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.415870527
Short name T70
Test name
Test status
Simulation time 8303998511 ps
CPU time 7.02 seconds
Started Sep 18 06:10:05 AM UTC 24
Finished Sep 18 06:10:13 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415870527 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.415870527
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3864178935
Short name T831
Test name
Test status
Simulation time 481845370 ps
CPU time 1.76 seconds
Started Sep 18 06:10:22 AM UTC 24
Finished Sep 18 06:10:25 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3864178935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c
sr_mem_rw_with_rand_reset.3864178935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2047786209
Short name T112
Test name
Test status
Simulation time 406206834 ps
CPU time 2.58 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:24 AM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047786209 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2047786209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2471735844
Short name T829
Test name
Test status
Simulation time 491421437 ps
CPU time 1.87 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:24 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471735844 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2471735844
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.201667275
Short name T848
Test name
Test status
Simulation time 4577896088 ps
CPU time 6.8 seconds
Started Sep 18 06:10:22 AM UTC 24
Finished Sep 18 06:10:30 AM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201667275 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.201667275
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2219938358
Short name T78
Test name
Test status
Simulation time 1654159704 ps
CPU time 2.62 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:24 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219938358 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2219938358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.898661028
Short name T836
Test name
Test status
Simulation time 4384983835 ps
CPU time 4.97 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:27 AM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898661028 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.898661028
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2867944123
Short name T841
Test name
Test status
Simulation time 522080405 ps
CPU time 2.51 seconds
Started Sep 18 06:10:24 AM UTC 24
Finished Sep 18 06:10:28 AM UTC 24
Peak memory 211264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2867944123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_c
sr_mem_rw_with_rand_reset.2867944123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2243419788
Short name T838
Test name
Test status
Simulation time 378460449 ps
CPU time 1.42 seconds
Started Sep 18 06:10:24 AM UTC 24
Finished Sep 18 06:10:27 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243419788 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2243419788
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.925345790
Short name T837
Test name
Test status
Simulation time 447907995 ps
CPU time 2.69 seconds
Started Sep 18 06:10:23 AM UTC 24
Finished Sep 18 06:10:27 AM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925345790 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.925345790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3161796312
Short name T849
Test name
Test status
Simulation time 2800348780 ps
CPU time 4.99 seconds
Started Sep 18 06:10:24 AM UTC 24
Finished Sep 18 06:10:31 AM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161796312 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.3161796312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.390785994
Short name T839
Test name
Test status
Simulation time 772818066 ps
CPU time 3.85 seconds
Started Sep 18 06:10:23 AM UTC 24
Finished Sep 18 06:10:28 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390785994 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.390785994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2314344972
Short name T877
Test name
Test status
Simulation time 8207914759 ps
CPU time 13.08 seconds
Started Sep 18 06:10:23 AM UTC 24
Finished Sep 18 06:10:37 AM UTC 24
Peak memory 211504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314344972 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.2314344972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4077285719
Short name T843
Test name
Test status
Simulation time 432422094 ps
CPU time 3.36 seconds
Started Sep 18 06:10:25 AM UTC 24
Finished Sep 18 06:10:29 AM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4077285719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c
sr_mem_rw_with_rand_reset.4077285719
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2026039169
Short name T121
Test name
Test status
Simulation time 522859344 ps
CPU time 1.67 seconds
Started Sep 18 06:10:24 AM UTC 24
Finished Sep 18 06:10:28 AM UTC 24
Peak memory 209596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026039169 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2026039169
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2037048538
Short name T840
Test name
Test status
Simulation time 345389866 ps
CPU time 2.18 seconds
Started Sep 18 06:10:24 AM UTC 24
Finished Sep 18 06:10:28 AM UTC 24
Peak memory 211092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037048538 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2037048538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2156849591
Short name T846
Test name
Test status
Simulation time 2760209585 ps
CPU time 3.72 seconds
Started Sep 18 06:10:25 AM UTC 24
Finished Sep 18 06:10:30 AM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156849591 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.2156849591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1455812345
Short name T845
Test name
Test status
Simulation time 490603190 ps
CPU time 3.59 seconds
Started Sep 18 06:10:24 AM UTC 24
Finished Sep 18 06:10:30 AM UTC 24
Peak memory 227644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455812345 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1455812345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3531563933
Short name T879
Test name
Test status
Simulation time 4020946514 ps
CPU time 11.39 seconds
Started Sep 18 06:10:24 AM UTC 24
Finished Sep 18 06:10:37 AM UTC 24
Peak memory 211464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531563933 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.3531563933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.845283150
Short name T850
Test name
Test status
Simulation time 407110072 ps
CPU time 2.43 seconds
Started Sep 18 06:10:27 AM UTC 24
Finished Sep 18 06:10:31 AM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=845283150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_cs
r_mem_rw_with_rand_reset.845283150
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.391685307
Short name T114
Test name
Test status
Simulation time 654160220 ps
CPU time 1.4 seconds
Started Sep 18 06:10:26 AM UTC 24
Finished Sep 18 06:10:29 AM UTC 24
Peak memory 209816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391685307 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.391685307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2839209050
Short name T842
Test name
Test status
Simulation time 392739960 ps
CPU time 1.66 seconds
Started Sep 18 06:10:26 AM UTC 24
Finished Sep 18 06:10:29 AM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839209050 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2839209050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1154592886
Short name T847
Test name
Test status
Simulation time 2328621131 ps
CPU time 2.33 seconds
Started Sep 18 06:10:26 AM UTC 24
Finished Sep 18 06:10:30 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154592886 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.1154592886
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1554734249
Short name T834
Test name
Test status
Simulation time 745467594 ps
CPU time 2.83 seconds
Started Sep 18 06:10:25 AM UTC 24
Finished Sep 18 06:10:29 AM UTC 24
Peak memory 211496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554734249 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1554734249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3087858281
Short name T339
Test name
Test status
Simulation time 9285669267 ps
CPU time 7.29 seconds
Started Sep 18 06:10:25 AM UTC 24
Finished Sep 18 06:10:33 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087858281 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.3087858281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1903128167
Short name T852
Test name
Test status
Simulation time 477433392 ps
CPU time 1.86 seconds
Started Sep 18 06:10:28 AM UTC 24
Finished Sep 18 06:10:31 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1903128167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_c
sr_mem_rw_with_rand_reset.1903128167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3740514560
Short name T122
Test name
Test status
Simulation time 599538513 ps
CPU time 1.93 seconds
Started Sep 18 06:10:28 AM UTC 24
Finished Sep 18 06:10:31 AM UTC 24
Peak memory 210020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740514560 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3740514560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2747250473
Short name T853
Test name
Test status
Simulation time 449375033 ps
CPU time 1.9 seconds
Started Sep 18 06:10:28 AM UTC 24
Finished Sep 18 06:10:31 AM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747250473 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2747250473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2521156507
Short name T865
Test name
Test status
Simulation time 5060129786 ps
CPU time 5.17 seconds
Started Sep 18 06:10:28 AM UTC 24
Finished Sep 18 06:10:35 AM UTC 24
Peak memory 211404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521156507 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.2521156507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3637645387
Short name T851
Test name
Test status
Simulation time 428756346 ps
CPU time 2.65 seconds
Started Sep 18 06:10:27 AM UTC 24
Finished Sep 18 06:10:31 AM UTC 24
Peak memory 211372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637645387 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3637645387
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1905287286
Short name T858
Test name
Test status
Simulation time 10685739578 ps
CPU time 4.28 seconds
Started Sep 18 06:10:27 AM UTC 24
Finished Sep 18 06:10:33 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905287286 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.1905287286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.257037111
Short name T854
Test name
Test status
Simulation time 420542961 ps
CPU time 1.29 seconds
Started Sep 18 06:10:30 AM UTC 24
Finished Sep 18 06:10:32 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=257037111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_cs
r_mem_rw_with_rand_reset.257037111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3237287352
Short name T124
Test name
Test status
Simulation time 531685939 ps
CPU time 2.93 seconds
Started Sep 18 06:10:29 AM UTC 24
Finished Sep 18 06:10:33 AM UTC 24
Peak memory 211196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237287352 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3237287352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.890903684
Short name T856
Test name
Test status
Simulation time 495953629 ps
CPU time 1.78 seconds
Started Sep 18 06:10:29 AM UTC 24
Finished Sep 18 06:10:32 AM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890903684 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.890903684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2415246898
Short name T857
Test name
Test status
Simulation time 2743556168 ps
CPU time 2.27 seconds
Started Sep 18 06:10:29 AM UTC 24
Finished Sep 18 06:10:33 AM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415246898 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.2415246898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4221716385
Short name T855
Test name
Test status
Simulation time 688766339 ps
CPU time 1.59 seconds
Started Sep 18 06:10:29 AM UTC 24
Finished Sep 18 06:10:32 AM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221716385 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4221716385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.246944775
Short name T915
Test name
Test status
Simulation time 8422171754 ps
CPU time 24.26 seconds
Started Sep 18 06:10:29 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246944775 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.246944775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1302947692
Short name T863
Test name
Test status
Simulation time 466588743 ps
CPU time 1.92 seconds
Started Sep 18 06:10:31 AM UTC 24
Finished Sep 18 06:10:34 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1302947692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_c
sr_mem_rw_with_rand_reset.1302947692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3885823113
Short name T862
Test name
Test status
Simulation time 343208355 ps
CPU time 1.87 seconds
Started Sep 18 06:10:31 AM UTC 24
Finished Sep 18 06:10:34 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885823113 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3885823113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.1705251271
Short name T859
Test name
Test status
Simulation time 495117468 ps
CPU time 1.85 seconds
Started Sep 18 06:10:31 AM UTC 24
Finished Sep 18 06:10:33 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705251271 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1705251271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.519442667
Short name T886
Test name
Test status
Simulation time 3869911399 ps
CPU time 6.38 seconds
Started Sep 18 06:10:31 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 211616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519442667 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.519442667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1521296332
Short name T866
Test name
Test status
Simulation time 513214234 ps
CPU time 3.2 seconds
Started Sep 18 06:10:31 AM UTC 24
Finished Sep 18 06:10:35 AM UTC 24
Peak memory 221356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521296332 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1521296332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2056748564
Short name T872
Test name
Test status
Simulation time 4067502792 ps
CPU time 4.22 seconds
Started Sep 18 06:10:31 AM UTC 24
Finished Sep 18 06:10:36 AM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056748564 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.2056748564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1187383295
Short name T868
Test name
Test status
Simulation time 590491836 ps
CPU time 2.21 seconds
Started Sep 18 06:10:32 AM UTC 24
Finished Sep 18 06:10:35 AM UTC 24
Peak memory 211264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1187383295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c
sr_mem_rw_with_rand_reset.1187383295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1441035486
Short name T125
Test name
Test status
Simulation time 525409977 ps
CPU time 3.11 seconds
Started Sep 18 06:10:32 AM UTC 24
Finished Sep 18 06:10:36 AM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441035486 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1441035486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1286511
Short name T864
Test name
Test status
Simulation time 503428939 ps
CPU time 1.14 seconds
Started Sep 18 06:10:32 AM UTC 24
Finished Sep 18 06:10:34 AM UTC 24
Peak memory 210392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_
base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1286511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.457748074
Short name T889
Test name
Test status
Simulation time 4752804914 ps
CPU time 5.49 seconds
Started Sep 18 06:10:32 AM UTC 24
Finished Sep 18 06:10:39 AM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457748074 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.457748074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2214198134
Short name T873
Test name
Test status
Simulation time 1131138043 ps
CPU time 4.03 seconds
Started Sep 18 06:10:31 AM UTC 24
Finished Sep 18 06:10:36 AM UTC 24
Peak memory 227588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214198134 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2214198134
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3347427706
Short name T875
Test name
Test status
Simulation time 4191938266 ps
CPU time 4.01 seconds
Started Sep 18 06:10:32 AM UTC 24
Finished Sep 18 06:10:37 AM UTC 24
Peak memory 211640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347427706 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.3347427706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1268759042
Short name T869
Test name
Test status
Simulation time 766624866 ps
CPU time 1.02 seconds
Started Sep 18 06:10:33 AM UTC 24
Finished Sep 18 06:10:35 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1268759042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c
sr_mem_rw_with_rand_reset.1268759042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1600337365
Short name T123
Test name
Test status
Simulation time 374792184 ps
CPU time 1.68 seconds
Started Sep 18 06:10:33 AM UTC 24
Finished Sep 18 06:10:36 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600337365 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1600337365
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.3261238805
Short name T870
Test name
Test status
Simulation time 495634218 ps
CPU time 1.44 seconds
Started Sep 18 06:10:33 AM UTC 24
Finished Sep 18 06:10:36 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261238805 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3261238805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2032020612
Short name T914
Test name
Test status
Simulation time 4701175922 ps
CPU time 19.36 seconds
Started Sep 18 06:10:33 AM UTC 24
Finished Sep 18 06:10:54 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032020612 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.2032020612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.877443356
Short name T867
Test name
Test status
Simulation time 546687518 ps
CPU time 1.94 seconds
Started Sep 18 06:10:32 AM UTC 24
Finished Sep 18 06:10:35 AM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877443356 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.877443356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1206414744
Short name T916
Test name
Test status
Simulation time 8184438375 ps
CPU time 21.68 seconds
Started Sep 18 06:10:33 AM UTC 24
Finished Sep 18 06:10:56 AM UTC 24
Peak memory 211204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206414744 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.1206414744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.572373286
Short name T880
Test name
Test status
Simulation time 576007184 ps
CPU time 2 seconds
Started Sep 18 06:10:35 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 220432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=572373286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_cs
r_mem_rw_with_rand_reset.572373286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3859396659
Short name T876
Test name
Test status
Simulation time 448241436 ps
CPU time 1.48 seconds
Started Sep 18 06:10:35 AM UTC 24
Finished Sep 18 06:10:37 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859396659 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3859396659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2604694810
Short name T874
Test name
Test status
Simulation time 530078775 ps
CPU time 1.25 seconds
Started Sep 18 06:10:35 AM UTC 24
Finished Sep 18 06:10:37 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604694810 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2604694810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.872962974
Short name T896
Test name
Test status
Simulation time 2309339299 ps
CPU time 3.99 seconds
Started Sep 18 06:10:35 AM UTC 24
Finished Sep 18 06:10:40 AM UTC 24
Peak memory 211464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872962974 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.872962974
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3207472550
Short name T882
Test name
Test status
Simulation time 661924153 ps
CPU time 2.29 seconds
Started Sep 18 06:10:35 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207472550 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3207472550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2011868505
Short name T135
Test name
Test status
Simulation time 1285496550 ps
CPU time 3.17 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:13 AM UTC 24
Peak memory 211344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011868505 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.2011868505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3823956955
Short name T913
Test name
Test status
Simulation time 53303018130 ps
CPU time 36.51 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823956955 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.3823956955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1594606551
Short name T113
Test name
Test status
Simulation time 1088726381 ps
CPU time 4.37 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:13 AM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594606551 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.1594606551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2198825403
Short name T87
Test name
Test status
Simulation time 410499189 ps
CPU time 1.71 seconds
Started Sep 18 06:10:08 AM UTC 24
Finished Sep 18 06:10:11 AM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2198825403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs
r_mem_rw_with_rand_reset.2198825403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3785369775
Short name T134
Test name
Test status
Simulation time 399919091 ps
CPU time 1.55 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:10 AM UTC 24
Peak memory 209852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785369775 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3785369775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.71162938
Short name T806
Test name
Test status
Simulation time 395601981 ps
CPU time 1.18 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:10 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71162938 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.71162938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4057336014
Short name T128
Test name
Test status
Simulation time 4014494792 ps
CPU time 8.62 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:18 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057336014 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.4057336014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3320899943
Short name T71
Test name
Test status
Simulation time 4442139309 ps
CPU time 5.25 seconds
Started Sep 18 06:10:07 AM UTC 24
Finished Sep 18 06:10:14 AM UTC 24
Peak memory 211684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320899943 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.3320899943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2079403252
Short name T881
Test name
Test status
Simulation time 530402460 ps
CPU time 2.07 seconds
Started Sep 18 06:10:35 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079403252 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2079403252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.335886399
Short name T884
Test name
Test status
Simulation time 594965193 ps
CPU time 1.14 seconds
Started Sep 18 06:10:36 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335886399 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.335886399
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.1000775811
Short name T885
Test name
Test status
Simulation time 475531902 ps
CPU time 1.34 seconds
Started Sep 18 06:10:36 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000775811 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1000775811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1039849783
Short name T888
Test name
Test status
Simulation time 290933883 ps
CPU time 1.56 seconds
Started Sep 18 06:10:36 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039849783 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1039849783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.730289000
Short name T883
Test name
Test status
Simulation time 478760082 ps
CPU time 1.03 seconds
Started Sep 18 06:10:36 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730289000 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.730289000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1239280097
Short name T887
Test name
Test status
Simulation time 389209757 ps
CPU time 1.27 seconds
Started Sep 18 06:10:36 AM UTC 24
Finished Sep 18 06:10:38 AM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239280097 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1239280097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.917606903
Short name T891
Test name
Test status
Simulation time 441227566 ps
CPU time 1.19 seconds
Started Sep 18 06:10:37 AM UTC 24
Finished Sep 18 06:10:39 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917606903 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.917606903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.1329826096
Short name T893
Test name
Test status
Simulation time 420344986 ps
CPU time 1.33 seconds
Started Sep 18 06:10:37 AM UTC 24
Finished Sep 18 06:10:39 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329826096 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1329826096
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1542379075
Short name T895
Test name
Test status
Simulation time 323500426 ps
CPU time 1.52 seconds
Started Sep 18 06:10:37 AM UTC 24
Finished Sep 18 06:10:40 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542379075 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1542379075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2190515600
Short name T894
Test name
Test status
Simulation time 525792732 ps
CPU time 1.31 seconds
Started Sep 18 06:10:37 AM UTC 24
Finished Sep 18 06:10:40 AM UTC 24
Peak memory 209848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190515600 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2190515600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1040591034
Short name T809
Test name
Test status
Simulation time 1346563585 ps
CPU time 3.56 seconds
Started Sep 18 06:10:10 AM UTC 24
Finished Sep 18 06:10:15 AM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040591034 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.1040591034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4165646928
Short name T918
Test name
Test status
Simulation time 24941522732 ps
CPU time 53.4 seconds
Started Sep 18 06:10:10 AM UTC 24
Finished Sep 18 06:11:05 AM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165646928 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.4165646928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2725540583
Short name T136
Test name
Test status
Simulation time 951503269 ps
CPU time 2.18 seconds
Started Sep 18 06:10:10 AM UTC 24
Finished Sep 18 06:10:13 AM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725540583 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.2725540583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3612883893
Short name T88
Test name
Test status
Simulation time 496474671 ps
CPU time 2.36 seconds
Started Sep 18 06:10:11 AM UTC 24
Finished Sep 18 06:10:15 AM UTC 24
Peak memory 211404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3612883893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cs
r_mem_rw_with_rand_reset.3612883893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3663360327
Short name T66
Test name
Test status
Simulation time 370859259 ps
CPU time 2.39 seconds
Started Sep 18 06:10:10 AM UTC 24
Finished Sep 18 06:10:14 AM UTC 24
Peak memory 211184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663360327 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3663360327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.946850235
Short name T807
Test name
Test status
Simulation time 476161430 ps
CPU time 1.28 seconds
Started Sep 18 06:10:09 AM UTC 24
Finished Sep 18 06:10:11 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946850235 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.946850235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3963411584
Short name T67
Test name
Test status
Simulation time 2474544269 ps
CPU time 2.87 seconds
Started Sep 18 06:10:11 AM UTC 24
Finished Sep 18 06:10:15 AM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963411584 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.3963411584
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3885625297
Short name T80
Test name
Test status
Simulation time 548324285 ps
CPU time 2.7 seconds
Started Sep 18 06:10:09 AM UTC 24
Finished Sep 18 06:10:13 AM UTC 24
Peak memory 211504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885625297 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3885625297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3929193987
Short name T72
Test name
Test status
Simulation time 4064731555 ps
CPU time 12.24 seconds
Started Sep 18 06:10:09 AM UTC 24
Finished Sep 18 06:10:22 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929193987 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.3929193987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.2273795852
Short name T892
Test name
Test status
Simulation time 421649029 ps
CPU time 1.02 seconds
Started Sep 18 06:10:37 AM UTC 24
Finished Sep 18 06:10:39 AM UTC 24
Peak memory 210228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273795852 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2273795852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1109636321
Short name T890
Test name
Test status
Simulation time 547679878 ps
CPU time 0.95 seconds
Started Sep 18 06:10:37 AM UTC 24
Finished Sep 18 06:10:39 AM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109636321 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1109636321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.722649411
Short name T899
Test name
Test status
Simulation time 509113703 ps
CPU time 2.26 seconds
Started Sep 18 06:10:37 AM UTC 24
Finished Sep 18 06:10:41 AM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722649411 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.722649411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.316216517
Short name T903
Test name
Test status
Simulation time 483500894 ps
CPU time 1.81 seconds
Started Sep 18 06:10:38 AM UTC 24
Finished Sep 18 06:10:41 AM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316216517 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.316216517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.1199940537
Short name T905
Test name
Test status
Simulation time 395587878 ps
CPU time 2.02 seconds
Started Sep 18 06:10:38 AM UTC 24
Finished Sep 18 06:10:41 AM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199940537 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1199940537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.3880703294
Short name T898
Test name
Test status
Simulation time 512114188 ps
CPU time 0.81 seconds
Started Sep 18 06:10:38 AM UTC 24
Finished Sep 18 06:10:40 AM UTC 24
Peak memory 210272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880703294 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3880703294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.3543736927
Short name T902
Test name
Test status
Simulation time 463836959 ps
CPU time 1.34 seconds
Started Sep 18 06:10:39 AM UTC 24
Finished Sep 18 06:10:41 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543736927 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3543736927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.25628041
Short name T906
Test name
Test status
Simulation time 477061268 ps
CPU time 2.06 seconds
Started Sep 18 06:10:39 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25628041 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.25628041
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.730143073
Short name T901
Test name
Test status
Simulation time 555932370 ps
CPU time 1.23 seconds
Started Sep 18 06:10:39 AM UTC 24
Finished Sep 18 06:10:41 AM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730143073 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.730143073
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3462795191
Short name T904
Test name
Test status
Simulation time 315206279 ps
CPU time 1.83 seconds
Started Sep 18 06:10:39 AM UTC 24
Finished Sep 18 06:10:41 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462795191 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3462795191
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.466712819
Short name T118
Test name
Test status
Simulation time 365931763 ps
CPU time 2.78 seconds
Started Sep 18 06:10:13 AM UTC 24
Finished Sep 18 06:10:17 AM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466712819 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.466712819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3789753485
Short name T919
Test name
Test status
Simulation time 26967253923 ps
CPU time 51.01 seconds
Started Sep 18 06:10:13 AM UTC 24
Finished Sep 18 06:11:06 AM UTC 24
Peak memory 211412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789753485 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.3789753485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3605256598
Short name T117
Test name
Test status
Simulation time 1105581383 ps
CPU time 2.41 seconds
Started Sep 18 06:10:13 AM UTC 24
Finished Sep 18 06:10:16 AM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605256598 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.3605256598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3062822897
Short name T811
Test name
Test status
Simulation time 432951418 ps
CPU time 2.24 seconds
Started Sep 18 06:10:14 AM UTC 24
Finished Sep 18 06:10:17 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3062822897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cs
r_mem_rw_with_rand_reset.3062822897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3719179468
Short name T116
Test name
Test status
Simulation time 537537222 ps
CPU time 1.49 seconds
Started Sep 18 06:10:13 AM UTC 24
Finished Sep 18 06:10:15 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719179468 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3719179468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1550841101
Short name T808
Test name
Test status
Simulation time 430211191 ps
CPU time 1.92 seconds
Started Sep 18 06:10:11 AM UTC 24
Finished Sep 18 06:10:14 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550841101 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1550841101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3054956067
Short name T127
Test name
Test status
Simulation time 4351512136 ps
CPU time 3.76 seconds
Started Sep 18 06:10:13 AM UTC 24
Finished Sep 18 06:10:18 AM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054956067 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.3054956067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2117186944
Short name T89
Test name
Test status
Simulation time 557271987 ps
CPU time 2.67 seconds
Started Sep 18 06:10:11 AM UTC 24
Finished Sep 18 06:10:15 AM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117186944 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2117186944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3124389479
Short name T340
Test name
Test status
Simulation time 8236582341 ps
CPU time 21.74 seconds
Started Sep 18 06:10:11 AM UTC 24
Finished Sep 18 06:10:34 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124389479 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.3124389479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.3269308757
Short name T900
Test name
Test status
Simulation time 528485807 ps
CPU time 1.09 seconds
Started Sep 18 06:10:39 AM UTC 24
Finished Sep 18 06:10:41 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269308757 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3269308757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.605819254
Short name T909
Test name
Test status
Simulation time 525652388 ps
CPU time 2.13 seconds
Started Sep 18 06:10:39 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 211160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605819254 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.605819254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.73375197
Short name T908
Test name
Test status
Simulation time 343809179 ps
CPU time 1.05 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73375197 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.73375197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.4026724936
Short name T907
Test name
Test status
Simulation time 514835185 ps
CPU time 0.97 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026724936 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4026724936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.1987206640
Short name T911
Test name
Test status
Simulation time 483184723 ps
CPU time 1.17 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987206640 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1987206640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.4263407669
Short name T861
Test name
Test status
Simulation time 498707932 ps
CPU time 1.85 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:43 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263407669 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.4263407669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.3090911677
Short name T910
Test name
Test status
Simulation time 495381316 ps
CPU time 1.04 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090911677 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3090911677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1250372162
Short name T878
Test name
Test status
Simulation time 416497374 ps
CPU time 2.27 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:43 AM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250372162 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1250372162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.3801650437
Short name T860
Test name
Test status
Simulation time 330219806 ps
CPU time 0.99 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801650437 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3801650437
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.480730951
Short name T912
Test name
Test status
Simulation time 355563180 ps
CPU time 0.95 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480730951 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.480730951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.300787964
Short name T812
Test name
Test status
Simulation time 593388250 ps
CPU time 1.49 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:18 AM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=300787964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr
_mem_rw_with_rand_reset.300787964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1614958472
Short name T126
Test name
Test status
Simulation time 366414198 ps
CPU time 1.88 seconds
Started Sep 18 06:10:14 AM UTC 24
Finished Sep 18 06:10:17 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614958472 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1614958472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.173079279
Short name T810
Test name
Test status
Simulation time 541419493 ps
CPU time 1.47 seconds
Started Sep 18 06:10:14 AM UTC 24
Finished Sep 18 06:10:17 AM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173079279 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.173079279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2450837652
Short name T826
Test name
Test status
Simulation time 2265164093 ps
CPU time 6.26 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:23 AM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450837652 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.2450837652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3988336440
Short name T79
Test name
Test status
Simulation time 833457722 ps
CPU time 3.55 seconds
Started Sep 18 06:10:14 AM UTC 24
Finished Sep 18 06:10:19 AM UTC 24
Peak memory 221424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988336440 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3988336440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1666623654
Short name T337
Test name
Test status
Simulation time 8743447027 ps
CPU time 7.53 seconds
Started Sep 18 06:10:14 AM UTC 24
Finished Sep 18 06:10:23 AM UTC 24
Peak memory 211504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666623654 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.1666623654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.135952083
Short name T815
Test name
Test status
Simulation time 448244626 ps
CPU time 2.21 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:19 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=135952083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr
_mem_rw_with_rand_reset.135952083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.2659704481
Short name T813
Test name
Test status
Simulation time 443376672 ps
CPU time 1.91 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:19 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659704481 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2659704481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.989063287
Short name T823
Test name
Test status
Simulation time 4108251494 ps
CPU time 4.93 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:22 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989063287 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.989063287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3017663895
Short name T819
Test name
Test status
Simulation time 1854375526 ps
CPU time 3.29 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:20 AM UTC 24
Peak memory 227396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017663895 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3017663895
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2544443802
Short name T832
Test name
Test status
Simulation time 8024552206 ps
CPU time 8.57 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:26 AM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544443802 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.2544443802
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2400405515
Short name T818
Test name
Test status
Simulation time 431848897 ps
CPU time 1.42 seconds
Started Sep 18 06:10:17 AM UTC 24
Finished Sep 18 06:10:20 AM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2400405515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_cs
r_mem_rw_with_rand_reset.2400405515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1502178981
Short name T817
Test name
Test status
Simulation time 396743298 ps
CPU time 1.32 seconds
Started Sep 18 06:10:17 AM UTC 24
Finished Sep 18 06:10:20 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502178981 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1502178981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.964482483
Short name T814
Test name
Test status
Simulation time 366854652 ps
CPU time 1.04 seconds
Started Sep 18 06:10:17 AM UTC 24
Finished Sep 18 06:10:19 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964482483 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.964482483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2580621707
Short name T871
Test name
Test status
Simulation time 4910417533 ps
CPU time 17.43 seconds
Started Sep 18 06:10:17 AM UTC 24
Finished Sep 18 06:10:36 AM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580621707 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.2580621707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1962015240
Short name T816
Test name
Test status
Simulation time 535961651 ps
CPU time 2.42 seconds
Started Sep 18 06:10:16 AM UTC 24
Finished Sep 18 06:10:19 AM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962015240 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1962015240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2092973076
Short name T76
Test name
Test status
Simulation time 8382256306 ps
CPU time 4.83 seconds
Started Sep 18 06:10:17 AM UTC 24
Finished Sep 18 06:10:23 AM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092973076 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.2092973076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3557653511
Short name T827
Test name
Test status
Simulation time 583309872 ps
CPU time 2.06 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:23 AM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3557653511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs
r_mem_rw_with_rand_reset.3557653511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1673602254
Short name T820
Test name
Test status
Simulation time 364420122 ps
CPU time 1.53 seconds
Started Sep 18 06:10:19 AM UTC 24
Finished Sep 18 06:10:21 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673602254 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1673602254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.3303762336
Short name T821
Test name
Test status
Simulation time 359385157 ps
CPU time 1.78 seconds
Started Sep 18 06:10:18 AM UTC 24
Finished Sep 18 06:10:21 AM UTC 24
Peak memory 209728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303762336 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3303762336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2701268348
Short name T844
Test name
Test status
Simulation time 2176415440 ps
CPU time 9.65 seconds
Started Sep 18 06:10:19 AM UTC 24
Finished Sep 18 06:10:29 AM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701268348 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.2701268348
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2822053209
Short name T822
Test name
Test status
Simulation time 557913286 ps
CPU time 2.05 seconds
Started Sep 18 06:10:18 AM UTC 24
Finished Sep 18 06:10:22 AM UTC 24
Peak memory 211388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822053209 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2822053209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.336412744
Short name T835
Test name
Test status
Simulation time 4493074523 ps
CPU time 6.72 seconds
Started Sep 18 06:10:18 AM UTC 24
Finished Sep 18 06:10:26 AM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336412744 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.336412744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3285896874
Short name T830
Test name
Test status
Simulation time 376291130 ps
CPU time 2.25 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:24 AM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3285896874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs
r_mem_rw_with_rand_reset.3285896874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2390222587
Short name T825
Test name
Test status
Simulation time 516235303 ps
CPU time 1.73 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:23 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390222587 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2390222587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.423082018
Short name T824
Test name
Test status
Simulation time 477894964 ps
CPU time 1.25 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:23 AM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423082018 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.423082018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2298105445
Short name T833
Test name
Test status
Simulation time 3251634336 ps
CPU time 4.86 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:26 AM UTC 24
Peak memory 211488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298105445 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.2298105445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.351787180
Short name T828
Test name
Test status
Simulation time 515714530 ps
CPU time 2.13 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:23 AM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351787180 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.351787180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2431009078
Short name T897
Test name
Test status
Simulation time 8423663661 ps
CPU time 23.13 seconds
Started Sep 18 06:10:20 AM UTC 24
Finished Sep 18 06:10:45 AM UTC 24
Peak memory 211512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431009078 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.2431009078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.3663133205
Short name T99
Test name
Test status
Simulation time 497009975173 ps
CPU time 1487.27 seconds
Started Sep 18 06:32:20 AM UTC 24
Finished Sep 18 06:57:22 AM UTC 24
Peak memory 213372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663133205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3663133205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2302204914
Short name T363
Test name
Test status
Simulation time 162285236417 ps
CPU time 556.13 seconds
Started Sep 18 06:32:20 AM UTC 24
Finished Sep 18 06:41:42 AM UTC 24
Peak memory 213372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302204914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.2302204914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.59111238
Short name T47
Test name
Test status
Simulation time 324390419337 ps
CPU time 195.66 seconds
Started Sep 18 06:32:20 AM UTC 24
Finished Sep 18 06:35:38 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59111238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.59111238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3423694
Short name T172
Test name
Test status
Simulation time 355250592162 ps
CPU time 1053.98 seconds
Started Sep 18 06:32:20 AM UTC 24
Finished Sep 18 06:50:04 AM UTC 24
Peak memory 213448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423694 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.3423694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2325871910
Short name T400
Test name
Test status
Simulation time 414145279133 ps
CPU time 1194.79 seconds
Started Sep 18 06:32:21 AM UTC 24
Finished Sep 18 06:52:28 AM UTC 24
Peak memory 213284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325871910 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.2325871910
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.3210186605
Short name T4
Test name
Test status
Simulation time 5292993279 ps
CPU time 7.16 seconds
Started Sep 18 06:32:21 AM UTC 24
Finished Sep 18 06:32:29 AM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210186605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3210186605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.715901615
Short name T2
Test name
Test status
Simulation time 5782569260 ps
CPU time 6.76 seconds
Started Sep 18 06:32:20 AM UTC 24
Finished Sep 18 06:32:27 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715901615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.715901615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.4020145696
Short name T18
Test name
Test status
Simulation time 325003924 ps
CPU time 2.27 seconds
Started Sep 18 06:32:31 AM UTC 24
Finished Sep 18 06:32:34 AM UTC 24
Peak memory 210640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020145696 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4020145696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1708343308
Short name T171
Test name
Test status
Simulation time 485834504906 ps
CPU time 870.47 seconds
Started Sep 18 06:32:28 AM UTC 24
Finished Sep 18 06:47:08 AM UTC 24
Peak memory 213692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708343308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1708343308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2339869879
Short name T201
Test name
Test status
Simulation time 167491282689 ps
CPU time 397.72 seconds
Started Sep 18 06:32:26 AM UTC 24
Finished Sep 18 06:39:08 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339869879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.2339869879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.2117841403
Short name T11
Test name
Test status
Simulation time 162880653893 ps
CPU time 23.39 seconds
Started Sep 18 06:32:25 AM UTC 24
Finished Sep 18 06:32:49 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117841403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2117841403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.888984326
Short name T14
Test name
Test status
Simulation time 160173440977 ps
CPU time 111.71 seconds
Started Sep 18 06:32:25 AM UTC 24
Finished Sep 18 06:34:18 AM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888984326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.888984326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2610319597
Short name T139
Test name
Test status
Simulation time 622228753126 ps
CPU time 304.9 seconds
Started Sep 18 06:32:26 AM UTC 24
Finished Sep 18 06:37:34 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610319597 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.2610319597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.3617388351
Short name T213
Test name
Test status
Simulation time 110302717194 ps
CPU time 595.17 seconds
Started Sep 18 06:32:29 AM UTC 24
Finished Sep 18 06:42:31 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617388351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3617388351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.3294104068
Short name T60
Test name
Test status
Simulation time 21107318652 ps
CPU time 43.38 seconds
Started Sep 18 06:32:29 AM UTC 24
Finished Sep 18 06:33:14 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294104068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3294104068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.265222761
Short name T7
Test name
Test status
Simulation time 4807409226 ps
CPU time 5.69 seconds
Started Sep 18 06:32:29 AM UTC 24
Finished Sep 18 06:32:36 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265222761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.265222761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.4252767372
Short name T20
Test name
Test status
Simulation time 8457235261 ps
CPU time 15.42 seconds
Started Sep 18 06:32:30 AM UTC 24
Finished Sep 18 06:32:46 AM UTC 24
Peak memory 242840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252767372 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4252767372
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1293042386
Short name T3
Test name
Test status
Simulation time 5754010948 ps
CPU time 2.29 seconds
Started Sep 18 06:32:25 AM UTC 24
Finished Sep 18 06:32:28 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293042386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1293042386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.3975691769
Short name T370
Test name
Test status
Simulation time 484574258 ps
CPU time 1.36 seconds
Started Sep 18 06:43:38 AM UTC 24
Finished Sep 18 06:43:40 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975691769 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3975691769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.3568101111
Short name T253
Test name
Test status
Simulation time 165993964150 ps
CPU time 399.01 seconds
Started Sep 18 06:42:41 AM UTC 24
Finished Sep 18 06:49:25 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568101111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3568101111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.1315279984
Short name T168
Test name
Test status
Simulation time 484127132013 ps
CPU time 332.81 seconds
Started Sep 18 06:42:09 AM UTC 24
Finished Sep 18 06:47:46 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315279984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1315279984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1616965523
Short name T92
Test name
Test status
Simulation time 324405157704 ps
CPU time 863.11 seconds
Started Sep 18 06:42:10 AM UTC 24
Finished Sep 18 06:56:42 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616965523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.1616965523
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.696466493
Short name T174
Test name
Test status
Simulation time 490608036492 ps
CPU time 1171.22 seconds
Started Sep 18 06:41:44 AM UTC 24
Finished Sep 18 07:01:26 AM UTC 24
Peak memory 213372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696466493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.696466493
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.2139943920
Short name T419
Test name
Test status
Simulation time 327094500115 ps
CPU time 825.63 seconds
Started Sep 18 06:41:58 AM UTC 24
Finished Sep 18 06:55:52 AM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139943920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.2139943920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2565473226
Short name T183
Test name
Test status
Simulation time 185623816253 ps
CPU time 133.64 seconds
Started Sep 18 06:42:15 AM UTC 24
Finished Sep 18 06:44:31 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565473226 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.2565473226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2441868659
Short name T180
Test name
Test status
Simulation time 192791398553 ps
CPU time 92.66 seconds
Started Sep 18 06:42:19 AM UTC 24
Finished Sep 18 06:43:54 AM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441868659 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.2441868659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.625695209
Short name T186
Test name
Test status
Simulation time 28104605511 ps
CPU time 109.71 seconds
Started Sep 18 06:43:06 AM UTC 24
Finished Sep 18 06:44:57 AM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625695209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.625695209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.4068700174
Short name T367
Test name
Test status
Simulation time 4262952042 ps
CPU time 17.35 seconds
Started Sep 18 06:42:47 AM UTC 24
Finished Sep 18 06:43:05 AM UTC 24
Peak memory 210640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068700174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4068700174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.4228245241
Short name T365
Test name
Test status
Simulation time 5823386197 ps
CPU time 23.86 seconds
Started Sep 18 06:41:43 AM UTC 24
Finished Sep 18 06:42:08 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228245241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.4228245241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.4254302070
Short name T372
Test name
Test status
Simulation time 353814445 ps
CPU time 1.08 seconds
Started Sep 18 06:45:25 AM UTC 24
Finished Sep 18 06:45:27 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254302070 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4254302070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.16445303
Short name T158
Test name
Test status
Simulation time 529862111311 ps
CPU time 1183.03 seconds
Started Sep 18 06:44:32 AM UTC 24
Finished Sep 18 07:04:27 AM UTC 24
Peak memory 213600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16445303 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.16445303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.574413248
Short name T242
Test name
Test status
Simulation time 330993129806 ps
CPU time 382.9 seconds
Started Sep 18 06:43:53 AM UTC 24
Finished Sep 18 06:50:20 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574413248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.574413248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1877786352
Short name T392
Test name
Test status
Simulation time 163443504395 ps
CPU time 391.65 seconds
Started Sep 18 06:43:54 AM UTC 24
Finished Sep 18 06:50:30 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877786352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.1877786352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.4128161528
Short name T147
Test name
Test status
Simulation time 330457337280 ps
CPU time 140.99 seconds
Started Sep 18 06:43:41 AM UTC 24
Finished Sep 18 06:46:04 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128161528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4128161528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.1136760564
Short name T109
Test name
Test status
Simulation time 167529979437 ps
CPU time 452.34 seconds
Started Sep 18 06:43:49 AM UTC 24
Finished Sep 18 06:51:27 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136760564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.1136760564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.907783932
Short name T203
Test name
Test status
Simulation time 539805266082 ps
CPU time 312.46 seconds
Started Sep 18 06:44:15 AM UTC 24
Finished Sep 18 06:49:32 AM UTC 24
Peak memory 210848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907783932 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.907783932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1197304933
Short name T408
Test name
Test status
Simulation time 204297990618 ps
CPU time 575.89 seconds
Started Sep 18 06:44:19 AM UTC 24
Finished Sep 18 06:54:00 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197304933 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.1197304933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.203042501
Short name T223
Test name
Test status
Simulation time 120205779991 ps
CPU time 796.74 seconds
Started Sep 18 06:44:58 AM UTC 24
Finished Sep 18 06:58:23 AM UTC 24
Peak memory 211248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203042501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.203042501
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.669030814
Short name T376
Test name
Test status
Simulation time 43393989394 ps
CPU time 68.07 seconds
Started Sep 18 06:44:58 AM UTC 24
Finished Sep 18 06:46:07 AM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669030814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.669030814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.3535082035
Short name T371
Test name
Test status
Simulation time 3715614362 ps
CPU time 2.82 seconds
Started Sep 18 06:44:55 AM UTC 24
Finished Sep 18 06:44:59 AM UTC 24
Peak memory 210552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535082035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3535082035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.3115096539
Short name T179
Test name
Test status
Simulation time 5753116746 ps
CPU time 12.01 seconds
Started Sep 18 06:43:39 AM UTC 24
Finished Sep 18 06:43:52 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115096539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3115096539
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.598013069
Short name T230
Test name
Test status
Simulation time 204688595061 ps
CPU time 215.77 seconds
Started Sep 18 06:45:20 AM UTC 24
Finished Sep 18 06:48:59 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598013069 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.598013069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3494666684
Short name T138
Test name
Test status
Simulation time 18244816951 ps
CPU time 48.2 seconds
Started Sep 18 06:44:59 AM UTC 24
Finished Sep 18 06:45:49 AM UTC 24
Peak memory 221460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3494666684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.adc_ctrl_stress_all_with_rand_reset.3494666684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.2409591856
Short name T379
Test name
Test status
Simulation time 491784884 ps
CPU time 2.79 seconds
Started Sep 18 06:46:51 AM UTC 24
Finished Sep 18 06:46:55 AM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409591856 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2409591856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.610650438
Short name T249
Test name
Test status
Simulation time 163787900100 ps
CPU time 318.72 seconds
Started Sep 18 06:46:12 AM UTC 24
Finished Sep 18 06:51:35 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610650438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.610650438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.1034646333
Short name T241
Test name
Test status
Simulation time 494684149466 ps
CPU time 1336.15 seconds
Started Sep 18 06:45:43 AM UTC 24
Finished Sep 18 07:08:13 AM UTC 24
Peak memory 213496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034646333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1034646333
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1695051984
Short name T418
Test name
Test status
Simulation time 332786975366 ps
CPU time 581.37 seconds
Started Sep 18 06:45:49 AM UTC 24
Finished Sep 18 06:55:37 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695051984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.1695051984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.240736908
Short name T295
Test name
Test status
Simulation time 489714080661 ps
CPU time 1480.53 seconds
Started Sep 18 06:45:34 AM UTC 24
Finished Sep 18 07:10:29 AM UTC 24
Peak memory 213432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240736908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.240736908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.3125730559
Short name T471
Test name
Test status
Simulation time 489731591507 ps
CPU time 1235.11 seconds
Started Sep 18 06:45:34 AM UTC 24
Finished Sep 18 07:06:21 AM UTC 24
Peak memory 213352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125730559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.3125730559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1789443987
Short name T291
Test name
Test status
Simulation time 197734719284 ps
CPU time 355.79 seconds
Started Sep 18 06:46:06 AM UTC 24
Finished Sep 18 06:52:06 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789443987 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.1789443987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2624802737
Short name T101
Test name
Test status
Simulation time 402139871265 ps
CPU time 277.19 seconds
Started Sep 18 06:46:08 AM UTC 24
Finished Sep 18 06:50:49 AM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624802737 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.2624802737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.1884166433
Short name T407
Test name
Test status
Simulation time 85131118635 ps
CPU time 414.75 seconds
Started Sep 18 06:46:28 AM UTC 24
Finished Sep 18 06:53:28 AM UTC 24
Peak memory 211052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884166433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1884166433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.3610836930
Short name T382
Test name
Test status
Simulation time 21759921325 ps
CPU time 80.81 seconds
Started Sep 18 06:46:28 AM UTC 24
Finished Sep 18 06:47:51 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610836930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3610836930
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.3586584313
Short name T377
Test name
Test status
Simulation time 5029497239 ps
CPU time 11.73 seconds
Started Sep 18 06:46:14 AM UTC 24
Finished Sep 18 06:46:27 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586584313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3586584313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.2419934208
Short name T374
Test name
Test status
Simulation time 6020923324 ps
CPU time 4.18 seconds
Started Sep 18 06:45:28 AM UTC 24
Finished Sep 18 06:45:34 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419934208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2419934208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.1079381822
Short name T269
Test name
Test status
Simulation time 346250628674 ps
CPU time 221.23 seconds
Started Sep 18 06:46:50 AM UTC 24
Finished Sep 18 06:50:35 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079381822 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.1079381822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.1496083601
Short name T386
Test name
Test status
Simulation time 285111005 ps
CPU time 2.07 seconds
Started Sep 18 06:49:35 AM UTC 24
Finished Sep 18 06:49:38 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496083601 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1496083601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1221284089
Short name T248
Test name
Test status
Simulation time 359848300048 ps
CPU time 262.87 seconds
Started Sep 18 06:48:11 AM UTC 24
Finished Sep 18 06:52:37 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221284089 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.1221284089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.611023069
Short name T103
Test name
Test status
Simulation time 184562518567 ps
CPU time 119.56 seconds
Started Sep 18 06:48:53 AM UTC 24
Finished Sep 18 06:50:55 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611023069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.611023069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1974134626
Short name T244
Test name
Test status
Simulation time 159245600225 ps
CPU time 361.77 seconds
Started Sep 18 06:47:34 AM UTC 24
Finished Sep 18 06:53:40 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974134626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1974134626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.862136997
Short name T473
Test name
Test status
Simulation time 502780816552 ps
CPU time 1128.35 seconds
Started Sep 18 06:47:47 AM UTC 24
Finished Sep 18 07:06:47 AM UTC 24
Peak memory 213412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862136997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.862136997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.811062230
Short name T204
Test name
Test status
Simulation time 490507208829 ps
CPU time 281.04 seconds
Started Sep 18 06:47:09 AM UTC 24
Finished Sep 18 06:51:53 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811062230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.811062230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.2768043456
Short name T401
Test name
Test status
Simulation time 484646611602 ps
CPU time 302.79 seconds
Started Sep 18 06:47:24 AM UTC 24
Finished Sep 18 06:52:30 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768043456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.2768043456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.866502185
Short name T169
Test name
Test status
Simulation time 207903072200 ps
CPU time 115.11 seconds
Started Sep 18 06:47:52 AM UTC 24
Finished Sep 18 06:49:49 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866502185 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.866502185
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.476471368
Short name T464
Test name
Test status
Simulation time 401451535331 ps
CPU time 1058.91 seconds
Started Sep 18 06:47:57 AM UTC 24
Finished Sep 18 07:05:46 AM UTC 24
Peak memory 213764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476471368 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.476471368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.3839905766
Short name T207
Test name
Test status
Simulation time 121884800935 ps
CPU time 735.27 seconds
Started Sep 18 06:49:23 AM UTC 24
Finished Sep 18 07:01:45 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839905766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3839905766
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3614119428
Short name T388
Test name
Test status
Simulation time 31356664840 ps
CPU time 33.76 seconds
Started Sep 18 06:49:14 AM UTC 24
Finished Sep 18 06:49:49 AM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614119428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3614119428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.4124353665
Short name T384
Test name
Test status
Simulation time 4675845933 ps
CPU time 20.58 seconds
Started Sep 18 06:48:59 AM UTC 24
Finished Sep 18 06:49:21 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124353665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4124353665
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.1306225778
Short name T380
Test name
Test status
Simulation time 5734805964 ps
CPU time 26.06 seconds
Started Sep 18 06:46:55 AM UTC 24
Finished Sep 18 06:47:23 AM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306225778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1306225778
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.1471953496
Short name T387
Test name
Test status
Simulation time 6853287042 ps
CPU time 11.87 seconds
Started Sep 18 06:49:33 AM UTC 24
Finished Sep 18 06:49:46 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471953496 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.1471953496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.54230979
Short name T394
Test name
Test status
Simulation time 388451266 ps
CPU time 2.39 seconds
Started Sep 18 06:50:40 AM UTC 24
Finished Sep 18 06:50:43 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54230979 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.54230979
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.3939586203
Short name T276
Test name
Test status
Simulation time 563856455453 ps
CPU time 642.68 seconds
Started Sep 18 06:50:04 AM UTC 24
Finished Sep 18 07:00:54 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939586203 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.3939586203
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.103745831
Short name T234
Test name
Test status
Simulation time 322655586957 ps
CPU time 923.65 seconds
Started Sep 18 06:49:49 AM UTC 24
Finished Sep 18 07:05:22 AM UTC 24
Peak memory 213592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103745831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.103745831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.596627407
Short name T403
Test name
Test status
Simulation time 160564572058 ps
CPU time 183.37 seconds
Started Sep 18 06:49:50 AM UTC 24
Finished Sep 18 06:52:56 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596627407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.596627407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.3711080925
Short name T428
Test name
Test status
Simulation time 165308813635 ps
CPU time 495.22 seconds
Started Sep 18 06:49:42 AM UTC 24
Finished Sep 18 06:58:03 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711080925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3711080925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.767897862
Short name T424
Test name
Test status
Simulation time 328659912238 ps
CPU time 401.87 seconds
Started Sep 18 06:49:46 AM UTC 24
Finished Sep 18 06:56:32 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767897862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.767897862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.3950365496
Short name T263
Test name
Test status
Simulation time 193155789165 ps
CPU time 652.52 seconds
Started Sep 18 06:49:52 AM UTC 24
Finished Sep 18 07:00:52 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950365496 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.3950365496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1499391318
Short name T521
Test name
Test status
Simulation time 585986667862 ps
CPU time 1443.85 seconds
Started Sep 18 06:49:52 AM UTC 24
Finished Sep 18 07:14:10 AM UTC 24
Peak memory 213420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499391318 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.1499391318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.3575571180
Short name T222
Test name
Test status
Simulation time 82613735089 ps
CPU time 449.7 seconds
Started Sep 18 06:50:30 AM UTC 24
Finished Sep 18 06:58:04 AM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575571180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3575571180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1192096964
Short name T106
Test name
Test status
Simulation time 35910353093 ps
CPU time 47.05 seconds
Started Sep 18 06:50:21 AM UTC 24
Finished Sep 18 06:51:09 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192096964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1192096964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.3418234027
Short name T393
Test name
Test status
Simulation time 4994033264 ps
CPU time 22.89 seconds
Started Sep 18 06:50:16 AM UTC 24
Finished Sep 18 06:50:41 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418234027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3418234027
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.1772667462
Short name T390
Test name
Test status
Simulation time 5922056331 ps
CPU time 11.79 seconds
Started Sep 18 06:49:39 AM UTC 24
Finished Sep 18 06:49:52 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772667462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1772667462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1656621962
Short name T257
Test name
Test status
Simulation time 327223165305 ps
CPU time 871.5 seconds
Started Sep 18 06:50:36 AM UTC 24
Finished Sep 18 07:05:16 AM UTC 24
Peak memory 213692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656621962 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.1656621962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.597814097
Short name T397
Test name
Test status
Simulation time 489882319 ps
CPU time 1.36 seconds
Started Sep 18 06:51:41 AM UTC 24
Finished Sep 18 06:51:43 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597814097 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.597814097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2343244090
Short name T303
Test name
Test status
Simulation time 399225705817 ps
CPU time 854.92 seconds
Started Sep 18 06:50:57 AM UTC 24
Finished Sep 18 07:05:20 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343244090 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.2343244090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.3021212881
Short name T239
Test name
Test status
Simulation time 494794959123 ps
CPU time 297.05 seconds
Started Sep 18 06:50:49 AM UTC 24
Finished Sep 18 06:55:50 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021212881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3021212881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3067940306
Short name T413
Test name
Test status
Simulation time 490184136907 ps
CPU time 261.16 seconds
Started Sep 18 06:50:55 AM UTC 24
Finished Sep 18 06:55:20 AM UTC 24
Peak memory 211096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067940306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.3067940306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.399446248
Short name T333
Test name
Test status
Simulation time 495539315614 ps
CPU time 1341.3 seconds
Started Sep 18 06:50:44 AM UTC 24
Finished Sep 18 07:13:18 AM UTC 24
Peak memory 213432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399446248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.399446248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.2433402567
Short name T468
Test name
Test status
Simulation time 327229288053 ps
CPU time 918.82 seconds
Started Sep 18 06:50:44 AM UTC 24
Finished Sep 18 07:06:12 AM UTC 24
Peak memory 213424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433402567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.2433402567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.2679158646
Short name T264
Test name
Test status
Simulation time 509865227318 ps
CPU time 1133.22 seconds
Started Sep 18 06:50:56 AM UTC 24
Finished Sep 18 07:10:01 AM UTC 24
Peak memory 213432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679158646 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.2679158646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1576226642
Short name T409
Test name
Test status
Simulation time 611458266482 ps
CPU time 206.64 seconds
Started Sep 18 06:50:56 AM UTC 24
Finished Sep 18 06:54:26 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576226642 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.1576226642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.681180609
Short name T437
Test name
Test status
Simulation time 128467128944 ps
CPU time 531.51 seconds
Started Sep 18 06:51:28 AM UTC 24
Finished Sep 18 07:00:25 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681180609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.681180609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.999343789
Short name T399
Test name
Test status
Simulation time 26403203073 ps
CPU time 55.29 seconds
Started Sep 18 06:51:23 AM UTC 24
Finished Sep 18 06:52:19 AM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999343789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.999343789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1167164742
Short name T396
Test name
Test status
Simulation time 4610584777 ps
CPU time 19.01 seconds
Started Sep 18 06:51:19 AM UTC 24
Finished Sep 18 06:51:40 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167164742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1167164742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.3335567487
Short name T104
Test name
Test status
Simulation time 5919554273 ps
CPU time 13.06 seconds
Started Sep 18 06:50:41 AM UTC 24
Finished Sep 18 06:50:55 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335567487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3335567487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.3570328351
Short name T260
Test name
Test status
Simulation time 182853886663 ps
CPU time 474.39 seconds
Started Sep 18 06:51:36 AM UTC 24
Finished Sep 18 06:59:35 AM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570328351 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.3570328351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.895469812
Short name T318
Test name
Test status
Simulation time 5113902126 ps
CPU time 22.86 seconds
Started Sep 18 06:51:28 AM UTC 24
Finished Sep 18 06:51:52 AM UTC 24
Peak memory 221324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=895469812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
15.adc_ctrl_stress_all_with_rand_reset.895469812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1585925092
Short name T405
Test name
Test status
Simulation time 353092057 ps
CPU time 2.15 seconds
Started Sep 18 06:53:03 AM UTC 24
Finished Sep 18 06:53:06 AM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585925092 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1585925092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.607901055
Short name T283
Test name
Test status
Simulation time 167338875186 ps
CPU time 329.22 seconds
Started Sep 18 06:52:32 AM UTC 24
Finished Sep 18 06:58:05 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607901055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.607901055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3111792156
Short name T519
Test name
Test status
Simulation time 496724475093 ps
CPU time 1309.69 seconds
Started Sep 18 06:51:58 AM UTC 24
Finished Sep 18 07:14:00 AM UTC 24
Peak memory 213360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111792156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.3111792156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.697108779
Short name T411
Test name
Test status
Simulation time 328130752862 ps
CPU time 183.91 seconds
Started Sep 18 06:51:48 AM UTC 24
Finished Sep 18 06:54:54 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697108779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.697108779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.547727225
Short name T430
Test name
Test status
Simulation time 496359415847 ps
CPU time 383.26 seconds
Started Sep 18 06:51:52 AM UTC 24
Finished Sep 18 06:58:20 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547727225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.547727225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.658853464
Short name T498
Test name
Test status
Simulation time 406853298027 ps
CPU time 1127.16 seconds
Started Sep 18 06:52:20 AM UTC 24
Finished Sep 18 07:11:19 AM UTC 24
Peak memory 213352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658853464 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.658853464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.667462013
Short name T211
Test name
Test status
Simulation time 111332426035 ps
CPU time 631.98 seconds
Started Sep 18 06:52:42 AM UTC 24
Finished Sep 18 07:03:20 AM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667462013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.667462013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.3800551617
Short name T404
Test name
Test status
Simulation time 26762930185 ps
CPU time 19.31 seconds
Started Sep 18 06:52:42 AM UTC 24
Finished Sep 18 06:53:02 AM UTC 24
Peak memory 210556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800551617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3800551617
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.4130871597
Short name T402
Test name
Test status
Simulation time 2878605391 ps
CPU time 8 seconds
Started Sep 18 06:52:39 AM UTC 24
Finished Sep 18 06:52:48 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130871597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4130871597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1924733679
Short name T398
Test name
Test status
Simulation time 5796341025 ps
CPU time 12.52 seconds
Started Sep 18 06:51:44 AM UTC 24
Finished Sep 18 06:51:58 AM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924733679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1924733679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.3237634456
Short name T43
Test name
Test status
Simulation time 165538207766 ps
CPU time 569.53 seconds
Started Sep 18 06:52:57 AM UTC 24
Finished Sep 18 07:02:33 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237634456 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.3237634456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3905178513
Short name T254
Test name
Test status
Simulation time 5859057198 ps
CPU time 13.61 seconds
Started Sep 18 06:52:49 AM UTC 24
Finished Sep 18 06:53:04 AM UTC 24
Peak memory 220992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3905178513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.adc_ctrl_stress_all_with_rand_reset.3905178513
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.4098799309
Short name T415
Test name
Test status
Simulation time 582850414 ps
CPU time 1.05 seconds
Started Sep 18 06:55:21 AM UTC 24
Finished Sep 18 06:55:23 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098799309 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.4098799309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.269497069
Short name T261
Test name
Test status
Simulation time 530484121241 ps
CPU time 703.06 seconds
Started Sep 18 06:54:02 AM UTC 24
Finished Sep 18 07:05:52 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269497069 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.269497069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.939493145
Short name T302
Test name
Test status
Simulation time 165439766005 ps
CPU time 515.82 seconds
Started Sep 18 06:54:13 AM UTC 24
Finished Sep 18 07:02:54 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939493145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.939493145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2474983835
Short name T416
Test name
Test status
Simulation time 160150674963 ps
CPU time 118.29 seconds
Started Sep 18 06:53:28 AM UTC 24
Finished Sep 18 06:55:29 AM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474983835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.2474983835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1690941308
Short name T426
Test name
Test status
Simulation time 168073655337 ps
CPU time 285.13 seconds
Started Sep 18 06:53:11 AM UTC 24
Finished Sep 18 06:58:00 AM UTC 24
Peak memory 210960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690941308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.1690941308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.2502930686
Short name T275
Test name
Test status
Simulation time 421082263659 ps
CPU time 602.19 seconds
Started Sep 18 06:53:32 AM UTC 24
Finished Sep 18 07:03:41 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502930686 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.2502930686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.458997358
Short name T455
Test name
Test status
Simulation time 407505811127 ps
CPU time 603.7 seconds
Started Sep 18 06:53:40 AM UTC 24
Finished Sep 18 07:03:51 AM UTC 24
Peak memory 211024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458997358 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.458997358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.3544409938
Short name T209
Test name
Test status
Simulation time 129625244758 ps
CPU time 975.22 seconds
Started Sep 18 06:54:55 AM UTC 24
Finished Sep 18 07:11:20 AM UTC 24
Peak memory 213700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544409938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3544409938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.2655108102
Short name T94
Test name
Test status
Simulation time 38145841628 ps
CPU time 117.29 seconds
Started Sep 18 06:54:50 AM UTC 24
Finished Sep 18 06:56:49 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655108102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2655108102
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3940044172
Short name T410
Test name
Test status
Simulation time 5160001556 ps
CPU time 21.33 seconds
Started Sep 18 06:54:27 AM UTC 24
Finished Sep 18 06:54:49 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940044172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3940044172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.3589226692
Short name T406
Test name
Test status
Simulation time 6192399246 ps
CPU time 5.64 seconds
Started Sep 18 06:53:04 AM UTC 24
Finished Sep 18 06:53:11 AM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589226692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3589226692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1885271054
Short name T23
Test name
Test status
Simulation time 3960193510 ps
CPU time 26.25 seconds
Started Sep 18 06:54:59 AM UTC 24
Finished Sep 18 06:55:26 AM UTC 24
Peak memory 221360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1885271054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.adc_ctrl_stress_all_with_rand_reset.1885271054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.2814698486
Short name T389
Test name
Test status
Simulation time 400363670 ps
CPU time 1.22 seconds
Started Sep 18 06:56:23 AM UTC 24
Finished Sep 18 06:56:25 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814698486 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2814698486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.1733994090
Short name T321
Test name
Test status
Simulation time 176380861426 ps
CPU time 132.64 seconds
Started Sep 18 06:55:51 AM UTC 24
Finished Sep 18 06:58:06 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733994090 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.1733994090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.2675143492
Short name T435
Test name
Test status
Simulation time 166961375833 ps
CPU time 209.94 seconds
Started Sep 18 06:55:53 AM UTC 24
Finished Sep 18 06:59:26 AM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675143492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2675143492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.1049043968
Short name T100
Test name
Test status
Simulation time 329727625483 ps
CPU time 117.16 seconds
Started Sep 18 06:55:29 AM UTC 24
Finished Sep 18 06:57:29 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049043968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1049043968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3693827814
Short name T564
Test name
Test status
Simulation time 500286366893 ps
CPU time 1403.03 seconds
Started Sep 18 06:55:31 AM UTC 24
Finished Sep 18 07:19:07 AM UTC 24
Peak memory 213372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693827814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.3693827814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.3680319968
Short name T453
Test name
Test status
Simulation time 334310749116 ps
CPU time 487.2 seconds
Started Sep 18 06:55:24 AM UTC 24
Finished Sep 18 07:03:37 AM UTC 24
Peak memory 211020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680319968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3680319968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.3451694029
Short name T96
Test name
Test status
Simulation time 166204684221 ps
CPU time 99.54 seconds
Started Sep 18 06:55:27 AM UTC 24
Finished Sep 18 06:57:09 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451694029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.3451694029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.836101559
Short name T575
Test name
Test status
Simulation time 509268688582 ps
CPU time 1505.16 seconds
Started Sep 18 06:55:37 AM UTC 24
Finished Sep 18 07:20:58 AM UTC 24
Peak memory 213360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836101559 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.836101559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.587629201
Short name T517
Test name
Test status
Simulation time 395296781296 ps
CPU time 1069.14 seconds
Started Sep 18 06:55:49 AM UTC 24
Finished Sep 18 07:13:48 AM UTC 24
Peak memory 213348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587629201 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.587629201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.1567941783
Short name T344
Test name
Test status
Simulation time 112295353745 ps
CPU time 695.19 seconds
Started Sep 18 06:56:08 AM UTC 24
Finished Sep 18 07:07:50 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567941783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1567941783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1520069374
Short name T422
Test name
Test status
Simulation time 26370885227 ps
CPU time 22.7 seconds
Started Sep 18 06:56:03 AM UTC 24
Finished Sep 18 06:56:27 AM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520069374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1520069374
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.3495157488
Short name T420
Test name
Test status
Simulation time 3643360293 ps
CPU time 2.95 seconds
Started Sep 18 06:55:58 AM UTC 24
Finished Sep 18 06:56:02 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495157488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3495157488
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.4222302045
Short name T417
Test name
Test status
Simulation time 6094647469 ps
CPU time 7.07 seconds
Started Sep 18 06:55:22 AM UTC 24
Finished Sep 18 06:55:30 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222302045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4222302045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2167247638
Short name T90
Test name
Test status
Simulation time 95813824015 ps
CPU time 22.68 seconds
Started Sep 18 06:56:12 AM UTC 24
Finished Sep 18 06:56:36 AM UTC 24
Peak memory 227960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2167247638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.adc_ctrl_stress_all_with_rand_reset.2167247638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.2354948366
Short name T425
Test name
Test status
Simulation time 478904930 ps
CPU time 3.01 seconds
Started Sep 18 06:57:53 AM UTC 24
Finished Sep 18 06:57:57 AM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354948366 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2354948366
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3963684267
Short name T316
Test name
Test status
Simulation time 162756189479 ps
CPU time 424.59 seconds
Started Sep 18 06:56:50 AM UTC 24
Finished Sep 18 07:03:59 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963684267 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.3963684267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.4245200695
Short name T282
Test name
Test status
Simulation time 369069700894 ps
CPU time 491.94 seconds
Started Sep 18 06:56:54 AM UTC 24
Finished Sep 18 07:05:11 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245200695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4245200695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.1566359581
Short name T238
Test name
Test status
Simulation time 328084178524 ps
CPU time 505.8 seconds
Started Sep 18 06:56:33 AM UTC 24
Finished Sep 18 07:05:05 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566359581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1566359581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1104359373
Short name T447
Test name
Test status
Simulation time 500918430986 ps
CPU time 353.91 seconds
Started Sep 18 06:56:36 AM UTC 24
Finished Sep 18 07:02:35 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104359373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.1104359373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.2249215346
Short name T442
Test name
Test status
Simulation time 331391811219 ps
CPU time 277.96 seconds
Started Sep 18 06:56:27 AM UTC 24
Finished Sep 18 07:01:09 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249215346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2249215346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.1184080842
Short name T433
Test name
Test status
Simulation time 325989387328 ps
CPU time 145.33 seconds
Started Sep 18 06:56:32 AM UTC 24
Finished Sep 18 06:59:00 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184080842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.1184080842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.372666501
Short name T309
Test name
Test status
Simulation time 180355258125 ps
CPU time 70.88 seconds
Started Sep 18 06:56:42 AM UTC 24
Finished Sep 18 06:57:55 AM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372666501 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.372666501
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.356372810
Short name T98
Test name
Test status
Simulation time 205855084972 ps
CPU time 34.46 seconds
Started Sep 18 06:56:46 AM UTC 24
Finished Sep 18 06:57:21 AM UTC 24
Peak memory 210960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356372810 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.356372810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.2076257416
Short name T431
Test name
Test status
Simulation time 32953718285 ps
CPU time 64.87 seconds
Started Sep 18 06:57:14 AM UTC 24
Finished Sep 18 06:58:20 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076257416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2076257416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1608198226
Short name T97
Test name
Test status
Simulation time 4580201520 ps
CPU time 2.69 seconds
Started Sep 18 06:57:10 AM UTC 24
Finished Sep 18 06:57:13 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608198226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1608198226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1183377802
Short name T95
Test name
Test status
Simulation time 5965663844 ps
CPU time 25.3 seconds
Started Sep 18 06:56:26 AM UTC 24
Finished Sep 18 06:56:53 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183377802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1183377802
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.1983097679
Short name T509
Test name
Test status
Simulation time 283425973260 ps
CPU time 910.48 seconds
Started Sep 18 06:57:29 AM UTC 24
Finished Sep 18 07:12:48 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983097679 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.1983097679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3558712695
Short name T156
Test name
Test status
Simulation time 39591961127 ps
CPU time 39.39 seconds
Started Sep 18 06:57:23 AM UTC 24
Finished Sep 18 06:58:04 AM UTC 24
Peak memory 221460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3558712695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.adc_ctrl_stress_all_with_rand_reset.3558712695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.467819610
Short name T48
Test name
Test status
Simulation time 302400577 ps
CPU time 1 seconds
Started Sep 18 06:32:54 AM UTC 24
Finished Sep 18 06:32:56 AM UTC 24
Peak memory 210380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467819610 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.467819610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2065382739
Short name T232
Test name
Test status
Simulation time 328811690915 ps
CPU time 777.99 seconds
Started Sep 18 06:32:37 AM UTC 24
Finished Sep 18 06:45:42 AM UTC 24
Peak memory 213372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065382739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2065382739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.1659294287
Short name T142
Test name
Test status
Simulation time 330436901201 ps
CPU time 313.13 seconds
Started Sep 18 06:32:33 AM UTC 24
Finished Sep 18 06:37:50 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659294287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1659294287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3174481879
Short name T200
Test name
Test status
Simulation time 321621216379 ps
CPU time 366.03 seconds
Started Sep 18 06:32:35 AM UTC 24
Finished Sep 18 06:38:45 AM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174481879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.3174481879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.415565297
Short name T56
Test name
Test status
Simulation time 168207845791 ps
CPU time 194.88 seconds
Started Sep 18 06:32:37 AM UTC 24
Finished Sep 18 06:35:55 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415565297 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.415565297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2065624046
Short name T378
Test name
Test status
Simulation time 612985905687 ps
CPU time 831.08 seconds
Started Sep 18 06:32:43 AM UTC 24
Finished Sep 18 06:46:42 AM UTC 24
Peak memory 213440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065624046 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.2065624046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1468228630
Short name T51
Test name
Test status
Simulation time 21972625322 ps
CPU time 16.61 seconds
Started Sep 18 06:32:46 AM UTC 24
Finished Sep 18 06:33:04 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468228630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1468228630
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1710104897
Short name T49
Test name
Test status
Simulation time 3445932711 ps
CPU time 10.76 seconds
Started Sep 18 06:32:45 AM UTC 24
Finished Sep 18 06:32:57 AM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710104897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1710104897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.4170066104
Short name T55
Test name
Test status
Simulation time 7310450131 ps
CPU time 20.04 seconds
Started Sep 18 06:32:50 AM UTC 24
Finished Sep 18 06:33:11 AM UTC 24
Peak memory 243040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170066104 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.4170066104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3929913840
Short name T10
Test name
Test status
Simulation time 5723413778 ps
CPU time 13.17 seconds
Started Sep 18 06:32:32 AM UTC 24
Finished Sep 18 06:32:46 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929913840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3929913840
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.3977791308
Short name T45
Test name
Test status
Simulation time 184878227550 ps
CPU time 149.5 seconds
Started Sep 18 06:32:47 AM UTC 24
Finished Sep 18 06:35:18 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977791308 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.3977791308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.246639441
Short name T432
Test name
Test status
Simulation time 363892867 ps
CPU time 2.32 seconds
Started Sep 18 06:58:40 AM UTC 24
Finished Sep 18 06:58:44 AM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246639441 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.246639441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1357005335
Short name T327
Test name
Test status
Simulation time 164912418045 ps
CPU time 413.07 seconds
Started Sep 18 06:58:06 AM UTC 24
Finished Sep 18 07:05:03 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357005335 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.1357005335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.1036506566
Short name T330
Test name
Test status
Simulation time 157816931998 ps
CPU time 425.71 seconds
Started Sep 18 06:58:07 AM UTC 24
Finished Sep 18 07:05:17 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036506566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1036506566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.3500586922
Short name T334
Test name
Test status
Simulation time 333637402956 ps
CPU time 953.03 seconds
Started Sep 18 06:58:02 AM UTC 24
Finished Sep 18 07:14:05 AM UTC 24
Peak memory 213424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500586922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3500586922
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3160170700
Short name T530
Test name
Test status
Simulation time 333039874215 ps
CPU time 1033.78 seconds
Started Sep 18 06:58:04 AM UTC 24
Finished Sep 18 07:15:28 AM UTC 24
Peak memory 213436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160170700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.3160170700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.448827125
Short name T326
Test name
Test status
Simulation time 164565469343 ps
CPU time 169.77 seconds
Started Sep 18 06:57:58 AM UTC 24
Finished Sep 18 07:00:51 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448827125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.448827125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.2230988845
Short name T445
Test name
Test status
Simulation time 165512914620 ps
CPU time 222.07 seconds
Started Sep 18 06:58:00 AM UTC 24
Finished Sep 18 07:01:45 AM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230988845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.2230988845
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.3128757912
Short name T438
Test name
Test status
Simulation time 165436062672 ps
CPU time 168.95 seconds
Started Sep 18 06:58:05 AM UTC 24
Finished Sep 18 07:00:56 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128757912 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.3128757912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1584351528
Short name T522
Test name
Test status
Simulation time 594291054853 ps
CPU time 955.99 seconds
Started Sep 18 06:58:05 AM UTC 24
Finished Sep 18 07:14:10 AM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584351528 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.1584351528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.1205901602
Short name T476
Test name
Test status
Simulation time 120480587134 ps
CPU time 545.35 seconds
Started Sep 18 06:58:21 AM UTC 24
Finished Sep 18 07:07:32 AM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205901602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1205901602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.2031736496
Short name T436
Test name
Test status
Simulation time 37929540346 ps
CPU time 70.97 seconds
Started Sep 18 06:58:18 AM UTC 24
Finished Sep 18 06:59:31 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031736496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2031736496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.3727771437
Short name T429
Test name
Test status
Simulation time 3411572405 ps
CPU time 8.98 seconds
Started Sep 18 06:58:07 AM UTC 24
Finished Sep 18 06:58:17 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727771437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3727771437
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.984003340
Short name T427
Test name
Test status
Simulation time 6010500743 ps
CPU time 4.8 seconds
Started Sep 18 06:57:56 AM UTC 24
Finished Sep 18 06:58:02 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984003340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.984003340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.1827302926
Short name T446
Test name
Test status
Simulation time 194458884602 ps
CPU time 233.24 seconds
Started Sep 18 06:58:24 AM UTC 24
Finished Sep 18 07:02:20 AM UTC 24
Peak memory 210808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827302926 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.1827302926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.518208898
Short name T157
Test name
Test status
Simulation time 10286299956 ps
CPU time 17.28 seconds
Started Sep 18 06:58:21 AM UTC 24
Finished Sep 18 06:58:39 AM UTC 24
Peak memory 221016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=518208898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
20.adc_ctrl_stress_all_with_rand_reset.518208898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.3794186885
Short name T440
Test name
Test status
Simulation time 364151449 ps
CPU time 1.22 seconds
Started Sep 18 07:01:02 AM UTC 24
Finished Sep 18 07:01:05 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794186885 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3794186885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.37100273
Short name T176
Test name
Test status
Simulation time 504958659147 ps
CPU time 605.83 seconds
Started Sep 18 07:00:26 AM UTC 24
Finished Sep 18 07:10:39 AM UTC 24
Peak memory 210944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37100273 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.37100273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.1593780752
Short name T262
Test name
Test status
Simulation time 185700758371 ps
CPU time 435.01 seconds
Started Sep 18 07:00:33 AM UTC 24
Finished Sep 18 07:07:53 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593780752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1593780752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.2669061017
Short name T189
Test name
Test status
Simulation time 495806460084 ps
CPU time 254.43 seconds
Started Sep 18 06:59:27 AM UTC 24
Finished Sep 18 07:03:44 AM UTC 24
Peak memory 210908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669061017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2669061017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2651809030
Short name T484
Test name
Test status
Simulation time 163971941979 ps
CPU time 559.69 seconds
Started Sep 18 06:59:32 AM UTC 24
Finished Sep 18 07:08:58 AM UTC 24
Peak memory 211032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651809030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.2651809030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.4101261304
Short name T458
Test name
Test status
Simulation time 326736599137 ps
CPU time 331.66 seconds
Started Sep 18 06:59:00 AM UTC 24
Finished Sep 18 07:04:36 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101261304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4101261304
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.858849089
Short name T529
Test name
Test status
Simulation time 493853221505 ps
CPU time 942.42 seconds
Started Sep 18 06:59:12 AM UTC 24
Finished Sep 18 07:15:04 AM UTC 24
Peak memory 213352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858849089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.858849089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1580863045
Short name T477
Test name
Test status
Simulation time 592859908104 ps
CPU time 437.19 seconds
Started Sep 18 07:00:13 AM UTC 24
Finished Sep 18 07:07:35 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580863045 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.1580863045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.3296329249
Short name T212
Test name
Test status
Simulation time 107880593215 ps
CPU time 568.19 seconds
Started Sep 18 07:00:52 AM UTC 24
Finished Sep 18 07:10:26 AM UTC 24
Peak memory 211316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296329249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3296329249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.240046738
Short name T441
Test name
Test status
Simulation time 32582669098 ps
CPU time 14.21 seconds
Started Sep 18 07:00:51 AM UTC 24
Finished Sep 18 07:01:07 AM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240046738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.240046738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.2399772973
Short name T439
Test name
Test status
Simulation time 3814576388 ps
CPU time 10.03 seconds
Started Sep 18 07:00:50 AM UTC 24
Finished Sep 18 07:01:01 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399772973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2399772973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.4189669894
Short name T434
Test name
Test status
Simulation time 5834812337 ps
CPU time 25.65 seconds
Started Sep 18 06:58:44 AM UTC 24
Finished Sep 18 06:59:11 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189669894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.4189669894
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1394128140
Short name T443
Test name
Test status
Simulation time 3296451913 ps
CPU time 15.65 seconds
Started Sep 18 07:00:54 AM UTC 24
Finished Sep 18 07:01:11 AM UTC 24
Peak memory 221348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1394128140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.adc_ctrl_stress_all_with_rand_reset.1394128140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.1926746410
Short name T451
Test name
Test status
Simulation time 517033090 ps
CPU time 1.53 seconds
Started Sep 18 07:03:14 AM UTC 24
Finished Sep 18 07:03:16 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926746410 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1926746410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.2117621059
Short name T454
Test name
Test status
Simulation time 165111772230 ps
CPU time 118.97 seconds
Started Sep 18 07:01:46 AM UTC 24
Finished Sep 18 07:03:47 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117621059 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.2117621059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.1758638175
Short name T293
Test name
Test status
Simulation time 325662973427 ps
CPU time 980.48 seconds
Started Sep 18 07:02:21 AM UTC 24
Finished Sep 18 07:18:51 AM UTC 24
Peak memory 213740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758638175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1758638175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.4159329464
Short name T472
Test name
Test status
Simulation time 167365140535 ps
CPU time 327.3 seconds
Started Sep 18 07:01:12 AM UTC 24
Finished Sep 18 07:06:43 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159329464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4159329464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2100679318
Short name T541
Test name
Test status
Simulation time 328255431590 ps
CPU time 900.09 seconds
Started Sep 18 07:01:27 AM UTC 24
Finished Sep 18 07:16:36 AM UTC 24
Peak memory 213412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100679318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.2100679318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.368871911
Short name T532
Test name
Test status
Simulation time 328009400474 ps
CPU time 855.11 seconds
Started Sep 18 07:01:08 AM UTC 24
Finished Sep 18 07:15:31 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368871911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.368871911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.2196940268
Short name T462
Test name
Test status
Simulation time 501439650479 ps
CPU time 262.66 seconds
Started Sep 18 07:01:10 AM UTC 24
Finished Sep 18 07:05:35 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196940268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.2196940268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.2234704610
Short name T246
Test name
Test status
Simulation time 177067907700 ps
CPU time 496.51 seconds
Started Sep 18 07:01:30 AM UTC 24
Finished Sep 18 07:09:52 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234704610 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.2234704610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3335522362
Short name T449
Test name
Test status
Simulation time 215913878952 ps
CPU time 81.08 seconds
Started Sep 18 07:01:46 AM UTC 24
Finished Sep 18 07:03:09 AM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335522362 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.3335522362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.1912349929
Short name T349
Test name
Test status
Simulation time 101588740586 ps
CPU time 525.96 seconds
Started Sep 18 07:02:46 AM UTC 24
Finished Sep 18 07:11:38 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912349929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1912349929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.1906493714
Short name T456
Test name
Test status
Simulation time 31418805100 ps
CPU time 104.18 seconds
Started Sep 18 07:02:35 AM UTC 24
Finished Sep 18 07:04:21 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906493714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1906493714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.1677590626
Short name T448
Test name
Test status
Simulation time 4754129441 ps
CPU time 10.58 seconds
Started Sep 18 07:02:34 AM UTC 24
Finished Sep 18 07:02:46 AM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677590626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1677590626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.2514429260
Short name T444
Test name
Test status
Simulation time 6021161752 ps
CPU time 22.39 seconds
Started Sep 18 07:01:05 AM UTC 24
Finished Sep 18 07:01:29 AM UTC 24
Peak memory 210648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514429260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2514429260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.1915953544
Short name T240
Test name
Test status
Simulation time 187082619654 ps
CPU time 185.3 seconds
Started Sep 18 07:03:09 AM UTC 24
Finished Sep 18 07:06:17 AM UTC 24
Peak memory 210952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915953544 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.1915953544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1091167018
Short name T450
Test name
Test status
Simulation time 3740253978 ps
CPU time 15.85 seconds
Started Sep 18 07:02:55 AM UTC 24
Finished Sep 18 07:03:12 AM UTC 24
Peak memory 210624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1091167018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.adc_ctrl_stress_all_with_rand_reset.1091167018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.4287142289
Short name T459
Test name
Test status
Simulation time 486124331 ps
CPU time 1.36 seconds
Started Sep 18 07:05:05 AM UTC 24
Finished Sep 18 07:05:07 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287142289 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4287142289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.1142437873
Short name T599
Test name
Test status
Simulation time 549481667570 ps
CPU time 1185.54 seconds
Started Sep 18 07:04:00 AM UTC 24
Finished Sep 18 07:23:57 AM UTC 24
Peak memory 213424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142437873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1142437873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.1878282746
Short name T475
Test name
Test status
Simulation time 163192252961 ps
CPU time 226.97 seconds
Started Sep 18 07:03:38 AM UTC 24
Finished Sep 18 07:07:28 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878282746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1878282746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1571667905
Short name T478
Test name
Test status
Simulation time 326226710315 ps
CPU time 232.45 seconds
Started Sep 18 07:03:42 AM UTC 24
Finished Sep 18 07:07:37 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571667905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.1571667905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.4276002449
Short name T312
Test name
Test status
Simulation time 158883695372 ps
CPU time 376.38 seconds
Started Sep 18 07:03:21 AM UTC 24
Finished Sep 18 07:09:41 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276002449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4276002449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.1961760600
Short name T494
Test name
Test status
Simulation time 159922909556 ps
CPU time 447.97 seconds
Started Sep 18 07:03:24 AM UTC 24
Finished Sep 18 07:10:56 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961760600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.1961760600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.1102787917
Short name T194
Test name
Test status
Simulation time 530811901817 ps
CPU time 414.13 seconds
Started Sep 18 07:03:45 AM UTC 24
Finished Sep 18 07:10:44 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102787917 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.1102787917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2889915112
Short name T481
Test name
Test status
Simulation time 213502899566 ps
CPU time 238.97 seconds
Started Sep 18 07:03:48 AM UTC 24
Finished Sep 18 07:07:50 AM UTC 24
Peak memory 210748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889915112 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.2889915112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.2615899753
Short name T565
Test name
Test status
Simulation time 98327539243 ps
CPU time 869.67 seconds
Started Sep 18 07:04:34 AM UTC 24
Finished Sep 18 07:19:13 AM UTC 24
Peak memory 213636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615899753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2615899753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.2717732360
Short name T470
Test name
Test status
Simulation time 41030640626 ps
CPU time 107.05 seconds
Started Sep 18 07:04:28 AM UTC 24
Finished Sep 18 07:06:17 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717732360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2717732360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.107480728
Short name T457
Test name
Test status
Simulation time 4236679887 ps
CPU time 9.73 seconds
Started Sep 18 07:04:22 AM UTC 24
Finished Sep 18 07:04:33 AM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107480728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.107480728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.2767750817
Short name T452
Test name
Test status
Simulation time 6093303730 ps
CPU time 5.3 seconds
Started Sep 18 07:03:17 AM UTC 24
Finished Sep 18 07:03:23 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767750817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2767750817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.1838432511
Short name T460
Test name
Test status
Simulation time 6730840068 ps
CPU time 7.43 seconds
Started Sep 18 07:05:05 AM UTC 24
Finished Sep 18 07:05:13 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838432511 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.1838432511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.4278142995
Short name T467
Test name
Test status
Simulation time 325249441 ps
CPU time 1.24 seconds
Started Sep 18 07:06:04 AM UTC 24
Finished Sep 18 07:06:06 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278142995 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4278142995
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.3508551832
Short name T322
Test name
Test status
Simulation time 166824315421 ps
CPU time 547.75 seconds
Started Sep 18 07:05:23 AM UTC 24
Finished Sep 18 07:14:37 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508551832 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.3508551832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.309669985
Short name T624
Test name
Test status
Simulation time 511559538236 ps
CPU time 1298.69 seconds
Started Sep 18 07:05:27 AM UTC 24
Finished Sep 18 07:27:18 AM UTC 24
Peak memory 213728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309669985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.309669985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.4288135159
Short name T550
Test name
Test status
Simulation time 321853176719 ps
CPU time 769.59 seconds
Started Sep 18 07:05:14 AM UTC 24
Finished Sep 18 07:18:11 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288135159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4288135159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1518174507
Short name T620
Test name
Test status
Simulation time 501788878631 ps
CPU time 1284.69 seconds
Started Sep 18 07:05:17 AM UTC 24
Finished Sep 18 07:26:54 AM UTC 24
Peak memory 213364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518174507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.1518174507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.3974919290
Short name T555
Test name
Test status
Simulation time 335918563564 ps
CPU time 792.47 seconds
Started Sep 18 07:05:08 AM UTC 24
Finished Sep 18 07:18:28 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974919290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3974919290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.2691082805
Short name T669
Test name
Test status
Simulation time 495973035025 ps
CPU time 1606.76 seconds
Started Sep 18 07:05:12 AM UTC 24
Finished Sep 18 07:32:14 AM UTC 24
Peak memory 213412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691082805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.2691082805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.3141951527
Short name T317
Test name
Test status
Simulation time 172839960616 ps
CPU time 558.96 seconds
Started Sep 18 07:05:18 AM UTC 24
Finished Sep 18 07:14:43 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141951527 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.3141951527
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1881836768
Short name T582
Test name
Test status
Simulation time 382407235290 ps
CPU time 942.12 seconds
Started Sep 18 07:05:21 AM UTC 24
Finished Sep 18 07:21:12 AM UTC 24
Peak memory 213404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881836768 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.1881836768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.2947649230
Short name T500
Test name
Test status
Simulation time 91082228472 ps
CPU time 346.82 seconds
Started Sep 18 07:05:47 AM UTC 24
Finished Sep 18 07:11:37 AM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947649230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2947649230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.3725599733
Short name T465
Test name
Test status
Simulation time 35712730504 ps
CPU time 15.61 seconds
Started Sep 18 07:05:42 AM UTC 24
Finished Sep 18 07:05:59 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725599733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3725599733
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.2894315660
Short name T463
Test name
Test status
Simulation time 2880953539 ps
CPU time 4.05 seconds
Started Sep 18 07:05:36 AM UTC 24
Finished Sep 18 07:05:41 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894315660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2894315660
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.2622740801
Short name T461
Test name
Test status
Simulation time 6037609691 ps
CPU time 19.32 seconds
Started Sep 18 07:05:06 AM UTC 24
Finished Sep 18 07:05:26 AM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622740801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2622740801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.3319096272
Short name T535
Test name
Test status
Simulation time 209397083350 ps
CPU time 607.83 seconds
Started Sep 18 07:06:00 AM UTC 24
Finished Sep 18 07:16:14 AM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319096272 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.3319096272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1573638724
Short name T466
Test name
Test status
Simulation time 10785509103 ps
CPU time 9.16 seconds
Started Sep 18 07:05:53 AM UTC 24
Finished Sep 18 07:06:03 AM UTC 24
Peak memory 210912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1573638724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.adc_ctrl_stress_all_with_rand_reset.1573638724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.3904973490
Short name T479
Test name
Test status
Simulation time 323884207 ps
CPU time 1.1 seconds
Started Sep 18 07:07:36 AM UTC 24
Finished Sep 18 07:07:38 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904973490 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3904973490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.145618237
Short name T315
Test name
Test status
Simulation time 635867520164 ps
CPU time 335.96 seconds
Started Sep 18 07:06:43 AM UTC 24
Finished Sep 18 07:12:23 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145618237 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.145618237
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.1956762159
Short name T331
Test name
Test status
Simulation time 320155109250 ps
CPU time 342.48 seconds
Started Sep 18 07:06:48 AM UTC 24
Finished Sep 18 07:12:34 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956762159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1956762159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.2797975473
Short name T523
Test name
Test status
Simulation time 163122354294 ps
CPU time 470.83 seconds
Started Sep 18 07:06:18 AM UTC 24
Finished Sep 18 07:14:14 AM UTC 24
Peak memory 211064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797975473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2797975473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3738236033
Short name T518
Test name
Test status
Simulation time 328247400240 ps
CPU time 451.54 seconds
Started Sep 18 07:06:18 AM UTC 24
Finished Sep 18 07:13:55 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738236033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.3738236033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.2868491110
Short name T485
Test name
Test status
Simulation time 334226966252 ps
CPU time 169.58 seconds
Started Sep 18 07:06:13 AM UTC 24
Finished Sep 18 07:09:05 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868491110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2868491110
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.2245785716
Short name T578
Test name
Test status
Simulation time 326354157547 ps
CPU time 880.98 seconds
Started Sep 18 07:06:16 AM UTC 24
Finished Sep 18 07:21:06 AM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245785716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.2245785716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.3807155812
Short name T515
Test name
Test status
Simulation time 172605215217 ps
CPU time 436.95 seconds
Started Sep 18 07:06:22 AM UTC 24
Finished Sep 18 07:13:44 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807155812 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.3807155812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1597914493
Short name T489
Test name
Test status
Simulation time 197958935604 ps
CPU time 199.4 seconds
Started Sep 18 07:06:41 AM UTC 24
Finished Sep 18 07:10:04 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597914493 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.1597914493
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.1364679509
Short name T348
Test name
Test status
Simulation time 84214484305 ps
CPU time 651.48 seconds
Started Sep 18 07:07:12 AM UTC 24
Finished Sep 18 07:18:10 AM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364679509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1364679509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.1322105489
Short name T480
Test name
Test status
Simulation time 25196686682 ps
CPU time 51.9 seconds
Started Sep 18 07:06:52 AM UTC 24
Finished Sep 18 07:07:45 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322105489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1322105489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.1345051595
Short name T474
Test name
Test status
Simulation time 4744180251 ps
CPU time 20.27 seconds
Started Sep 18 07:06:49 AM UTC 24
Finished Sep 18 07:07:11 AM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345051595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1345051595
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.264699363
Short name T469
Test name
Test status
Simulation time 5724951444 ps
CPU time 7.05 seconds
Started Sep 18 07:06:07 AM UTC 24
Finished Sep 18 07:06:15 AM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264699363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.264699363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2464635815
Short name T175
Test name
Test status
Simulation time 157074932711 ps
CPU time 34.82 seconds
Started Sep 18 07:07:29 AM UTC 24
Finished Sep 18 07:08:05 AM UTC 24
Peak memory 221652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2464635815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.adc_ctrl_stress_all_with_rand_reset.2464635815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.1860151957
Short name T487
Test name
Test status
Simulation time 533627261 ps
CPU time 1.42 seconds
Started Sep 18 07:09:42 AM UTC 24
Finished Sep 18 07:09:45 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860151957 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1860151957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.252391767
Short name T504
Test name
Test status
Simulation time 163137286837 ps
CPU time 239.66 seconds
Started Sep 18 07:08:14 AM UTC 24
Finished Sep 18 07:12:17 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252391767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.252391767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.3860921760
Short name T501
Test name
Test status
Simulation time 330559324325 ps
CPU time 242.78 seconds
Started Sep 18 07:07:51 AM UTC 24
Finished Sep 18 07:11:57 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860921760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3860921760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2267741357
Short name T492
Test name
Test status
Simulation time 161286843082 ps
CPU time 158.02 seconds
Started Sep 18 07:07:51 AM UTC 24
Finished Sep 18 07:10:32 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267741357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.2267741357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.4233053754
Short name T505
Test name
Test status
Simulation time 325910608368 ps
CPU time 285.47 seconds
Started Sep 18 07:07:39 AM UTC 24
Finished Sep 18 07:12:28 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233053754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4233053754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.2750053525
Short name T491
Test name
Test status
Simulation time 164377002862 ps
CPU time 161.79 seconds
Started Sep 18 07:07:45 AM UTC 24
Finished Sep 18 07:10:30 AM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750053525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.2750053525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.2336241898
Short name T332
Test name
Test status
Simulation time 174006427147 ps
CPU time 588.66 seconds
Started Sep 18 07:07:54 AM UTC 24
Finished Sep 18 07:17:49 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336241898 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.2336241898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2150245143
Short name T732
Test name
Test status
Simulation time 616171419005 ps
CPU time 1837.99 seconds
Started Sep 18 07:08:03 AM UTC 24
Finished Sep 18 07:39:00 AM UTC 24
Peak memory 213416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150245143 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.2150245143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.3344826847
Short name T600
Test name
Test status
Simulation time 113164120631 ps
CPU time 891.34 seconds
Started Sep 18 07:08:59 AM UTC 24
Finished Sep 18 07:24:00 AM UTC 24
Peak memory 213768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344826847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3344826847
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.2403351713
Short name T490
Test name
Test status
Simulation time 40410396492 ps
CPU time 109.77 seconds
Started Sep 18 07:08:30 AM UTC 24
Finished Sep 18 07:10:21 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403351713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2403351713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.1401276983
Short name T483
Test name
Test status
Simulation time 4685229612 ps
CPU time 6.45 seconds
Started Sep 18 07:08:22 AM UTC 24
Finished Sep 18 07:08:29 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401276983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1401276983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.1175540855
Short name T482
Test name
Test status
Simulation time 5716501429 ps
CPU time 23.86 seconds
Started Sep 18 07:07:38 AM UTC 24
Finished Sep 18 07:08:03 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175540855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1175540855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.1250709345
Short name T588
Test name
Test status
Simulation time 138734980631 ps
CPU time 747.31 seconds
Started Sep 18 07:09:22 AM UTC 24
Finished Sep 18 07:21:57 AM UTC 24
Peak memory 221340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250709345 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.1250709345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3198244163
Short name T486
Test name
Test status
Simulation time 10832778421 ps
CPU time 14.02 seconds
Started Sep 18 07:09:06 AM UTC 24
Finished Sep 18 07:09:21 AM UTC 24
Peak memory 210888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3198244163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.adc_ctrl_stress_all_with_rand_reset.3198244163
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.4282388896
Short name T496
Test name
Test status
Simulation time 294945983 ps
CPU time 1.48 seconds
Started Sep 18 07:11:05 AM UTC 24
Finished Sep 18 07:11:08 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282388896 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.4282388896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.2481422995
Short name T548
Test name
Test status
Simulation time 160755990033 ps
CPU time 443.37 seconds
Started Sep 18 07:10:31 AM UTC 24
Finished Sep 18 07:17:59 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481422995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2481422995
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.3838313167
Short name T547
Test name
Test status
Simulation time 170869254410 ps
CPU time 463.79 seconds
Started Sep 18 07:10:01 AM UTC 24
Finished Sep 18 07:17:51 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838313167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3838313167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1415224485
Short name T502
Test name
Test status
Simulation time 498802270415 ps
CPU time 113.58 seconds
Started Sep 18 07:10:04 AM UTC 24
Finished Sep 18 07:12:00 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415224485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.1415224485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.985529683
Short name T511
Test name
Test status
Simulation time 166230324398 ps
CPU time 185.12 seconds
Started Sep 18 07:09:51 AM UTC 24
Finished Sep 18 07:12:59 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985529683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.985529683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.2070276702
Short name T634
Test name
Test status
Simulation time 325956950251 ps
CPU time 1138.34 seconds
Started Sep 18 07:09:52 AM UTC 24
Finished Sep 18 07:29:03 AM UTC 24
Peak memory 213508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070276702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.2070276702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.801641177
Short name T508
Test name
Test status
Simulation time 240750153644 ps
CPU time 139.45 seconds
Started Sep 18 07:10:23 AM UTC 24
Finished Sep 18 07:12:44 AM UTC 24
Peak memory 210912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801641177 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.801641177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.171272688
Short name T610
Test name
Test status
Simulation time 413411118532 ps
CPU time 907.7 seconds
Started Sep 18 07:10:27 AM UTC 24
Finished Sep 18 07:25:43 AM UTC 24
Peak memory 213352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171272688 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.171272688
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.1434371509
Short name T542
Test name
Test status
Simulation time 73229481826 ps
CPU time 359.46 seconds
Started Sep 18 07:10:45 AM UTC 24
Finished Sep 18 07:16:49 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434371509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1434371509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.1154681228
Short name T495
Test name
Test status
Simulation time 28919434338 ps
CPU time 24.56 seconds
Started Sep 18 07:10:39 AM UTC 24
Finished Sep 18 07:11:05 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154681228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1154681228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.3700671757
Short name T493
Test name
Test status
Simulation time 4275805750 ps
CPU time 18.48 seconds
Started Sep 18 07:10:33 AM UTC 24
Finished Sep 18 07:10:52 AM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700671757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3700671757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.2276727408
Short name T488
Test name
Test status
Simulation time 5926213993 ps
CPU time 4.14 seconds
Started Sep 18 07:09:45 AM UTC 24
Finished Sep 18 07:09:50 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276727408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2276727408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.1869749032
Short name T563
Test name
Test status
Simulation time 172656981668 ps
CPU time 481.26 seconds
Started Sep 18 07:10:57 AM UTC 24
Finished Sep 18 07:19:04 AM UTC 24
Peak memory 210692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869749032 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.1869749032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.404515229
Short name T497
Test name
Test status
Simulation time 20214320817 ps
CPU time 17.27 seconds
Started Sep 18 07:10:53 AM UTC 24
Finished Sep 18 07:11:11 AM UTC 24
Peak memory 221060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=404515229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
27.adc_ctrl_stress_all_with_rand_reset.404515229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.3320180559
Short name T506
Test name
Test status
Simulation time 282895472 ps
CPU time 2.05 seconds
Started Sep 18 07:12:32 AM UTC 24
Finished Sep 18 07:12:36 AM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320180559 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3320180559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.4006381381
Short name T552
Test name
Test status
Simulation time 551318794895 ps
CPU time 372.04 seconds
Started Sep 18 07:11:58 AM UTC 24
Finished Sep 18 07:18:14 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006381381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4006381381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.475318946
Short name T631
Test name
Test status
Simulation time 335539792321 ps
CPU time 1022.12 seconds
Started Sep 18 07:11:29 AM UTC 24
Finished Sep 18 07:28:42 AM UTC 24
Peak memory 213624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475318946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.475318946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.3228361623
Short name T525
Test name
Test status
Simulation time 326039802612 ps
CPU time 200.32 seconds
Started Sep 18 07:11:12 AM UTC 24
Finished Sep 18 07:14:35 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228361623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3228361623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.2959774304
Short name T540
Test name
Test status
Simulation time 491043020686 ps
CPU time 311.09 seconds
Started Sep 18 07:11:20 AM UTC 24
Finished Sep 18 07:16:35 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959774304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.2959774304
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.799662565
Short name T572
Test name
Test status
Simulation time 195545551066 ps
CPU time 509.89 seconds
Started Sep 18 07:11:39 AM UTC 24
Finished Sep 18 07:20:14 AM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799662565 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.799662565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.333808416
Short name T341
Test name
Test status
Simulation time 92136168906 ps
CPU time 574.99 seconds
Started Sep 18 07:12:18 AM UTC 24
Finished Sep 18 07:22:00 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333808416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.333808416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.1959060616
Short name T512
Test name
Test status
Simulation time 45358604997 ps
CPU time 60.65 seconds
Started Sep 18 07:12:06 AM UTC 24
Finished Sep 18 07:13:08 AM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959060616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1959060616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.1619271458
Short name T503
Test name
Test status
Simulation time 3230027225 ps
CPU time 2.82 seconds
Started Sep 18 07:12:01 AM UTC 24
Finished Sep 18 07:12:05 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619271458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1619271458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.2048046648
Short name T499
Test name
Test status
Simulation time 6054625901 ps
CPU time 16.55 seconds
Started Sep 18 07:11:08 AM UTC 24
Finished Sep 18 07:11:26 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048046648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2048046648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.4239850596
Short name T298
Test name
Test status
Simulation time 215974722126 ps
CPU time 158.33 seconds
Started Sep 18 07:12:29 AM UTC 24
Finished Sep 18 07:15:10 AM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239850596 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.4239850596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1120899898
Short name T510
Test name
Test status
Simulation time 7919714907 ps
CPU time 26.46 seconds
Started Sep 18 07:12:23 AM UTC 24
Finished Sep 18 07:12:51 AM UTC 24
Peak memory 221384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1120899898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.adc_ctrl_stress_all_with_rand_reset.1120899898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.1442439045
Short name T516
Test name
Test status
Simulation time 415168595 ps
CPU time 2.47 seconds
Started Sep 18 07:13:44 AM UTC 24
Finished Sep 18 07:13:48 AM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442439045 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1442439045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.729992208
Short name T178
Test name
Test status
Simulation time 602242089987 ps
CPU time 142.93 seconds
Started Sep 18 07:13:00 AM UTC 24
Finished Sep 18 07:15:25 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729992208 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.729992208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.3986782157
Short name T300
Test name
Test status
Simulation time 502053032247 ps
CPU time 466.41 seconds
Started Sep 18 07:12:42 AM UTC 24
Finished Sep 18 07:20:34 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986782157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3986782157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.4278608717
Short name T536
Test name
Test status
Simulation time 164705461028 ps
CPU time 220.54 seconds
Started Sep 18 07:12:45 AM UTC 24
Finished Sep 18 07:16:29 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278608717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.4278608717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.641770516
Short name T545
Test name
Test status
Simulation time 159726711125 ps
CPU time 295.37 seconds
Started Sep 18 07:12:38 AM UTC 24
Finished Sep 18 07:17:37 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641770516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.641770516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.2373129982
Short name T560
Test name
Test status
Simulation time 493162771017 ps
CPU time 373.49 seconds
Started Sep 18 07:12:39 AM UTC 24
Finished Sep 18 07:18:57 AM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373129982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.2373129982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.3873935234
Short name T191
Test name
Test status
Simulation time 544472729882 ps
CPU time 307.16 seconds
Started Sep 18 07:12:49 AM UTC 24
Finished Sep 18 07:18:00 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873935234 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.3873935234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1451583423
Short name T567
Test name
Test status
Simulation time 207745708670 ps
CPU time 381.03 seconds
Started Sep 18 07:12:52 AM UTC 24
Finished Sep 18 07:19:18 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451583423 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.1451583423
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.255913854
Short name T586
Test name
Test status
Simulation time 88808944353 ps
CPU time 479.01 seconds
Started Sep 18 07:13:20 AM UTC 24
Finished Sep 18 07:21:24 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255913854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.255913854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.491615655
Short name T528
Test name
Test status
Simulation time 38827785558 ps
CPU time 100.4 seconds
Started Sep 18 07:13:19 AM UTC 24
Finished Sep 18 07:15:01 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491615655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.491615655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.894364913
Short name T513
Test name
Test status
Simulation time 3827128252 ps
CPU time 9.18 seconds
Started Sep 18 07:13:09 AM UTC 24
Finished Sep 18 07:13:19 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894364913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.894364913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.3567414000
Short name T507
Test name
Test status
Simulation time 6086297968 ps
CPU time 4.38 seconds
Started Sep 18 07:12:35 AM UTC 24
Finished Sep 18 07:12:41 AM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567414000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3567414000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.1932587264
Short name T570
Test name
Test status
Simulation time 167885209978 ps
CPU time 366.87 seconds
Started Sep 18 07:13:39 AM UTC 24
Finished Sep 18 07:19:50 AM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932587264 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.1932587264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.436061043
Short name T514
Test name
Test status
Simulation time 1374717217 ps
CPU time 9.1 seconds
Started Sep 18 07:13:28 AM UTC 24
Finished Sep 18 07:13:39 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=436061043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
29.adc_ctrl_stress_all_with_rand_reset.436061043
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.1046093804
Short name T166
Test name
Test status
Simulation time 373831593 ps
CPU time 0.92 seconds
Started Sep 18 06:33:36 AM UTC 24
Finished Sep 18 06:33:38 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046093804 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1046093804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2554646331
Short name T46
Test name
Test status
Simulation time 161909151880 ps
CPU time 153.05 seconds
Started Sep 18 06:32:56 AM UTC 24
Finished Sep 18 06:35:31 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554646331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2554646331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3095098913
Short name T358
Test name
Test status
Simulation time 324844397856 ps
CPU time 457.06 seconds
Started Sep 18 06:32:58 AM UTC 24
Finished Sep 18 06:40:40 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095098913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.3095098913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.3919467528
Short name T35
Test name
Test status
Simulation time 487569641315 ps
CPU time 245.61 seconds
Started Sep 18 06:32:55 AM UTC 24
Finished Sep 18 06:37:04 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919467528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3919467528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2480887257
Short name T197
Test name
Test status
Simulation time 326541718691 ps
CPU time 320.07 seconds
Started Sep 18 06:32:55 AM UTC 24
Finished Sep 18 06:38:19 AM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480887257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.2480887257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.778826553
Short name T15
Test name
Test status
Simulation time 199840828875 ps
CPU time 108.46 seconds
Started Sep 18 06:33:03 AM UTC 24
Finished Sep 18 06:34:53 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778826553 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.778826553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.125619440
Short name T65
Test name
Test status
Simulation time 34511965036 ps
CPU time 27 seconds
Started Sep 18 06:33:15 AM UTC 24
Finished Sep 18 06:33:44 AM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125619440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.125619440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.644262928
Short name T64
Test name
Test status
Simulation time 5388907618 ps
CPU time 9.57 seconds
Started Sep 18 06:33:11 AM UTC 24
Finished Sep 18 06:33:22 AM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644262928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.644262928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.185780222
Short name T83
Test name
Test status
Simulation time 7893219260 ps
CPU time 6.2 seconds
Started Sep 18 06:33:28 AM UTC 24
Finished Sep 18 06:33:35 AM UTC 24
Peak memory 242844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185780222 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.185780222
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.3501547947
Short name T50
Test name
Test status
Simulation time 5853643416 ps
CPU time 6.81 seconds
Started Sep 18 06:32:55 AM UTC 24
Finished Sep 18 06:33:03 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501547947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3501547947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.3094794859
Short name T61
Test name
Test status
Simulation time 125779069178 ps
CPU time 483.79 seconds
Started Sep 18 06:33:25 AM UTC 24
Finished Sep 18 06:41:33 AM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094794859 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.3094794859
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2401709327
Short name T44
Test name
Test status
Simulation time 2556373139 ps
CPU time 22.69 seconds
Started Sep 18 06:33:23 AM UTC 24
Finished Sep 18 06:33:46 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2401709327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.adc_ctrl_stress_all_with_rand_reset.2401709327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.2255492364
Short name T526
Test name
Test status
Simulation time 363710095 ps
CPU time 2.11 seconds
Started Sep 18 07:14:44 AM UTC 24
Finished Sep 18 07:14:47 AM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255492364 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2255492364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.2095150454
Short name T556
Test name
Test status
Simulation time 325835136806 ps
CPU time 263.18 seconds
Started Sep 18 07:14:10 AM UTC 24
Finished Sep 18 07:18:37 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095150454 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.2095150454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.1140234957
Short name T714
Test name
Test status
Simulation time 496520670413 ps
CPU time 1365.11 seconds
Started Sep 18 07:14:11 AM UTC 24
Finished Sep 18 07:37:10 AM UTC 24
Peak memory 213448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140234957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1140234957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.2848473500
Short name T538
Test name
Test status
Simulation time 165449502374 ps
CPU time 152.66 seconds
Started Sep 18 07:13:55 AM UTC 24
Finished Sep 18 07:16:31 AM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848473500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2848473500
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2074789787
Short name T625
Test name
Test status
Simulation time 331288902101 ps
CPU time 789.83 seconds
Started Sep 18 07:14:01 AM UTC 24
Finished Sep 18 07:27:19 AM UTC 24
Peak memory 213364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074789787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.2074789787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.1727652603
Short name T533
Test name
Test status
Simulation time 163302765374 ps
CPU time 102.99 seconds
Started Sep 18 07:13:49 AM UTC 24
Finished Sep 18 07:15:34 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727652603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1727652603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.231410256
Short name T574
Test name
Test status
Simulation time 493237113816 ps
CPU time 404.87 seconds
Started Sep 18 07:13:49 AM UTC 24
Finished Sep 18 07:20:39 AM UTC 24
Peak memory 211032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231410256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.231410256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.1026189941
Short name T544
Test name
Test status
Simulation time 185031009023 ps
CPU time 187.41 seconds
Started Sep 18 07:14:06 AM UTC 24
Finished Sep 18 07:17:16 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026189941 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.1026189941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1087041679
Short name T568
Test name
Test status
Simulation time 398089550698 ps
CPU time 308.95 seconds
Started Sep 18 07:14:09 AM UTC 24
Finished Sep 18 07:19:22 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087041679 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.1087041679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.3168172225
Short name T350
Test name
Test status
Simulation time 138543563280 ps
CPU time 597.69 seconds
Started Sep 18 07:14:22 AM UTC 24
Finished Sep 18 07:24:25 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168172225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3168172225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.360560140
Short name T531
Test name
Test status
Simulation time 33225828471 ps
CPU time 68.25 seconds
Started Sep 18 07:14:19 AM UTC 24
Finished Sep 18 07:15:29 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360560140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.360560140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.3100206475
Short name T524
Test name
Test status
Simulation time 4456214352 ps
CPU time 5.61 seconds
Started Sep 18 07:14:14 AM UTC 24
Finished Sep 18 07:14:21 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100206475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3100206475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.3254999564
Short name T520
Test name
Test status
Simulation time 6139377570 ps
CPU time 21.47 seconds
Started Sep 18 07:13:46 AM UTC 24
Finished Sep 18 07:14:08 AM UTC 24
Peak memory 210520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254999564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3254999564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.44697572
Short name T537
Test name
Test status
Simulation time 291586705 ps
CPU time 2.02 seconds
Started Sep 18 07:16:27 AM UTC 24
Finished Sep 18 07:16:30 AM UTC 24
Peak memory 210648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44697572 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.44697572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.4272775497
Short name T627
Test name
Test status
Simulation time 512852992557 ps
CPU time 707.13 seconds
Started Sep 18 07:15:28 AM UTC 24
Finished Sep 18 07:27:24 AM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272775497 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.4272775497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.2125306825
Short name T226
Test name
Test status
Simulation time 189953916761 ps
CPU time 143.45 seconds
Started Sep 18 07:15:30 AM UTC 24
Finished Sep 18 07:17:56 AM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125306825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2125306825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.4023611366
Short name T313
Test name
Test status
Simulation time 488129439557 ps
CPU time 946.22 seconds
Started Sep 18 07:15:02 AM UTC 24
Finished Sep 18 07:30:58 AM UTC 24
Peak memory 213692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023611366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4023611366
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3042992035
Short name T711
Test name
Test status
Simulation time 488139286789 ps
CPU time 1300.97 seconds
Started Sep 18 07:15:05 AM UTC 24
Finished Sep 18 07:36:59 AM UTC 24
Peak memory 213748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042992035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.3042992035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.2221727067
Short name T744
Test name
Test status
Simulation time 484570964589 ps
CPU time 1511.79 seconds
Started Sep 18 07:14:58 AM UTC 24
Finished Sep 18 07:40:25 AM UTC 24
Peak memory 213408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221727067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.2221727067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.2264232413
Short name T336
Test name
Test status
Simulation time 350190757507 ps
CPU time 298.23 seconds
Started Sep 18 07:15:11 AM UTC 24
Finished Sep 18 07:20:13 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264232413 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.2264232413
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3286130689
Short name T558
Test name
Test status
Simulation time 192038962592 ps
CPU time 191.61 seconds
Started Sep 18 07:15:26 AM UTC 24
Finished Sep 18 07:18:41 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286130689 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.3286130689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.1061616403
Short name T220
Test name
Test status
Simulation time 70305980571 ps
CPU time 425.1 seconds
Started Sep 18 07:15:40 AM UTC 24
Finished Sep 18 07:22:50 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061616403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1061616403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.4099057970
Short name T543
Test name
Test status
Simulation time 26911175423 ps
CPU time 95.1 seconds
Started Sep 18 07:15:35 AM UTC 24
Finished Sep 18 07:17:12 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099057970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4099057970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.2234894683
Short name T534
Test name
Test status
Simulation time 4379653882 ps
CPU time 5.93 seconds
Started Sep 18 07:15:31 AM UTC 24
Finished Sep 18 07:15:39 AM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234894683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2234894683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.3513722507
Short name T527
Test name
Test status
Simulation time 5719640854 ps
CPU time 12.52 seconds
Started Sep 18 07:14:44 AM UTC 24
Finished Sep 18 07:14:57 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513722507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3513722507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.1158866402
Short name T716
Test name
Test status
Simulation time 1261900807787 ps
CPU time 1251.31 seconds
Started Sep 18 07:16:15 AM UTC 24
Finished Sep 18 07:37:18 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158866402 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.1158866402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1685188181
Short name T25
Test name
Test status
Simulation time 7389765358 ps
CPU time 16.68 seconds
Started Sep 18 07:16:09 AM UTC 24
Finished Sep 18 07:16:27 AM UTC 24
Peak memory 221076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1685188181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.adc_ctrl_stress_all_with_rand_reset.1685188181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.2366906705
Short name T549
Test name
Test status
Simulation time 382779442 ps
CPU time 1.96 seconds
Started Sep 18 07:17:57 AM UTC 24
Finished Sep 18 07:18:00 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366906705 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2366906705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.131357404
Short name T665
Test name
Test status
Simulation time 599501519042 ps
CPU time 884.77 seconds
Started Sep 18 07:17:12 AM UTC 24
Finished Sep 18 07:32:07 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131357404 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.131357404
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.1278262369
Short name T192
Test name
Test status
Simulation time 542582276977 ps
CPU time 242.81 seconds
Started Sep 18 07:17:18 AM UTC 24
Finished Sep 18 07:21:24 AM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278262369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1278262369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4187992054
Short name T608
Test name
Test status
Simulation time 165297618975 ps
CPU time 484.17 seconds
Started Sep 18 07:16:36 AM UTC 24
Finished Sep 18 07:24:46 AM UTC 24
Peak memory 211032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187992054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.4187992054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.1782127128
Short name T329
Test name
Test status
Simulation time 488608168975 ps
CPU time 310.81 seconds
Started Sep 18 07:16:31 AM UTC 24
Finished Sep 18 07:21:46 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782127128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1782127128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.407333823
Short name T637
Test name
Test status
Simulation time 487355708436 ps
CPU time 755.93 seconds
Started Sep 18 07:16:31 AM UTC 24
Finished Sep 18 07:29:15 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407333823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.407333823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.2552174617
Short name T285
Test name
Test status
Simulation time 179506530930 ps
CPU time 136.12 seconds
Started Sep 18 07:16:37 AM UTC 24
Finished Sep 18 07:18:56 AM UTC 24
Peak memory 210916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552174617 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.2552174617
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3646725957
Short name T779
Test name
Test status
Simulation time 600212610309 ps
CPU time 1820.62 seconds
Started Sep 18 07:16:49 AM UTC 24
Finished Sep 18 07:47:27 AM UTC 24
Peak memory 213416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646725957 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.3646725957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.3247936526
Short name T674
Test name
Test status
Simulation time 137238350533 ps
CPU time 889.52 seconds
Started Sep 18 07:17:40 AM UTC 24
Finished Sep 18 07:32:38 AM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247936526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3247936526
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.2852285466
Short name T551
Test name
Test status
Simulation time 37686072474 ps
CPU time 32.49 seconds
Started Sep 18 07:17:38 AM UTC 24
Finished Sep 18 07:18:11 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852285466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2852285466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.994527186
Short name T546
Test name
Test status
Simulation time 5480582014 ps
CPU time 9.82 seconds
Started Sep 18 07:17:29 AM UTC 24
Finished Sep 18 07:17:39 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994527186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.994527186
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.2196859652
Short name T539
Test name
Test status
Simulation time 5911432013 ps
CPU time 3.74 seconds
Started Sep 18 07:16:29 AM UTC 24
Finished Sep 18 07:16:34 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196859652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2196859652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.3130494526
Short name T673
Test name
Test status
Simulation time 170317250125 ps
CPU time 875.79 seconds
Started Sep 18 07:17:52 AM UTC 24
Finished Sep 18 07:32:36 AM UTC 24
Peak memory 221260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130494526 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.3130494526
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1257106529
Short name T554
Test name
Test status
Simulation time 6470042324 ps
CPU time 36.14 seconds
Started Sep 18 07:17:50 AM UTC 24
Finished Sep 18 07:18:27 AM UTC 24
Peak memory 221400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1257106529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.adc_ctrl_stress_all_with_rand_reset.1257106529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.2397472718
Short name T559
Test name
Test status
Simulation time 436412519 ps
CPU time 1.06 seconds
Started Sep 18 07:18:52 AM UTC 24
Finished Sep 18 07:18:54 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397472718 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2397472718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.1008298339
Short name T577
Test name
Test status
Simulation time 161826729863 ps
CPU time 150.36 seconds
Started Sep 18 07:18:28 AM UTC 24
Finished Sep 18 07:21:01 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008298339 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.1008298339
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.515682919
Short name T335
Test name
Test status
Simulation time 159554914785 ps
CPU time 278.44 seconds
Started Sep 18 07:18:11 AM UTC 24
Finished Sep 18 07:22:53 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515682919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.515682919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2936681032
Short name T683
Test name
Test status
Simulation time 334552895821 ps
CPU time 914.49 seconds
Started Sep 18 07:18:12 AM UTC 24
Finished Sep 18 07:33:36 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936681032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.2936681032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.4102483566
Short name T632
Test name
Test status
Simulation time 489394446511 ps
CPU time 638.39 seconds
Started Sep 18 07:18:01 AM UTC 24
Finished Sep 18 07:28:46 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102483566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4102483566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.4266878969
Short name T705
Test name
Test status
Simulation time 492244116142 ps
CPU time 1082.7 seconds
Started Sep 18 07:18:01 AM UTC 24
Finished Sep 18 07:36:13 AM UTC 24
Peak memory 213552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266878969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.4266878969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.329655591
Short name T759
Test name
Test status
Simulation time 527097498994 ps
CPU time 1432.3 seconds
Started Sep 18 07:18:12 AM UTC 24
Finished Sep 18 07:42:18 AM UTC 24
Peak memory 213712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329655591 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.329655591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1768194292
Short name T566
Test name
Test status
Simulation time 194503389578 ps
CPU time 57.5 seconds
Started Sep 18 07:18:15 AM UTC 24
Finished Sep 18 07:19:14 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768194292 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.1768194292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.2151801634
Short name T342
Test name
Test status
Simulation time 100951840623 ps
CPU time 433.38 seconds
Started Sep 18 07:18:39 AM UTC 24
Finished Sep 18 07:25:57 AM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151801634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2151801634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.1794267287
Short name T562
Test name
Test status
Simulation time 25645759622 ps
CPU time 23.9 seconds
Started Sep 18 07:18:38 AM UTC 24
Finished Sep 18 07:19:03 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794267287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1794267287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.1078860997
Short name T557
Test name
Test status
Simulation time 3347319345 ps
CPU time 8.15 seconds
Started Sep 18 07:18:29 AM UTC 24
Finished Sep 18 07:18:38 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078860997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1078860997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.1535907973
Short name T553
Test name
Test status
Simulation time 6023563623 ps
CPU time 26.01 seconds
Started Sep 18 07:18:00 AM UTC 24
Finished Sep 18 07:18:27 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535907973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1535907973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.3086543107
Short name T576
Test name
Test status
Simulation time 195263921165 ps
CPU time 133.96 seconds
Started Sep 18 07:18:42 AM UTC 24
Finished Sep 18 07:20:58 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086543107 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.3086543107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.466521821
Short name T328
Test name
Test status
Simulation time 109598084538 ps
CPU time 18.41 seconds
Started Sep 18 07:18:40 AM UTC 24
Finished Sep 18 07:18:59 AM UTC 24
Peak memory 221596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=466521821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
33.adc_ctrl_stress_all_with_rand_reset.466521821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.828542761
Short name T571
Test name
Test status
Simulation time 291690721 ps
CPU time 1.21 seconds
Started Sep 18 07:19:51 AM UTC 24
Finished Sep 18 07:19:53 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828542761 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.828542761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.2850843317
Short name T591
Test name
Test status
Simulation time 342688257802 ps
CPU time 191.36 seconds
Started Sep 18 07:19:08 AM UTC 24
Finished Sep 18 07:22:22 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850843317 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.2850843317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.1966599593
Short name T584
Test name
Test status
Simulation time 184938386954 ps
CPU time 124.18 seconds
Started Sep 18 07:19:14 AM UTC 24
Finished Sep 18 07:21:21 AM UTC 24
Peak memory 211112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966599593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1966599593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.691907877
Short name T643
Test name
Test status
Simulation time 481567168903 ps
CPU time 629.2 seconds
Started Sep 18 07:19:00 AM UTC 24
Finished Sep 18 07:29:36 AM UTC 24
Peak memory 210888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691907877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.691907877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3075146937
Short name T593
Test name
Test status
Simulation time 335092455549 ps
CPU time 208.73 seconds
Started Sep 18 07:19:01 AM UTC 24
Finished Sep 18 07:22:33 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075146937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.3075146937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.935579641
Short name T615
Test name
Test status
Simulation time 326424999155 ps
CPU time 441.37 seconds
Started Sep 18 07:18:56 AM UTC 24
Finished Sep 18 07:26:22 AM UTC 24
Peak memory 210852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935579641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.935579641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.759017991
Short name T601
Test name
Test status
Simulation time 168147482113 ps
CPU time 301.26 seconds
Started Sep 18 07:18:57 AM UTC 24
Finished Sep 18 07:24:02 AM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759017991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.759017991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.3001147855
Short name T603
Test name
Test status
Simulation time 378809222354 ps
CPU time 317.41 seconds
Started Sep 18 07:19:03 AM UTC 24
Finished Sep 18 07:24:25 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001147855 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.3001147855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2761853484
Short name T694
Test name
Test status
Simulation time 396245893380 ps
CPU time 922.33 seconds
Started Sep 18 07:19:04 AM UTC 24
Finished Sep 18 07:34:36 AM UTC 24
Peak memory 210680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761853484 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.2761853484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.3238611122
Short name T645
Test name
Test status
Simulation time 131743444849 ps
CPU time 619.37 seconds
Started Sep 18 07:19:23 AM UTC 24
Finished Sep 18 07:29:48 AM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238611122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3238611122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.1511147510
Short name T580
Test name
Test status
Simulation time 29338633322 ps
CPU time 110.49 seconds
Started Sep 18 07:19:19 AM UTC 24
Finished Sep 18 07:21:11 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511147510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1511147510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.4258907734
Short name T569
Test name
Test status
Simulation time 4516634346 ps
CPU time 9.96 seconds
Started Sep 18 07:19:16 AM UTC 24
Finished Sep 18 07:19:27 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258907734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4258907734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.3788607929
Short name T561
Test name
Test status
Simulation time 6023388764 ps
CPU time 4.16 seconds
Started Sep 18 07:18:55 AM UTC 24
Finished Sep 18 07:19:00 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788607929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3788607929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3953507007
Short name T216
Test name
Test status
Simulation time 636191853104 ps
CPU time 1078.87 seconds
Started Sep 18 07:19:47 AM UTC 24
Finished Sep 18 07:37:56 AM UTC 24
Peak memory 213972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953507007 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.3953507007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.578742691
Short name T26
Test name
Test status
Simulation time 4174146460 ps
CPU time 17.45 seconds
Started Sep 18 07:19:28 AM UTC 24
Finished Sep 18 07:19:46 AM UTC 24
Peak memory 210900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=578742691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
34.adc_ctrl_stress_all_with_rand_reset.578742691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.2242596680
Short name T583
Test name
Test status
Simulation time 532791330 ps
CPU time 1.36 seconds
Started Sep 18 07:21:13 AM UTC 24
Finished Sep 18 07:21:16 AM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242596680 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2242596680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.2803232675
Short name T310
Test name
Test status
Simulation time 526113318986 ps
CPU time 666.44 seconds
Started Sep 18 07:20:41 AM UTC 24
Finished Sep 18 07:31:54 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803232675 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.2803232675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.3585530201
Short name T279
Test name
Test status
Simulation time 538099029987 ps
CPU time 1547.83 seconds
Started Sep 18 07:20:59 AM UTC 24
Finished Sep 18 07:47:02 AM UTC 24
Peak memory 213640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585530201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3585530201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.3532884859
Short name T592
Test name
Test status
Simulation time 164688596431 ps
CPU time 125.71 seconds
Started Sep 18 07:20:18 AM UTC 24
Finished Sep 18 07:22:26 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532884859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3532884859
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.240421962
Short name T596
Test name
Test status
Simulation time 167483319917 ps
CPU time 142.92 seconds
Started Sep 18 07:20:35 AM UTC 24
Finished Sep 18 07:23:00 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240421962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.240421962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.2906578279
Short name T660
Test name
Test status
Simulation time 493396195448 ps
CPU time 675.73 seconds
Started Sep 18 07:20:14 AM UTC 24
Finished Sep 18 07:31:37 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906578279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2906578279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.1504626548
Short name T611
Test name
Test status
Simulation time 484263594996 ps
CPU time 334.88 seconds
Started Sep 18 07:20:15 AM UTC 24
Finished Sep 18 07:25:54 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504626548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.1504626548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.2134927604
Short name T598
Test name
Test status
Simulation time 197782778485 ps
CPU time 164.76 seconds
Started Sep 18 07:20:35 AM UTC 24
Finished Sep 18 07:23:22 AM UTC 24
Peak memory 210684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134927604 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.2134927604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.593932961
Short name T589
Test name
Test status
Simulation time 197130877875 ps
CPU time 85.84 seconds
Started Sep 18 07:20:40 AM UTC 24
Finished Sep 18 07:22:07 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593932961 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.593932961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.3360925124
Short name T618
Test name
Test status
Simulation time 80073502495 ps
CPU time 335.92 seconds
Started Sep 18 07:21:07 AM UTC 24
Finished Sep 18 07:26:46 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360925124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3360925124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.3775205388
Short name T581
Test name
Test status
Simulation time 29969640499 ps
CPU time 9.22 seconds
Started Sep 18 07:21:02 AM UTC 24
Finished Sep 18 07:21:12 AM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775205388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3775205388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.778677442
Short name T579
Test name
Test status
Simulation time 5171516676 ps
CPU time 11.2 seconds
Started Sep 18 07:20:59 AM UTC 24
Finished Sep 18 07:21:11 AM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778677442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.778677442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.3863390410
Short name T573
Test name
Test status
Simulation time 5652875915 ps
CPU time 22.44 seconds
Started Sep 18 07:19:54 AM UTC 24
Finished Sep 18 07:20:18 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863390410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3863390410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.1866634912
Short name T657
Test name
Test status
Simulation time 1231010567521 ps
CPU time 605.79 seconds
Started Sep 18 07:21:12 AM UTC 24
Finished Sep 18 07:31:24 AM UTC 24
Peak memory 223580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866634912 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.1866634912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3725104502
Short name T587
Test name
Test status
Simulation time 57476894783 ps
CPU time 34.52 seconds
Started Sep 18 07:21:12 AM UTC 24
Finished Sep 18 07:21:48 AM UTC 24
Peak memory 221388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3725104502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.adc_ctrl_stress_all_with_rand_reset.3725104502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.2378763338
Short name T594
Test name
Test status
Simulation time 378326146 ps
CPU time 1.65 seconds
Started Sep 18 07:22:33 AM UTC 24
Finished Sep 18 07:22:36 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378763338 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2378763338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.4076538959
Short name T297
Test name
Test status
Simulation time 495131674150 ps
CPU time 299.25 seconds
Started Sep 18 07:21:49 AM UTC 24
Finished Sep 18 07:26:52 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076538959 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.4076538959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.2681066551
Short name T648
Test name
Test status
Simulation time 166423035151 ps
CPU time 489.86 seconds
Started Sep 18 07:21:58 AM UTC 24
Finished Sep 18 07:30:13 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681066551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2681066551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.715211627
Short name T288
Test name
Test status
Simulation time 488806229494 ps
CPU time 310.11 seconds
Started Sep 18 07:21:23 AM UTC 24
Finished Sep 18 07:26:36 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715211627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.715211627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2705383743
Short name T651
Test name
Test status
Simulation time 164721949918 ps
CPU time 566.12 seconds
Started Sep 18 07:21:25 AM UTC 24
Finished Sep 18 07:30:57 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705383743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.2705383743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.2818921269
Short name T597
Test name
Test status
Simulation time 166545312296 ps
CPU time 108.59 seconds
Started Sep 18 07:21:21 AM UTC 24
Finished Sep 18 07:23:12 AM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818921269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.2818921269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3113038159
Short name T689
Test name
Test status
Simulation time 197137788225 ps
CPU time 723.93 seconds
Started Sep 18 07:21:47 AM UTC 24
Finished Sep 18 07:33:59 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113038159 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.3113038159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.2715556159
Short name T676
Test name
Test status
Simulation time 96873146385 ps
CPU time 629.52 seconds
Started Sep 18 07:22:18 AM UTC 24
Finished Sep 18 07:32:55 AM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715556159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2715556159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.640439934
Short name T607
Test name
Test status
Simulation time 38564845740 ps
CPU time 146.36 seconds
Started Sep 18 07:22:08 AM UTC 24
Finished Sep 18 07:24:37 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640439934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.640439934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.4085667009
Short name T590
Test name
Test status
Simulation time 5072448204 ps
CPU time 15.1 seconds
Started Sep 18 07:22:01 AM UTC 24
Finished Sep 18 07:22:17 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085667009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.4085667009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.3183465557
Short name T585
Test name
Test status
Simulation time 5802038437 ps
CPU time 7.37 seconds
Started Sep 18 07:21:13 AM UTC 24
Finished Sep 18 07:21:22 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183465557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3183465557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.718926282
Short name T619
Test name
Test status
Simulation time 87396429736 ps
CPU time 259.81 seconds
Started Sep 18 07:22:26 AM UTC 24
Finished Sep 18 07:26:49 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718926282 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.718926282
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1420276166
Short name T27
Test name
Test status
Simulation time 20678270771 ps
CPU time 36.91 seconds
Started Sep 18 07:22:23 AM UTC 24
Finished Sep 18 07:23:01 AM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1420276166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.adc_ctrl_stress_all_with_rand_reset.1420276166
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.2389467671
Short name T604
Test name
Test status
Simulation time 321162889 ps
CPU time 2.13 seconds
Started Sep 18 07:24:26 AM UTC 24
Finished Sep 18 07:24:29 AM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389467671 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2389467671
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.3150215801
Short name T764
Test name
Test status
Simulation time 487851795247 ps
CPU time 1248.04 seconds
Started Sep 18 07:23:23 AM UTC 24
Finished Sep 18 07:44:24 AM UTC 24
Peak memory 213636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150215801 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.3150215801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.1439491921
Short name T617
Test name
Test status
Simulation time 340481805957 ps
CPU time 181.64 seconds
Started Sep 18 07:23:23 AM UTC 24
Finished Sep 18 07:26:27 AM UTC 24
Peak memory 211052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439491921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1439491921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.779818728
Short name T623
Test name
Test status
Simulation time 165464457091 ps
CPU time 260.2 seconds
Started Sep 18 07:22:54 AM UTC 24
Finished Sep 18 07:27:17 AM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779818728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.779818728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3616044909
Short name T609
Test name
Test status
Simulation time 490402632918 ps
CPU time 122.23 seconds
Started Sep 18 07:23:01 AM UTC 24
Finished Sep 18 07:25:05 AM UTC 24
Peak memory 211032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616044909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.3616044909
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.54254903
Short name T633
Test name
Test status
Simulation time 326000480539 ps
CPU time 366.16 seconds
Started Sep 18 07:22:52 AM UTC 24
Finished Sep 18 07:29:02 AM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54254903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.54254903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.2622745370
Short name T661
Test name
Test status
Simulation time 168759519714 ps
CPU time 522.85 seconds
Started Sep 18 07:22:52 AM UTC 24
Finished Sep 18 07:31:40 AM UTC 24
Peak memory 211024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622745370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.2622745370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.2681101554
Short name T195
Test name
Test status
Simulation time 606549897136 ps
CPU time 134.53 seconds
Started Sep 18 07:23:02 AM UTC 24
Finished Sep 18 07:25:19 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681101554 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.2681101554
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3712114442
Short name T636
Test name
Test status
Simulation time 414262475215 ps
CPU time 355.45 seconds
Started Sep 18 07:23:13 AM UTC 24
Finished Sep 18 07:29:13 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712114442 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.3712114442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.2489542255
Short name T658
Test name
Test status
Simulation time 104389601619 ps
CPU time 437.29 seconds
Started Sep 18 07:24:02 AM UTC 24
Finished Sep 18 07:31:24 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489542255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2489542255
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.2204671136
Short name T612
Test name
Test status
Simulation time 42113640574 ps
CPU time 120.35 seconds
Started Sep 18 07:24:01 AM UTC 24
Finished Sep 18 07:26:04 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204671136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2204671136
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.255553005
Short name T602
Test name
Test status
Simulation time 5524891638 ps
CPU time 11.42 seconds
Started Sep 18 07:23:57 AM UTC 24
Finished Sep 18 07:24:11 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255553005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.255553005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.3738052972
Short name T595
Test name
Test status
Simulation time 6078057142 ps
CPU time 13.09 seconds
Started Sep 18 07:22:36 AM UTC 24
Finished Sep 18 07:22:51 AM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738052972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3738052972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1627534256
Short name T606
Test name
Test status
Simulation time 4925728483 ps
CPU time 22.88 seconds
Started Sep 18 07:24:12 AM UTC 24
Finished Sep 18 07:24:36 AM UTC 24
Peak memory 221016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1627534256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.adc_ctrl_stress_all_with_rand_reset.1627534256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.3736999892
Short name T614
Test name
Test status
Simulation time 339162194 ps
CPU time 2.33 seconds
Started Sep 18 07:26:14 AM UTC 24
Finished Sep 18 07:26:17 AM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736999892 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3736999892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.2981110176
Short name T281
Test name
Test status
Simulation time 600874943668 ps
CPU time 249.95 seconds
Started Sep 18 07:25:19 AM UTC 24
Finished Sep 18 07:29:32 AM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981110176 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.2981110176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.438053349
Short name T621
Test name
Test status
Simulation time 163911372874 ps
CPU time 90.48 seconds
Started Sep 18 07:25:44 AM UTC 24
Finished Sep 18 07:27:16 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438053349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.438053349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.4279741192
Short name T659
Test name
Test status
Simulation time 330773956406 ps
CPU time 410.72 seconds
Started Sep 18 07:24:37 AM UTC 24
Finished Sep 18 07:31:32 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279741192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4279741192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3255447583
Short name T724
Test name
Test status
Simulation time 331742682661 ps
CPU time 795.76 seconds
Started Sep 18 07:24:38 AM UTC 24
Finished Sep 18 07:38:02 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255447583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.3255447583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.3970258867
Short name T664
Test name
Test status
Simulation time 495816547008 ps
CPU time 445.59 seconds
Started Sep 18 07:24:35 AM UTC 24
Finished Sep 18 07:32:05 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970258867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.3970258867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.4192299690
Short name T695
Test name
Test status
Simulation time 181838786675 ps
CPU time 583.6 seconds
Started Sep 18 07:24:46 AM UTC 24
Finished Sep 18 07:34:36 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192299690 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.4192299690
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3004553484
Short name T792
Test name
Test status
Simulation time 603669911830 ps
CPU time 1610.94 seconds
Started Sep 18 07:25:06 AM UTC 24
Finished Sep 18 07:52:12 AM UTC 24
Peak memory 213292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004553484 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.3004553484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.1652608195
Short name T686
Test name
Test status
Simulation time 127420117754 ps
CPU time 466.35 seconds
Started Sep 18 07:26:00 AM UTC 24
Finished Sep 18 07:33:51 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652608195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1652608195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.4083578404
Short name T629
Test name
Test status
Simulation time 34427816641 ps
CPU time 92.02 seconds
Started Sep 18 07:25:59 AM UTC 24
Finished Sep 18 07:27:33 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083578404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4083578404
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.2270838453
Short name T613
Test name
Test status
Simulation time 3337237741 ps
CPU time 14.82 seconds
Started Sep 18 07:25:55 AM UTC 24
Finished Sep 18 07:26:11 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270838453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2270838453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.1680945007
Short name T605
Test name
Test status
Simulation time 5808711902 ps
CPU time 7.77 seconds
Started Sep 18 07:24:26 AM UTC 24
Finished Sep 18 07:24:34 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680945007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1680945007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.622073582
Short name T761
Test name
Test status
Simulation time 361616637876 ps
CPU time 973.09 seconds
Started Sep 18 07:26:11 AM UTC 24
Finished Sep 18 07:42:34 AM UTC 24
Peak memory 213684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622073582 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.622073582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2879963320
Short name T28
Test name
Test status
Simulation time 1736351793 ps
CPU time 8.48 seconds
Started Sep 18 07:26:04 AM UTC 24
Finished Sep 18 07:26:14 AM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2879963320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.adc_ctrl_stress_all_with_rand_reset.2879963320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.861137826
Short name T626
Test name
Test status
Simulation time 443182643 ps
CPU time 2.3 seconds
Started Sep 18 07:27:20 AM UTC 24
Finished Sep 18 07:27:23 AM UTC 24
Peak memory 210640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861137826 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.861137826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.2602095060
Short name T725
Test name
Test status
Simulation time 364671761371 ps
CPU time 667.27 seconds
Started Sep 18 07:26:51 AM UTC 24
Finished Sep 18 07:38:05 AM UTC 24
Peak memory 210876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602095060 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.2602095060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.527083402
Short name T278
Test name
Test status
Simulation time 502457903104 ps
CPU time 573.54 seconds
Started Sep 18 07:26:53 AM UTC 24
Finished Sep 18 07:36:32 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527083402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.527083402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.2659176569
Short name T719
Test name
Test status
Simulation time 324127780922 ps
CPU time 647.43 seconds
Started Sep 18 07:26:28 AM UTC 24
Finished Sep 18 07:37:22 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659176569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2659176569
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1758010047
Short name T649
Test name
Test status
Simulation time 489115952511 ps
CPU time 247.18 seconds
Started Sep 18 07:26:38 AM UTC 24
Finished Sep 18 07:30:48 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758010047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.1758010047
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.867042625
Short name T319
Test name
Test status
Simulation time 163862562901 ps
CPU time 628.25 seconds
Started Sep 18 07:26:23 AM UTC 24
Finished Sep 18 07:36:59 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867042625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.867042625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.1251679925
Short name T654
Test name
Test status
Simulation time 331759471535 ps
CPU time 280.2 seconds
Started Sep 18 07:26:26 AM UTC 24
Finished Sep 18 07:31:10 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251679925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.1251679925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.4105132026
Short name T642
Test name
Test status
Simulation time 184610562607 ps
CPU time 170.19 seconds
Started Sep 18 07:26:42 AM UTC 24
Finished Sep 18 07:29:34 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105132026 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.4105132026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.147137290
Short name T650
Test name
Test status
Simulation time 196231960733 ps
CPU time 242.16 seconds
Started Sep 18 07:26:47 AM UTC 24
Finished Sep 18 07:30:52 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147137290 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.147137290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.3349503626
Short name T735
Test name
Test status
Simulation time 107431280453 ps
CPU time 725.85 seconds
Started Sep 18 07:27:18 AM UTC 24
Finished Sep 18 07:39:31 AM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349503626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3349503626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.3925257200
Short name T630
Test name
Test status
Simulation time 42640362202 ps
CPU time 30.01 seconds
Started Sep 18 07:27:17 AM UTC 24
Finished Sep 18 07:27:48 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925257200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3925257200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.1744246187
Short name T622
Test name
Test status
Simulation time 4818728719 ps
CPU time 20.9 seconds
Started Sep 18 07:26:55 AM UTC 24
Finished Sep 18 07:27:17 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744246187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1744246187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.2433148764
Short name T616
Test name
Test status
Simulation time 5925112850 ps
CPU time 6.59 seconds
Started Sep 18 07:26:18 AM UTC 24
Finished Sep 18 07:26:26 AM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433148764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2433148764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.2545005673
Short name T762
Test name
Test status
Simulation time 349659602879 ps
CPU time 954.8 seconds
Started Sep 18 07:27:19 AM UTC 24
Finished Sep 18 07:43:24 AM UTC 24
Peak memory 213300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545005673 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.2545005673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.62148287
Short name T353
Test name
Test status
Simulation time 419307073 ps
CPU time 1.31 seconds
Started Sep 18 06:35:01 AM UTC 24
Finished Sep 18 06:35:03 AM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62148287 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.62148287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.62541490
Short name T149
Test name
Test status
Simulation time 330540279829 ps
CPU time 459.95 seconds
Started Sep 18 06:33:44 AM UTC 24
Finished Sep 18 06:41:30 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62541490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.62541490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3348821788
Short name T391
Test name
Test status
Simulation time 330691671825 ps
CPU time 981.46 seconds
Started Sep 18 06:33:44 AM UTC 24
Finished Sep 18 06:50:16 AM UTC 24
Peak memory 213772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348821788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.3348821788
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.2412994262
Short name T152
Test name
Test status
Simulation time 165771338327 ps
CPU time 134.47 seconds
Started Sep 18 06:33:39 AM UTC 24
Finished Sep 18 06:35:56 AM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412994262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2412994262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.680429937
Short name T34
Test name
Test status
Simulation time 163971572560 ps
CPU time 197.38 seconds
Started Sep 18 06:33:41 AM UTC 24
Finished Sep 18 06:37:01 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680429937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.680429937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2747280411
Short name T423
Test name
Test status
Simulation time 593744130687 ps
CPU time 1332.38 seconds
Started Sep 18 06:34:05 AM UTC 24
Finished Sep 18 06:56:31 AM UTC 24
Peak memory 213284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747280411 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.2747280411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.2434987557
Short name T59
Test name
Test status
Simulation time 102466600337 ps
CPU time 394.66 seconds
Started Sep 18 06:34:27 AM UTC 24
Finished Sep 18 06:41:05 AM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434987557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2434987557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.3389466735
Short name T352
Test name
Test status
Simulation time 35345628207 ps
CPU time 36.52 seconds
Started Sep 18 06:34:24 AM UTC 24
Finished Sep 18 06:35:02 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389466735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3389466735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1777460753
Short name T167
Test name
Test status
Simulation time 3686327958 ps
CPU time 2.21 seconds
Started Sep 18 06:34:20 AM UTC 24
Finished Sep 18 06:34:23 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777460753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1777460753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.967057441
Short name T84
Test name
Test status
Simulation time 7881160500 ps
CPU time 30.73 seconds
Started Sep 18 06:34:57 AM UTC 24
Finished Sep 18 06:35:29 AM UTC 24
Peak memory 242844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967057441 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.967057441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.604128591
Short name T110
Test name
Test status
Simulation time 5976762704 ps
CPU time 26.96 seconds
Started Sep 18 06:33:36 AM UTC 24
Finished Sep 18 06:34:04 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604128591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.604128591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.2897811527
Short name T143
Test name
Test status
Simulation time 173354417926 ps
CPU time 193.48 seconds
Started Sep 18 06:34:54 AM UTC 24
Finished Sep 18 06:38:10 AM UTC 24
Peak memory 210872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897811527 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.2897811527
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1967494602
Short name T16
Test name
Test status
Simulation time 6557771207 ps
CPU time 18.78 seconds
Started Sep 18 06:34:52 AM UTC 24
Finished Sep 18 06:35:12 AM UTC 24
Peak memory 221120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1967494602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.adc_ctrl_stress_all_with_rand_reset.1967494602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.308937629
Short name T638
Test name
Test status
Simulation time 529122716 ps
CPU time 1.37 seconds
Started Sep 18 07:29:13 AM UTC 24
Finished Sep 18 07:29:16 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308937629 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.308937629
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.3506155020
Short name T307
Test name
Test status
Simulation time 339790116776 ps
CPU time 228.93 seconds
Started Sep 18 07:28:12 AM UTC 24
Finished Sep 18 07:32:04 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506155020 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.3506155020
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.2848662021
Short name T314
Test name
Test status
Simulation time 329757691201 ps
CPU time 233.38 seconds
Started Sep 18 07:28:43 AM UTC 24
Finished Sep 18 07:32:40 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848662021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2848662021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.1164708577
Short name T646
Test name
Test status
Simulation time 163162516766 ps
CPU time 143.87 seconds
Started Sep 18 07:27:29 AM UTC 24
Finished Sep 18 07:29:55 AM UTC 24
Peak memory 210952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164708577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1164708577
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1946378940
Short name T667
Test name
Test status
Simulation time 495136918157 ps
CPU time 271.25 seconds
Started Sep 18 07:27:34 AM UTC 24
Finished Sep 18 07:32:08 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946378940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.1946378940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.3862677114
Short name T655
Test name
Test status
Simulation time 160032241173 ps
CPU time 224.32 seconds
Started Sep 18 07:27:24 AM UTC 24
Finished Sep 18 07:31:12 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862677114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3862677114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.2959324911
Short name T702
Test name
Test status
Simulation time 492675178167 ps
CPU time 518.7 seconds
Started Sep 18 07:27:25 AM UTC 24
Finished Sep 18 07:36:10 AM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959324911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.2959324911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.3404016249
Short name T777
Test name
Test status
Simulation time 448946806074 ps
CPU time 1160.24 seconds
Started Sep 18 07:27:49 AM UTC 24
Finished Sep 18 07:47:20 AM UTC 24
Peak memory 213360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404016249 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.3404016249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3892529126
Short name T709
Test name
Test status
Simulation time 395394336359 ps
CPU time 516.07 seconds
Started Sep 18 07:27:58 AM UTC 24
Finished Sep 18 07:36:39 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892529126 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.3892529126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.2317447300
Short name T644
Test name
Test status
Simulation time 26520838618 ps
CPU time 43.63 seconds
Started Sep 18 07:29:03 AM UTC 24
Finished Sep 18 07:29:48 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317447300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2317447300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.3101851398
Short name T635
Test name
Test status
Simulation time 4943381298 ps
CPU time 21.66 seconds
Started Sep 18 07:28:47 AM UTC 24
Finished Sep 18 07:29:10 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101851398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3101851398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.2191275170
Short name T628
Test name
Test status
Simulation time 5719976439 ps
CPU time 2.53 seconds
Started Sep 18 07:27:24 AM UTC 24
Finished Sep 18 07:27:28 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191275170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2191275170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.3893484548
Short name T684
Test name
Test status
Simulation time 171943677199 ps
CPU time 268.83 seconds
Started Sep 18 07:29:11 AM UTC 24
Finished Sep 18 07:33:44 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893484548 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.3893484548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1280836412
Short name T640
Test name
Test status
Simulation time 1356306504 ps
CPU time 6.83 seconds
Started Sep 18 07:29:10 AM UTC 24
Finished Sep 18 07:29:18 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1280836412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.adc_ctrl_stress_all_with_rand_reset.1280836412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.483963846
Short name T652
Test name
Test status
Simulation time 452678063 ps
CPU time 2.85 seconds
Started Sep 18 07:30:58 AM UTC 24
Finished Sep 18 07:31:01 AM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483963846 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.483963846
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.2194328587
Short name T715
Test name
Test status
Simulation time 168111574896 ps
CPU time 442 seconds
Started Sep 18 07:29:49 AM UTC 24
Finished Sep 18 07:37:16 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194328587 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.2194328587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.796191657
Short name T677
Test name
Test status
Simulation time 185452620766 ps
CPU time 187.95 seconds
Started Sep 18 07:29:49 AM UTC 24
Finished Sep 18 07:33:00 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796191657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.796191657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.3186043470
Short name T782
Test name
Test status
Simulation time 334772174596 ps
CPU time 1103.27 seconds
Started Sep 18 07:29:31 AM UTC 24
Finished Sep 18 07:48:05 AM UTC 24
Peak memory 213496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186043470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3186043470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1670614036
Short name T682
Test name
Test status
Simulation time 324882509482 ps
CPU time 223.94 seconds
Started Sep 18 07:29:33 AM UTC 24
Finished Sep 18 07:33:19 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670614036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.1670614036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.3944451252
Short name T287
Test name
Test status
Simulation time 334885130875 ps
CPU time 1022.62 seconds
Started Sep 18 07:29:17 AM UTC 24
Finished Sep 18 07:46:29 AM UTC 24
Peak memory 213408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944451252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3944451252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.1883753172
Short name T691
Test name
Test status
Simulation time 495508865018 ps
CPU time 288.59 seconds
Started Sep 18 07:29:19 AM UTC 24
Finished Sep 18 07:34:11 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883753172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.1883753172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2060751901
Short name T743
Test name
Test status
Simulation time 387283171422 ps
CPU time 640.01 seconds
Started Sep 18 07:29:37 AM UTC 24
Finished Sep 18 07:40:24 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060751901 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.2060751901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.3719700083
Short name T700
Test name
Test status
Simulation time 73670635685 ps
CPU time 327.34 seconds
Started Sep 18 07:30:14 AM UTC 24
Finished Sep 18 07:35:46 AM UTC 24
Peak memory 211072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719700083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3719700083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.3185395455
Short name T670
Test name
Test status
Simulation time 33506709221 ps
CPU time 132.76 seconds
Started Sep 18 07:30:02 AM UTC 24
Finished Sep 18 07:32:17 AM UTC 24
Peak memory 210824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185395455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3185395455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.2762266034
Short name T647
Test name
Test status
Simulation time 4262243781 ps
CPU time 5.57 seconds
Started Sep 18 07:29:55 AM UTC 24
Finished Sep 18 07:30:02 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762266034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2762266034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.2272731265
Short name T641
Test name
Test status
Simulation time 5943292017 ps
CPU time 13.46 seconds
Started Sep 18 07:29:15 AM UTC 24
Finished Sep 18 07:29:30 AM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272731265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2272731265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.1854857723
Short name T663
Test name
Test status
Simulation time 201256200003 ps
CPU time 71.04 seconds
Started Sep 18 07:30:53 AM UTC 24
Finished Sep 18 07:32:05 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854857723 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.1854857723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3043534055
Short name T653
Test name
Test status
Simulation time 2718563211 ps
CPU time 18.62 seconds
Started Sep 18 07:30:48 AM UTC 24
Finished Sep 18 07:31:08 AM UTC 24
Peak memory 210892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3043534055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.adc_ctrl_stress_all_with_rand_reset.3043534055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.3249233931
Short name T666
Test name
Test status
Simulation time 338734141 ps
CPU time 1.74 seconds
Started Sep 18 07:32:06 AM UTC 24
Finished Sep 18 07:32:08 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249233931 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3249233931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.2805148876
Short name T685
Test name
Test status
Simulation time 164385908131 ps
CPU time 138.73 seconds
Started Sep 18 07:31:25 AM UTC 24
Finished Sep 18 07:33:46 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805148876 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.2805148876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2803188482
Short name T739
Test name
Test status
Simulation time 323238217274 ps
CPU time 522.36 seconds
Started Sep 18 07:31:13 AM UTC 24
Finished Sep 18 07:40:01 AM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803188482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.2803188482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.2209710497
Short name T721
Test name
Test status
Simulation time 162197840033 ps
CPU time 385.84 seconds
Started Sep 18 07:31:03 AM UTC 24
Finished Sep 18 07:37:33 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209710497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2209710497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.2706057586
Short name T776
Test name
Test status
Simulation time 331274951997 ps
CPU time 961.08 seconds
Started Sep 18 07:31:09 AM UTC 24
Finished Sep 18 07:47:20 AM UTC 24
Peak memory 213412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706057586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.2706057586
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3953438543
Short name T771
Test name
Test status
Simulation time 403049507683 ps
CPU time 908.3 seconds
Started Sep 18 07:31:24 AM UTC 24
Finished Sep 18 07:46:41 AM UTC 24
Peak memory 213356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953438543 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.3953438543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.816342070
Short name T738
Test name
Test status
Simulation time 77803732732 ps
CPU time 491.98 seconds
Started Sep 18 07:31:43 AM UTC 24
Finished Sep 18 07:40:00 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816342070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.816342070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.3483840181
Short name T671
Test name
Test status
Simulation time 34067817261 ps
CPU time 35.96 seconds
Started Sep 18 07:31:41 AM UTC 24
Finished Sep 18 07:32:19 AM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483840181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3483840181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.4161474678
Short name T662
Test name
Test status
Simulation time 5376768749 ps
CPU time 3.22 seconds
Started Sep 18 07:31:38 AM UTC 24
Finished Sep 18 07:31:42 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161474678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4161474678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.1886232967
Short name T656
Test name
Test status
Simulation time 5784777017 ps
CPU time 12.38 seconds
Started Sep 18 07:30:59 AM UTC 24
Finished Sep 18 07:31:12 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886232967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1886232967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.2847188650
Short name T789
Test name
Test status
Simulation time 205983624739 ps
CPU time 1111.18 seconds
Started Sep 18 07:32:05 AM UTC 24
Finished Sep 18 07:50:47 AM UTC 24
Peak memory 214036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847188650 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.2847188650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3408184087
Short name T668
Test name
Test status
Simulation time 2432550389 ps
CPU time 12.23 seconds
Started Sep 18 07:31:56 AM UTC 24
Finished Sep 18 07:32:09 AM UTC 24
Peak memory 221652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3408184087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.adc_ctrl_stress_all_with_rand_reset.3408184087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.2573748225
Short name T679
Test name
Test status
Simulation time 399160074 ps
CPU time 1.13 seconds
Started Sep 18 07:33:01 AM UTC 24
Finished Sep 18 07:33:03 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573748225 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2573748225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.3847906267
Short name T737
Test name
Test status
Simulation time 538870668840 ps
CPU time 455.96 seconds
Started Sep 18 07:32:19 AM UTC 24
Finished Sep 18 07:40:00 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847906267 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.3847906267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.1965856651
Short name T678
Test name
Test status
Simulation time 165312426401 ps
CPU time 49.96 seconds
Started Sep 18 07:32:09 AM UTC 24
Finished Sep 18 07:33:00 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965856651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1965856651
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2123162255
Short name T794
Test name
Test status
Simulation time 487403179494 ps
CPU time 1260.02 seconds
Started Sep 18 07:32:10 AM UTC 24
Finished Sep 18 07:53:22 AM UTC 24
Peak memory 213748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123162255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.2123162255
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.4141412079
Short name T687
Test name
Test status
Simulation time 164532548497 ps
CPU time 104.08 seconds
Started Sep 18 07:32:08 AM UTC 24
Finished Sep 18 07:33:54 AM UTC 24
Peak memory 210780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141412079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4141412079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.1585794072
Short name T706
Test name
Test status
Simulation time 158141625505 ps
CPU time 244.25 seconds
Started Sep 18 07:32:09 AM UTC 24
Finished Sep 18 07:36:16 AM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585794072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.1585794072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.3831993119
Short name T791
Test name
Test status
Simulation time 382768232490 ps
CPU time 1140.79 seconds
Started Sep 18 07:32:15 AM UTC 24
Finished Sep 18 07:51:27 AM UTC 24
Peak memory 213432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831993119 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.3831993119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3157973171
Short name T768
Test name
Test status
Simulation time 601595633796 ps
CPU time 792.44 seconds
Started Sep 18 07:32:18 AM UTC 24
Finished Sep 18 07:45:38 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157973171 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.3157973171
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.1816620854
Short name T681
Test name
Test status
Simulation time 32105143151 ps
CPU time 32.1 seconds
Started Sep 18 07:32:38 AM UTC 24
Finished Sep 18 07:33:12 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816620854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1816620854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.2634166249
Short name T675
Test name
Test status
Simulation time 4810187835 ps
CPU time 4.96 seconds
Started Sep 18 07:32:36 AM UTC 24
Finished Sep 18 07:32:42 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634166249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2634166249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.3425824637
Short name T672
Test name
Test status
Simulation time 5950536771 ps
CPU time 24.9 seconds
Started Sep 18 07:32:07 AM UTC 24
Finished Sep 18 07:32:33 AM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425824637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3425824637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.3960594811
Short name T801
Test name
Test status
Simulation time 370222857048 ps
CPU time 1677.88 seconds
Started Sep 18 07:32:56 AM UTC 24
Finished Sep 18 08:01:09 AM UTC 24
Peak memory 213720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960594811 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.3960594811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.164647541
Short name T91
Test name
Test status
Simulation time 54010938363 ps
CPU time 25.16 seconds
Started Sep 18 07:32:44 AM UTC 24
Finished Sep 18 07:33:10 AM UTC 24
Peak memory 221324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=164647541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
43.adc_ctrl_stress_all_with_rand_reset.164647541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.2975964207
Short name T692
Test name
Test status
Simulation time 314333168 ps
CPU time 1.55 seconds
Started Sep 18 07:34:12 AM UTC 24
Finished Sep 18 07:34:17 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975964207 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2975964207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.2801176076
Short name T698
Test name
Test status
Simulation time 165169403354 ps
CPU time 72.2 seconds
Started Sep 18 07:33:44 AM UTC 24
Finished Sep 18 07:34:58 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801176076 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.2801176076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.1361075938
Short name T796
Test name
Test status
Simulation time 328425903780 ps
CPU time 1238.62 seconds
Started Sep 18 07:33:47 AM UTC 24
Finished Sep 18 07:54:39 AM UTC 24
Peak memory 213372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361075938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1361075938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.3144538633
Short name T770
Test name
Test status
Simulation time 323590048316 ps
CPU time 768.26 seconds
Started Sep 18 07:33:11 AM UTC 24
Finished Sep 18 07:46:07 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144538633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3144538633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1673843517
Short name T699
Test name
Test status
Simulation time 161557058837 ps
CPU time 107.4 seconds
Started Sep 18 07:33:13 AM UTC 24
Finished Sep 18 07:35:02 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673843517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.1673843517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.1843175525
Short name T750
Test name
Test status
Simulation time 164157855652 ps
CPU time 486.2 seconds
Started Sep 18 07:33:04 AM UTC 24
Finished Sep 18 07:41:15 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843175525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1843175525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.854398956
Short name T727
Test name
Test status
Simulation time 167168505720 ps
CPU time 308.83 seconds
Started Sep 18 07:33:08 AM UTC 24
Finished Sep 18 07:38:21 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854398956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.854398956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.2242694565
Short name T697
Test name
Test status
Simulation time 198856634560 ps
CPU time 84.39 seconds
Started Sep 18 07:33:20 AM UTC 24
Finished Sep 18 07:34:46 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242694565 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.2242694565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.607428229
Short name T710
Test name
Test status
Simulation time 206033519427 ps
CPU time 189.3 seconds
Started Sep 18 07:33:37 AM UTC 24
Finished Sep 18 07:36:49 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607428229 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.607428229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.3357974818
Short name T760
Test name
Test status
Simulation time 84128375670 ps
CPU time 501.66 seconds
Started Sep 18 07:34:00 AM UTC 24
Finished Sep 18 07:42:27 AM UTC 24
Peak memory 211152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357974818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3357974818
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.3514517815
Short name T703
Test name
Test status
Simulation time 42353098663 ps
CPU time 131.6 seconds
Started Sep 18 07:33:54 AM UTC 24
Finished Sep 18 07:36:12 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514517815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3514517815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.159032358
Short name T688
Test name
Test status
Simulation time 3977249703 ps
CPU time 3.88 seconds
Started Sep 18 07:33:52 AM UTC 24
Finished Sep 18 07:33:57 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159032358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.159032358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.3251682133
Short name T680
Test name
Test status
Simulation time 5944666052 ps
CPU time 5.3 seconds
Started Sep 18 07:33:01 AM UTC 24
Finished Sep 18 07:33:07 AM UTC 24
Peak memory 210648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251682133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3251682133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.980642475
Short name T690
Test name
Test status
Simulation time 1522522010 ps
CPU time 9.05 seconds
Started Sep 18 07:34:00 AM UTC 24
Finished Sep 18 07:34:10 AM UTC 24
Peak memory 210452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=980642475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
44.adc_ctrl_stress_all_with_rand_reset.980642475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.2490840841
Short name T707
Test name
Test status
Simulation time 326863128 ps
CPU time 1.39 seconds
Started Sep 18 07:36:14 AM UTC 24
Finished Sep 18 07:36:16 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490840841 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2490840841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.2277213964
Short name T713
Test name
Test status
Simulation time 229978918848 ps
CPU time 125.67 seconds
Started Sep 18 07:34:59 AM UTC 24
Finished Sep 18 07:37:07 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277213964 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.2277213964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.1277372743
Short name T733
Test name
Test status
Simulation time 162929276570 ps
CPU time 239.79 seconds
Started Sep 18 07:35:03 AM UTC 24
Finished Sep 18 07:39:06 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277372743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1277372743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.2443843325
Short name T741
Test name
Test status
Simulation time 493215924321 ps
CPU time 336.87 seconds
Started Sep 18 07:34:36 AM UTC 24
Finished Sep 18 07:40:17 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443843325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2443843325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.534706047
Short name T736
Test name
Test status
Simulation time 485635759823 ps
CPU time 305.3 seconds
Started Sep 18 07:34:36 AM UTC 24
Finished Sep 18 07:39:45 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534706047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.534706047
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.2032836359
Short name T795
Test name
Test status
Simulation time 490873784067 ps
CPU time 1175.45 seconds
Started Sep 18 07:34:29 AM UTC 24
Finished Sep 18 07:54:17 AM UTC 24
Peak memory 213696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032836359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2032836359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.1371755298
Short name T784
Test name
Test status
Simulation time 487925705755 ps
CPU time 885.82 seconds
Started Sep 18 07:34:32 AM UTC 24
Finished Sep 18 07:49:30 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371755298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.1371755298
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.2719397784
Short name T704
Test name
Test status
Simulation time 229411147331 ps
CPU time 85.83 seconds
Started Sep 18 07:34:45 AM UTC 24
Finished Sep 18 07:36:13 AM UTC 24
Peak memory 210684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719397784 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.2719397784
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1053168193
Short name T717
Test name
Test status
Simulation time 190250332514 ps
CPU time 149.77 seconds
Started Sep 18 07:34:47 AM UTC 24
Finished Sep 18 07:37:19 AM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053168193 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.1053168193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.1876451348
Short name T346
Test name
Test status
Simulation time 126097751303 ps
CPU time 1009.31 seconds
Started Sep 18 07:35:52 AM UTC 24
Finished Sep 18 07:52:51 AM UTC 24
Peak memory 213636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876451348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1876451348
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.1249695936
Short name T723
Test name
Test status
Simulation time 31576631785 ps
CPU time 113.11 seconds
Started Sep 18 07:35:47 AM UTC 24
Finished Sep 18 07:37:42 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249695936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1249695936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.1576899981
Short name T701
Test name
Test status
Simulation time 5523322038 ps
CPU time 7.96 seconds
Started Sep 18 07:35:42 AM UTC 24
Finished Sep 18 07:35:51 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576899981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1576899981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.1041017919
Short name T696
Test name
Test status
Simulation time 6024381343 ps
CPU time 21.91 seconds
Started Sep 18 07:34:18 AM UTC 24
Finished Sep 18 07:34:45 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041017919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1041017919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.905110039
Short name T740
Test name
Test status
Simulation time 356574180703 ps
CPU time 233.6 seconds
Started Sep 18 07:36:13 AM UTC 24
Finished Sep 18 07:40:09 AM UTC 24
Peak memory 210852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905110039 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.905110039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.4020414806
Short name T30
Test name
Test status
Simulation time 47887203956 ps
CPU time 22.17 seconds
Started Sep 18 07:36:11 AM UTC 24
Finished Sep 18 07:36:34 AM UTC 24
Peak memory 221400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4020414806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.adc_ctrl_stress_all_with_rand_reset.4020414806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.3735921580
Short name T718
Test name
Test status
Simulation time 404687893 ps
CPU time 1.3 seconds
Started Sep 18 07:37:19 AM UTC 24
Finished Sep 18 07:37:21 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735921580 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3735921580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.79151328
Short name T294
Test name
Test status
Simulation time 530990102926 ps
CPU time 482.3 seconds
Started Sep 18 07:36:49 AM UTC 24
Finished Sep 18 07:44:57 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79151328 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.79151328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.6415794
Short name T267
Test name
Test status
Simulation time 433688167387 ps
CPU time 642.95 seconds
Started Sep 18 07:37:00 AM UTC 24
Finished Sep 18 07:47:49 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6415794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_S
EQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.6415794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.1927134361
Short name T305
Test name
Test status
Simulation time 503924087881 ps
CPU time 698.76 seconds
Started Sep 18 07:36:32 AM UTC 24
Finished Sep 18 07:48:18 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927134361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1927134361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1474682341
Short name T748
Test name
Test status
Simulation time 329443001221 ps
CPU time 258.72 seconds
Started Sep 18 07:36:35 AM UTC 24
Finished Sep 18 07:40:57 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474682341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.1474682341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.3963439848
Short name T639
Test name
Test status
Simulation time 485253238991 ps
CPU time 292.5 seconds
Started Sep 18 07:36:17 AM UTC 24
Finished Sep 18 07:41:13 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963439848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3963439848
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.686783939
Short name T781
Test name
Test status
Simulation time 333163816937 ps
CPU time 696.03 seconds
Started Sep 18 07:36:17 AM UTC 24
Finished Sep 18 07:48:00 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686783939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.686783939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.3482685476
Short name T751
Test name
Test status
Simulation time 584216061021 ps
CPU time 288.37 seconds
Started Sep 18 07:36:36 AM UTC 24
Finished Sep 18 07:41:28 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482685476 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.3482685476
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1074816710
Short name T793
Test name
Test status
Simulation time 396133751291 ps
CPU time 955.14 seconds
Started Sep 18 07:36:40 AM UTC 24
Finished Sep 18 07:52:45 AM UTC 24
Peak memory 213292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074816710 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.1074816710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.1148639649
Short name T772
Test name
Test status
Simulation time 114398610741 ps
CPU time 584.08 seconds
Started Sep 18 07:37:08 AM UTC 24
Finished Sep 18 07:46:58 AM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148639649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1148639649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.490530665
Short name T726
Test name
Test status
Simulation time 32696719881 ps
CPU time 62.73 seconds
Started Sep 18 07:37:04 AM UTC 24
Finished Sep 18 07:38:08 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490530665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.490530665
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.3839900472
Short name T712
Test name
Test status
Simulation time 2937582166 ps
CPU time 2.46 seconds
Started Sep 18 07:37:00 AM UTC 24
Finished Sep 18 07:37:03 AM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839900472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3839900472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.2713230406
Short name T708
Test name
Test status
Simulation time 5640927673 ps
CPU time 20.57 seconds
Started Sep 18 07:36:14 AM UTC 24
Finished Sep 18 07:36:36 AM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713230406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2713230406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.4017174869
Short name T758
Test name
Test status
Simulation time 179141510551 ps
CPU time 285.32 seconds
Started Sep 18 07:37:17 AM UTC 24
Finished Sep 18 07:42:06 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017174869 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.4017174869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2438369309
Short name T720
Test name
Test status
Simulation time 11467673098 ps
CPU time 12.12 seconds
Started Sep 18 07:37:11 AM UTC 24
Finished Sep 18 07:37:24 AM UTC 24
Peak memory 221064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2438369309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.adc_ctrl_stress_all_with_rand_reset.2438369309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.3441528557
Short name T730
Test name
Test status
Simulation time 491497866 ps
CPU time 1.85 seconds
Started Sep 18 07:38:40 AM UTC 24
Finished Sep 18 07:38:43 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441528557 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3441528557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.1122452417
Short name T767
Test name
Test status
Simulation time 179117776098 ps
CPU time 429.71 seconds
Started Sep 18 07:37:57 AM UTC 24
Finished Sep 18 07:45:12 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122452417 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.1122452417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.130501334
Short name T752
Test name
Test status
Simulation time 357721553761 ps
CPU time 207.1 seconds
Started Sep 18 07:38:03 AM UTC 24
Finished Sep 18 07:41:33 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130501334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.130501334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.730347990
Short name T325
Test name
Test status
Simulation time 337399523411 ps
CPU time 300.07 seconds
Started Sep 18 07:37:25 AM UTC 24
Finished Sep 18 07:42:29 AM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730347990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.730347990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4247196173
Short name T800
Test name
Test status
Simulation time 501154444473 ps
CPU time 1223.17 seconds
Started Sep 18 07:37:33 AM UTC 24
Finished Sep 18 07:58:08 AM UTC 24
Peak memory 213580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247196173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.4247196173
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.3982449373
Short name T754
Test name
Test status
Simulation time 333414752153 ps
CPU time 269.09 seconds
Started Sep 18 07:37:22 AM UTC 24
Finished Sep 18 07:41:55 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982449373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3982449373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.2096899828
Short name T775
Test name
Test status
Simulation time 160706090413 ps
CPU time 585.37 seconds
Started Sep 18 07:37:23 AM UTC 24
Finished Sep 18 07:47:15 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096899828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.2096899828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.245683224
Short name T798
Test name
Test status
Simulation time 380112191305 ps
CPU time 1086.98 seconds
Started Sep 18 07:37:34 AM UTC 24
Finished Sep 18 07:55:52 AM UTC 24
Peak memory 213628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245683224 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.245683224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3668163501
Short name T797
Test name
Test status
Simulation time 386955067686 ps
CPU time 1026.77 seconds
Started Sep 18 07:37:43 AM UTC 24
Finished Sep 18 07:55:00 AM UTC 24
Peak memory 213356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668163501 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.3668163501
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.2436607142
Short name T734
Test name
Test status
Simulation time 32316218119 ps
CPU time 79.05 seconds
Started Sep 18 07:38:09 AM UTC 24
Finished Sep 18 07:39:30 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436607142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2436607142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.3256506670
Short name T728
Test name
Test status
Simulation time 3807843388 ps
CPU time 16.49 seconds
Started Sep 18 07:38:06 AM UTC 24
Finished Sep 18 07:38:23 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256506670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3256506670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.1691642811
Short name T722
Test name
Test status
Simulation time 5708491874 ps
CPU time 12.36 seconds
Started Sep 18 07:37:20 AM UTC 24
Finished Sep 18 07:37:34 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691642811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1691642811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.3519426300
Short name T799
Test name
Test status
Simulation time 375780067695 ps
CPU time 1065.61 seconds
Started Sep 18 07:38:39 AM UTC 24
Finished Sep 18 07:56:35 AM UTC 24
Peak memory 213524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519426300 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.3519426300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3288750399
Short name T729
Test name
Test status
Simulation time 2669432723 ps
CPU time 12.83 seconds
Started Sep 18 07:38:24 AM UTC 24
Finished Sep 18 07:38:38 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3288750399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.adc_ctrl_stress_all_with_rand_reset.3288750399
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.1812473018
Short name T745
Test name
Test status
Simulation time 529065231 ps
CPU time 2.97 seconds
Started Sep 18 07:40:24 AM UTC 24
Finished Sep 18 07:40:28 AM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812473018 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1812473018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.571390079
Short name T780
Test name
Test status
Simulation time 168603304825 ps
CPU time 470.39 seconds
Started Sep 18 07:39:46 AM UTC 24
Finished Sep 18 07:47:42 AM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571390079 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.571390079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2612971125
Short name T763
Test name
Test status
Simulation time 203057413120 ps
CPU time 259.56 seconds
Started Sep 18 07:40:01 AM UTC 24
Finished Sep 18 07:44:24 AM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612971125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2612971125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.4033016384
Short name T783
Test name
Test status
Simulation time 492434110234 ps
CPU time 608.9 seconds
Started Sep 18 07:39:07 AM UTC 24
Finished Sep 18 07:49:23 AM UTC 24
Peak memory 210848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033016384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4033016384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1179503908
Short name T749
Test name
Test status
Simulation time 158021423632 ps
CPU time 116.1 seconds
Started Sep 18 07:39:16 AM UTC 24
Finished Sep 18 07:41:14 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179503908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.1179503908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.84697872
Short name T786
Test name
Test status
Simulation time 492710691673 ps
CPU time 649.25 seconds
Started Sep 18 07:38:52 AM UTC 24
Finished Sep 18 07:49:48 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84697872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.84697872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.3657887118
Short name T778
Test name
Test status
Simulation time 164122561161 ps
CPU time 497.65 seconds
Started Sep 18 07:39:00 AM UTC 24
Finished Sep 18 07:47:23 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657887118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.3657887118
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.7010599
Short name T324
Test name
Test status
Simulation time 549092815348 ps
CPU time 1608.98 seconds
Started Sep 18 07:39:31 AM UTC 24
Finished Sep 18 08:06:35 AM UTC 24
Peak memory 213368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7010599 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.7010599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4063917198
Short name T787
Test name
Test status
Simulation time 392687954051 ps
CPU time 628.82 seconds
Started Sep 18 07:39:32 AM UTC 24
Finished Sep 18 07:50:08 AM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063917198 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.4063917198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.4054579083
Short name T773
Test name
Test status
Simulation time 90682661518 ps
CPU time 404.98 seconds
Started Sep 18 07:40:10 AM UTC 24
Finished Sep 18 07:46:59 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054579083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4054579083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.565432823
Short name T746
Test name
Test status
Simulation time 29747565959 ps
CPU time 27.08 seconds
Started Sep 18 07:40:02 AM UTC 24
Finished Sep 18 07:40:30 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565432823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.565432823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.612890471
Short name T742
Test name
Test status
Simulation time 4768880976 ps
CPU time 19.33 seconds
Started Sep 18 07:40:01 AM UTC 24
Finished Sep 18 07:40:21 AM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612890471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.612890471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.3166885329
Short name T731
Test name
Test status
Simulation time 5886128980 ps
CPU time 7.28 seconds
Started Sep 18 07:38:43 AM UTC 24
Finished Sep 18 07:38:52 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166885329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3166885329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.987974985
Short name T785
Test name
Test status
Simulation time 451878187979 ps
CPU time 544.96 seconds
Started Sep 18 07:40:22 AM UTC 24
Finished Sep 18 07:49:33 AM UTC 24
Peak memory 223328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987974985 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.987974985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1656718553
Short name T40
Test name
Test status
Simulation time 2630498813 ps
CPU time 12.22 seconds
Started Sep 18 07:40:18 AM UTC 24
Finished Sep 18 07:40:32 AM UTC 24
Peak memory 210624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1656718553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.adc_ctrl_stress_all_with_rand_reset.1656718553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.3957174190
Short name T757
Test name
Test status
Simulation time 497583033 ps
CPU time 2.93 seconds
Started Sep 18 07:42:02 AM UTC 24
Finished Sep 18 07:42:05 AM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957174190 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3957174190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.2114856547
Short name T802
Test name
Test status
Simulation time 514846136666 ps
CPU time 1461.09 seconds
Started Sep 18 07:41:15 AM UTC 24
Finished Sep 18 08:05:50 AM UTC 24
Peak memory 213640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114856547 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.2114856547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.2643241577
Short name T769
Test name
Test status
Simulation time 177506374053 ps
CPU time 271.3 seconds
Started Sep 18 07:41:16 AM UTC 24
Finished Sep 18 07:45:51 AM UTC 24
Peak memory 210880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643241577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2643241577
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.2789387635
Short name T803
Test name
Test status
Simulation time 501928409006 ps
CPU time 1514.97 seconds
Started Sep 18 07:40:33 AM UTC 24
Finished Sep 18 08:06:03 AM UTC 24
Peak memory 213668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789387635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2789387635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3929598153
Short name T766
Test name
Test status
Simulation time 328526180322 ps
CPU time 230.16 seconds
Started Sep 18 07:40:40 AM UTC 24
Finished Sep 18 07:44:33 AM UTC 24
Peak memory 210928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929598153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.3929598153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.1349983279
Short name T765
Test name
Test status
Simulation time 157815402253 ps
CPU time 236.01 seconds
Started Sep 18 07:40:30 AM UTC 24
Finished Sep 18 07:44:29 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349983279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1349983279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.3762182647
Short name T774
Test name
Test status
Simulation time 484181553865 ps
CPU time 383.46 seconds
Started Sep 18 07:40:32 AM UTC 24
Finished Sep 18 07:47:00 AM UTC 24
Peak memory 210960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762182647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.3762182647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.2996666184
Short name T271
Test name
Test status
Simulation time 346251453824 ps
CPU time 176.55 seconds
Started Sep 18 07:40:58 AM UTC 24
Finished Sep 18 07:43:57 AM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996666184 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.2996666184
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3953448914
Short name T788
Test name
Test status
Simulation time 201372890258 ps
CPU time 565.23 seconds
Started Sep 18 07:41:14 AM UTC 24
Finished Sep 18 07:50:46 AM UTC 24
Peak memory 210680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953448914 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.3953448914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.2138206271
Short name T790
Test name
Test status
Simulation time 94266907430 ps
CPU time 563.04 seconds
Started Sep 18 07:41:36 AM UTC 24
Finished Sep 18 07:51:05 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138206271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2138206271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.1239738420
Short name T756
Test name
Test status
Simulation time 33647445798 ps
CPU time 29.05 seconds
Started Sep 18 07:41:33 AM UTC 24
Finished Sep 18 07:42:04 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239738420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1239738420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.2013140768
Short name T753
Test name
Test status
Simulation time 4133663159 ps
CPU time 5.16 seconds
Started Sep 18 07:41:29 AM UTC 24
Finished Sep 18 07:41:36 AM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013140768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2013140768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.4252857877
Short name T747
Test name
Test status
Simulation time 5706812007 ps
CPU time 12.38 seconds
Started Sep 18 07:40:25 AM UTC 24
Finished Sep 18 07:40:39 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252857877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4252857877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1000221928
Short name T755
Test name
Test status
Simulation time 1525599268 ps
CPU time 8.02 seconds
Started Sep 18 07:41:51 AM UTC 24
Finished Sep 18 07:42:00 AM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1000221928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.adc_ctrl_stress_all_with_rand_reset.1000221928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.1462478104
Short name T162
Test name
Test status
Simulation time 420642108 ps
CPU time 1.76 seconds
Started Sep 18 06:35:55 AM UTC 24
Finished Sep 18 06:35:58 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462478104 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1462478104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2071847668
Short name T36
Test name
Test status
Simulation time 169751643347 ps
CPU time 117.7 seconds
Started Sep 18 06:35:15 AM UTC 24
Finished Sep 18 06:37:15 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071847668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.2071847668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2144494122
Short name T148
Test name
Test status
Simulation time 490000529360 ps
CPU time 262.99 seconds
Started Sep 18 06:35:04 AM UTC 24
Finished Sep 18 06:39:31 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144494122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2144494122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.2835114352
Short name T381
Test name
Test status
Simulation time 323680599262 ps
CPU time 734.39 seconds
Started Sep 18 06:35:11 AM UTC 24
Finished Sep 18 06:47:33 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835114352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.2835114352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2561001028
Short name T37
Test name
Test status
Simulation time 398208569551 ps
CPU time 114.18 seconds
Started Sep 18 06:35:20 AM UTC 24
Finished Sep 18 06:37:16 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561001028 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.2561001028
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.4057716843
Short name T210
Test name
Test status
Simulation time 93902391246 ps
CPU time 408.17 seconds
Started Sep 18 06:35:53 AM UTC 24
Finished Sep 18 06:42:45 AM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057716843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4057716843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.2548260200
Short name T31
Test name
Test status
Simulation time 28364348316 ps
CPU time 44.49 seconds
Started Sep 18 06:35:44 AM UTC 24
Finished Sep 18 06:36:30 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548260200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2548260200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.952473891
Short name T111
Test name
Test status
Simulation time 3016027007 ps
CPU time 13.28 seconds
Started Sep 18 06:35:39 AM UTC 24
Finished Sep 18 06:35:53 AM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952473891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.952473891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.4116651183
Short name T351
Test name
Test status
Simulation time 6025402319 ps
CPU time 6.96 seconds
Started Sep 18 06:35:02 AM UTC 24
Finished Sep 18 06:35:10 AM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116651183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4116651183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3850818138
Short name T21
Test name
Test status
Simulation time 3418897596 ps
CPU time 23 seconds
Started Sep 18 06:35:54 AM UTC 24
Finished Sep 18 06:36:18 AM UTC 24
Peak memory 221576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3850818138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.adc_ctrl_stress_all_with_rand_reset.3850818138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3529492182
Short name T38
Test name
Test status
Simulation time 523710921 ps
CPU time 1.3 seconds
Started Sep 18 06:37:16 AM UTC 24
Finished Sep 18 06:37:18 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529492182 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3529492182
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.3729995051
Short name T259
Test name
Test status
Simulation time 506286290528 ps
CPU time 1405.5 seconds
Started Sep 18 06:36:33 AM UTC 24
Finished Sep 18 07:00:12 AM UTC 24
Peak memory 213452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729995051 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.3729995051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.4114492617
Short name T256
Test name
Test status
Simulation time 187631479697 ps
CPU time 586.61 seconds
Started Sep 18 06:36:34 AM UTC 24
Finished Sep 18 06:46:28 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114492617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4114492617
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3279877870
Short name T182
Test name
Test status
Simulation time 169302544832 ps
CPU time 476.59 seconds
Started Sep 18 06:36:15 AM UTC 24
Finished Sep 18 06:44:17 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279877870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3279877870
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3236487223
Short name T206
Test name
Test status
Simulation time 333413740602 ps
CPU time 274.48 seconds
Started Sep 18 06:36:17 AM UTC 24
Finished Sep 18 06:40:55 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236487223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.3236487223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.1173113897
Short name T196
Test name
Test status
Simulation time 162406947085 ps
CPU time 112.35 seconds
Started Sep 18 06:35:58 AM UTC 24
Finished Sep 18 06:37:53 AM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173113897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1173113897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1048875891
Short name T369
Test name
Test status
Simulation time 161355997344 ps
CPU time 440.32 seconds
Started Sep 18 06:36:12 AM UTC 24
Finished Sep 18 06:43:38 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048875891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.1048875891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2903254744
Short name T296
Test name
Test status
Simulation time 554671215535 ps
CPU time 1456.67 seconds
Started Sep 18 06:36:19 AM UTC 24
Finished Sep 18 07:00:49 AM UTC 24
Peak memory 213716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903254744 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.2903254744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1617053023
Short name T375
Test name
Test status
Simulation time 200537895099 ps
CPU time 570.22 seconds
Started Sep 18 06:36:31 AM UTC 24
Finished Sep 18 06:46:07 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617053023 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.1617053023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2101449769
Short name T184
Test name
Test status
Simulation time 88398053649 ps
CPU time 466.91 seconds
Started Sep 18 06:37:02 AM UTC 24
Finished Sep 18 06:44:54 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101449769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2101449769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.3292150864
Short name T198
Test name
Test status
Simulation time 43189731682 ps
CPU time 85.75 seconds
Started Sep 18 06:36:55 AM UTC 24
Finished Sep 18 06:38:23 AM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292150864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3292150864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.2199149234
Short name T33
Test name
Test status
Simulation time 2856724169 ps
CPU time 7.33 seconds
Started Sep 18 06:36:46 AM UTC 24
Finished Sep 18 06:36:55 AM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199149234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2199149234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.3811958504
Short name T188
Test name
Test status
Simulation time 5679019993 ps
CPU time 13.99 seconds
Started Sep 18 06:35:56 AM UTC 24
Finished Sep 18 06:36:11 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811958504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3811958504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.3705353155
Short name T202
Test name
Test status
Simulation time 343827575 ps
CPU time 2.19 seconds
Started Sep 18 06:39:09 AM UTC 24
Finished Sep 18 06:39:12 AM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705353155 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3705353155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.3113353911
Short name T164
Test name
Test status
Simulation time 355290942493 ps
CPU time 492.36 seconds
Started Sep 18 06:37:53 AM UTC 24
Finished Sep 18 06:46:11 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113353911 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.3113353911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.3529644392
Short name T228
Test name
Test status
Simulation time 364789573498 ps
CPU time 151.93 seconds
Started Sep 18 06:38:11 AM UTC 24
Finished Sep 18 06:40:46 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529644392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3529644392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1171584931
Short name T154
Test name
Test status
Simulation time 161971024884 ps
CPU time 105.75 seconds
Started Sep 18 06:37:25 AM UTC 24
Finished Sep 18 06:39:13 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171584931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1171584931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1426929326
Short name T373
Test name
Test status
Simulation time 491104825579 ps
CPU time 472.4 seconds
Started Sep 18 06:37:35 AM UTC 24
Finished Sep 18 06:45:33 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426929326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.1426929326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.2772470393
Short name T368
Test name
Test status
Simulation time 329308899536 ps
CPU time 361.41 seconds
Started Sep 18 06:37:23 AM UTC 24
Finished Sep 18 06:43:29 AM UTC 24
Peak memory 211032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772470393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.2772470393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2896739601
Short name T421
Test name
Test status
Simulation time 403468168050 ps
CPU time 1086.51 seconds
Started Sep 18 06:37:50 AM UTC 24
Finished Sep 18 06:56:07 AM UTC 24
Peak memory 213508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896739601 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.2896739601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.754732457
Short name T219
Test name
Test status
Simulation time 141150594631 ps
CPU time 579.36 seconds
Started Sep 18 06:38:25 AM UTC 24
Finished Sep 18 06:48:10 AM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754732457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.754732457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1316857444
Short name T357
Test name
Test status
Simulation time 37100375895 ps
CPU time 132.28 seconds
Started Sep 18 06:38:24 AM UTC 24
Finished Sep 18 06:40:38 AM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316857444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1316857444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.819772238
Short name T199
Test name
Test status
Simulation time 4822689580 ps
CPU time 3.81 seconds
Started Sep 18 06:38:20 AM UTC 24
Finished Sep 18 06:38:24 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819772238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.819772238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.957798596
Short name T354
Test name
Test status
Simulation time 5841480787 ps
CPU time 6.43 seconds
Started Sep 18 06:37:17 AM UTC 24
Finished Sep 18 06:37:25 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957798596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.957798596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.1419343573
Short name T160
Test name
Test status
Simulation time 324927760759 ps
CPU time 193.2 seconds
Started Sep 18 06:38:58 AM UTC 24
Finished Sep 18 06:42:14 AM UTC 24
Peak memory 210692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419343573 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.1419343573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.467826354
Short name T52
Test name
Test status
Simulation time 25077351488 ps
CPU time 28.51 seconds
Started Sep 18 06:38:46 AM UTC 24
Finished Sep 18 06:39:16 AM UTC 24
Peak memory 221404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=467826354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
7.adc_ctrl_stress_all_with_rand_reset.467826354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1011966356
Short name T359
Test name
Test status
Simulation time 366728813 ps
CPU time 1.29 seconds
Started Sep 18 06:40:41 AM UTC 24
Finished Sep 18 06:40:43 AM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011966356 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1011966356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2234294555
Short name T245
Test name
Test status
Simulation time 335250470855 ps
CPU time 775.73 seconds
Started Sep 18 06:39:37 AM UTC 24
Finished Sep 18 06:52:41 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234294555 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.2234294555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.2673466350
Short name T229
Test name
Test status
Simulation time 170229824378 ps
CPU time 115.34 seconds
Started Sep 18 06:39:19 AM UTC 24
Finished Sep 18 06:41:17 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673466350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2673466350
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2826139510
Short name T150
Test name
Test status
Simulation time 162876758027 ps
CPU time 128.32 seconds
Started Sep 18 06:39:28 AM UTC 24
Finished Sep 18 06:41:39 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826139510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.2826139510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.2346554504
Short name T414
Test name
Test status
Simulation time 325979780778 ps
CPU time 958.85 seconds
Started Sep 18 06:39:13 AM UTC 24
Finished Sep 18 06:55:22 AM UTC 24
Peak memory 213368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346554504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2346554504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3651922208
Short name T385
Test name
Test status
Simulation time 483828850859 ps
CPU time 611.64 seconds
Started Sep 18 06:39:16 AM UTC 24
Finished Sep 18 06:49:34 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651922208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.3651922208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1467438668
Short name T383
Test name
Test status
Simulation time 614672889888 ps
CPU time 494.85 seconds
Started Sep 18 06:39:36 AM UTC 24
Finished Sep 18 06:47:56 AM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467438668 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.1467438668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.3179155780
Short name T63
Test name
Test status
Simulation time 117908036901 ps
CPU time 937.16 seconds
Started Sep 18 06:40:23 AM UTC 24
Finished Sep 18 06:56:11 AM UTC 24
Peak memory 213700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179155780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3179155780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.1966656742
Short name T361
Test name
Test status
Simulation time 26927750589 ps
CPU time 75.12 seconds
Started Sep 18 06:40:02 AM UTC 24
Finished Sep 18 06:41:19 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966656742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1966656742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.4137612672
Short name T356
Test name
Test status
Simulation time 3726002623 ps
CPU time 4.64 seconds
Started Sep 18 06:39:56 AM UTC 24
Finished Sep 18 06:40:02 AM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137612672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4137612672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.2512761851
Short name T355
Test name
Test status
Simulation time 5764602984 ps
CPU time 4.44 seconds
Started Sep 18 06:39:13 AM UTC 24
Finished Sep 18 06:39:19 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512761851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2512761851
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3577427829
Short name T42
Test name
Test status
Simulation time 336200219580 ps
CPU time 899.8 seconds
Started Sep 18 06:40:39 AM UTC 24
Finished Sep 18 06:55:48 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577427829 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.3577427829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2604812670
Short name T53
Test name
Test status
Simulation time 16312720470 ps
CPU time 20.45 seconds
Started Sep 18 06:40:26 AM UTC 24
Finished Sep 18 06:40:47 AM UTC 24
Peak memory 221136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2604812670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.adc_ctrl_stress_all_with_rand_reset.2604812670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.703855148
Short name T364
Test name
Test status
Simulation time 389522724 ps
CPU time 2.08 seconds
Started Sep 18 06:41:40 AM UTC 24
Finished Sep 18 06:41:43 AM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703855148 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.703855148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.83528321
Short name T146
Test name
Test status
Simulation time 351665650822 ps
CPU time 250.03 seconds
Started Sep 18 06:41:11 AM UTC 24
Finished Sep 18 06:45:25 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83528321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.83528321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.1548823926
Short name T151
Test name
Test status
Simulation time 159183107095 ps
CPU time 81.65 seconds
Started Sep 18 06:40:55 AM UTC 24
Finished Sep 18 06:42:19 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548823926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1548823926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2638956071
Short name T185
Test name
Test status
Simulation time 333631232985 ps
CPU time 234.71 seconds
Started Sep 18 06:40:56 AM UTC 24
Finished Sep 18 06:44:54 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638956071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.2638956071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.4046190122
Short name T181
Test name
Test status
Simulation time 163666629340 ps
CPU time 204.97 seconds
Started Sep 18 06:40:47 AM UTC 24
Finished Sep 18 06:44:15 AM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046190122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4046190122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.3429069797
Short name T412
Test name
Test status
Simulation time 328068998166 ps
CPU time 857.93 seconds
Started Sep 18 06:40:48 AM UTC 24
Finished Sep 18 06:55:15 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429069797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.3429069797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.568340145
Short name T235
Test name
Test status
Simulation time 515727946704 ps
CPU time 737.73 seconds
Started Sep 18 06:41:06 AM UTC 24
Finished Sep 18 06:53:32 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568340145 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.568340145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2134928271
Short name T395
Test name
Test status
Simulation time 201600987284 ps
CPU time 614.25 seconds
Started Sep 18 06:41:06 AM UTC 24
Finished Sep 18 06:51:27 AM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134928271 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.2134928271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.141845327
Short name T343
Test name
Test status
Simulation time 93655995322 ps
CPU time 498.32 seconds
Started Sep 18 06:41:28 AM UTC 24
Finished Sep 18 06:49:52 AM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141845327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.141845327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.221456205
Short name T366
Test name
Test status
Simulation time 45011499212 ps
CPU time 79.04 seconds
Started Sep 18 06:41:20 AM UTC 24
Finished Sep 18 06:42:40 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221456205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.221456205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.1175341309
Short name T362
Test name
Test status
Simulation time 4400929428 ps
CPU time 7.89 seconds
Started Sep 18 06:41:17 AM UTC 24
Finished Sep 18 06:41:26 AM UTC 24
Peak memory 210548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175341309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1175341309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2760647251
Short name T360
Test name
Test status
Simulation time 5821571094 ps
CPU time 25.76 seconds
Started Sep 18 06:40:44 AM UTC 24
Finished Sep 18 06:41:11 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760647251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2760647251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.3749251656
Short name T347
Test name
Test status
Simulation time 409181762541 ps
CPU time 1591.28 seconds
Started Sep 18 06:41:34 AM UTC 24
Finished Sep 18 07:08:21 AM UTC 24
Peak memory 213724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749251656 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.3749251656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1891726329
Short name T54
Test name
Test status
Simulation time 167126740523 ps
CPU time 37.17 seconds
Started Sep 18 06:41:31 AM UTC 24
Finished Sep 18 06:42:09 AM UTC 24
Peak memory 221004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1891726329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.adc_ctrl_stress_all_with_rand_reset.1891726329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest
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