Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1169234	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1141538

1

T1

3

T2

46

T3

63

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2043060	1			T1	1		T2	81		T3	81
values[0x0]	133341	1			T1	8		T2	26		T3	32
values[0x1]	134371	1			T1	4		T2	37		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	935752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1375020

1

T1

3

T2

65

T3

74

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7308	1			T11	1		T13	1		T53	1
valid_sources[0x01]	15326	1			T10	4		T11	1		T39	1
valid_sources[0x02]	15135	1			T7	1		T12	5		T14	20
valid_sources[0x03]	6933	1			T8	4		T26	1		T13	1
valid_sources[0x04]	10443	1			T10	6		T14	17		T15	3
valid_sources[0x05]	7002	1			T9	1		T26	1		T13	5
valid_sources[0x06]	11439	1			T13	2		T53	1		T14	24
valid_sources[0x07]	8528	1			T5	5		T13	1		T14	16
valid_sources[0x08]	7039	1			T26	1		T13	4		T14	23
valid_sources[0x09]	9893	1			T13	4		T53	1		T14	20
valid_sources[0x0a]	6610	1			T12	4		T13	2		T14	24
valid_sources[0x0b]	20335	1			T2	2		T13	2		T14	11
valid_sources[0x0c]	6967	1			T9	16		T39	1		T14	15
valid_sources[0x0d]	14990	1			T12	3		T13	2		T39	1
valid_sources[0x0e]	8181	1			T7	6		T13	1		T14	13
valid_sources[0x0f]	6923	1			T14	13		T15	10		T16	3
valid_sources[0x10]	6629	1			T7	1		T26	1		T14	26
valid_sources[0x11]	9831	1			T3	27		T11	1		T13	1
valid_sources[0x12]	6769	1			T23	3		T13	2		T14	24
valid_sources[0x13]	6842	1			T13	7		T53	1		T14	20
valid_sources[0x14]	7679	1			T26	4		T54	1		T14	15
valid_sources[0x15]	20760	1			T10	6		T26	2		T13	4
valid_sources[0x16]	8882	1			T26	3		T13	6		T53	1
valid_sources[0x17]	8243	1			T2	1		T13	1		T14	14
valid_sources[0x18]	8139	1			T54	1		T14	19		T15	3
valid_sources[0x19]	6647	1			T11	2		T27	43		T13	3
valid_sources[0x1a]	8550	1			T4	2		T13	1		T14	10
valid_sources[0x1b]	10487	1			T9	2		T13	1		T14	14
valid_sources[0x1c]	7078	1			T2	6		T13	1		T14	15
valid_sources[0x1d]	10141	1			T26	1		T13	1		T39	1
valid_sources[0x1e]	7533	1			T2	3		T13	4		T14	17
valid_sources[0x1f]	6795	1			T10	2		T13	1		T14	11
valid_sources[0x20]	6974	1			T4	1		T5	3		T13	2
valid_sources[0x21]	6805	1			T54	2		T14	25		T15	4
valid_sources[0x22]	7345	1			T13	3		T14	19		T15	5
valid_sources[0x23]	15319	1			T2	7		T5	2		T7	1
valid_sources[0x24]	7047	1			T26	1		T14	15		T15	6
valid_sources[0x25]	11123	1			T10	8		T26	3		T13	1
valid_sources[0x26]	7130	1			T5	7		T26	1		T13	2
valid_sources[0x27]	9725	1			T13	1		T14	16		T15	3
valid_sources[0x28]	7135	1			T10	23		T13	1		T14	15
valid_sources[0x29]	7999	1			T13	3		T54	1		T14	20
valid_sources[0x2a]	6677	1			T7	1		T26	1		T13	2
valid_sources[0x2b]	6992	1			T26	1		T13	1		T14	15
valid_sources[0x2c]	7024	1			T8	15		T9	11		T11	2
valid_sources[0x2d]	6586	1			T13	1		T14	15		T15	2
valid_sources[0x2e]	7912	1			T5	6		T12	7		T26	1
valid_sources[0x2f]	11546	1			T13	2		T14	13		T15	6
valid_sources[0x30]	12294	1			T2	8		T11	1		T26	1
valid_sources[0x31]	12038	1			T4	2		T7	2		T13	1
valid_sources[0x32]	6800	1			T13	1		T14	24		T15	1
valid_sources[0x33]	6887	1			T53	1		T14	16		T15	3
valid_sources[0x34]	8625	1			T4	1		T13	1		T14	13
valid_sources[0x35]	7750	1			T26	3		T14	22		T15	2
valid_sources[0x36]	11339	1			T7	2		T13	2		T54	1
valid_sources[0x37]	6910	1			T13	1		T39	1		T14	11
valid_sources[0x38]	6744	1			T10	3		T13	1		T14	15
valid_sources[0x39]	7852	1			T8	15		T12	3		T26	2
valid_sources[0x3a]	7250	1			T26	3		T13	2		T14	16
valid_sources[0x3b]	7239	1			T13	4		T14	17		T15	3
valid_sources[0x3c]	7017	1			T54	1		T14	17		T15	2
valid_sources[0x3d]	6712	1			T4	1		T26	2		T14	18
valid_sources[0x3e]	8111	1			T13	1		T14	23		T15	3
valid_sources[0x3f]	11903	1			T13	2		T53	1		T14	18
valid_sources[0x40]	7122	1			T4	2		T26	2		T14	17
valid_sources[0x41]	6809	1			T10	2		T26	2		T14	17
valid_sources[0x42]	7177	1			T13	2		T14	19		T16	4
valid_sources[0x43]	10694	1			T10	10		T13	5		T14	19
valid_sources[0x44]	7396	1			T14	10		T15	6		T19	41
valid_sources[0x45]	8279	1			T4	3		T5	3		T26	1
valid_sources[0x46]	7027	1			T13	1		T14	17		T15	2
valid_sources[0x47]	7569	1			T11	2		T26	3		T14	14
valid_sources[0x48]	11701	1			T13	1		T41	144		T14	20
valid_sources[0x49]	6607	1			T2	6		T9	3		T13	1
valid_sources[0x4a]	8312	1			T26	4		T13	1		T14	24
valid_sources[0x4b]	6840	1			T7	3		T13	1		T14	19
valid_sources[0x4c]	6903	1			T8	4		T11	1		T26	2
valid_sources[0x4d]	22088	1			T4	1		T5	4		T14	11
valid_sources[0x4e]	18271	1			T11	2		T26	2		T13	2
valid_sources[0x4f]	6736	1			T26	1		T14	12		T15	9
valid_sources[0x50]	20048	1			T7	1		T13	2		T14	18
valid_sources[0x51]	7948	1			T13	2		T14	20		T15	1
valid_sources[0x52]	6794	1			T4	2		T9	19		T13	4
valid_sources[0x53]	11174	1			T11	1		T26	1		T13	1
valid_sources[0x54]	8020	1			T4	1		T13	1		T53	1
valid_sources[0x55]	9257	1			T13	5		T14	19		T15	3
valid_sources[0x56]	9940	1			T4	1		T13	2		T14	18
valid_sources[0x57]	7289	1			T11	1		T26	3		T13	2
valid_sources[0x58]	8488	1			T22	3		T26	1		T13	3
valid_sources[0x59]	7868	1			T2	2		T6	7		T26	1
valid_sources[0x5a]	20936	1			T10	2		T11	3		T12	1
valid_sources[0x5b]	11207	1			T10	3		T13	1		T53	1
valid_sources[0x5c]	7118	1			T14	24		T16	1		T19	18
valid_sources[0x5d]	7655	1			T13	2		T14	15		T15	2
valid_sources[0x5e]	11143	1			T14	18		T15	3		T17	1
valid_sources[0x5f]	6796	1			T13	1		T14	16		T15	1
valid_sources[0x60]	6366	1			T13	3		T14	22		T16	3
valid_sources[0x61]	6788	1			T10	3		T13	2		T54	3
valid_sources[0x62]	12159	1			T13	1		T53	2		T14	15
valid_sources[0x63]	6890	1			T13	1		T14	19		T15	8
valid_sources[0x64]	8549	1			T8	15		T13	1		T54	2
valid_sources[0x65]	7194	1			T13	2		T14	11		T15	5
valid_sources[0x66]	7150	1			T5	7		T26	1		T13	2
valid_sources[0x67]	6646	1			T13	4		T14	21		T15	1
valid_sources[0x68]	6756	1			T13	1		T53	1		T14	14
valid_sources[0x69]	6969	1			T2	4		T9	9		T13	3
valid_sources[0x6a]	7002	1			T2	3		T8	31		T13	1
valid_sources[0x6b]	11009	1			T6	1		T12	1		T26	1
valid_sources[0x6c]	7203	1			T11	1		T40	3		T14	21
valid_sources[0x6d]	7530	1			T10	1		T26	1		T14	20
valid_sources[0x6e]	12266	1			T14	7		T15	3		T19	7
valid_sources[0x6f]	6922	1			T12	1		T26	1		T14	14
valid_sources[0x70]	8863	1			T3	39		T14	20		T15	6
valid_sources[0x71]	7044	1			T10	7		T26	3		T13	4
valid_sources[0x72]	6994	1			T2	2		T13	1		T14	20
valid_sources[0x73]	6857	1			T2	9		T9	14		T13	2
valid_sources[0x74]	6818	1			T14	9		T15	12		T19	19
valid_sources[0x75]	10764	1			T7	1		T23	1		T26	1
valid_sources[0x76]	8338	1			T23	1		T11	2		T12	1
valid_sources[0x77]	6732	1			T7	4		T9	3		T13	3
valid_sources[0x78]	6979	1			T14	15		T15	9		T16	2
valid_sources[0x79]	12902	1			T26	4		T13	5		T14	21
valid_sources[0x7a]	6871	1			T10	12		T12	2		T14	10
valid_sources[0x7b]	7046	1			T11	1		T53	1		T14	19
valid_sources[0x7c]	6587	1			T14	9		T16	12		T19	11
valid_sources[0x7d]	6622	1			T4	3		T7	2		T10	3
valid_sources[0x7e]	7037	1			T5	3		T13	1		T14	19
valid_sources[0x7f]	6818	1			T26	1		T13	5		T53	1
valid_sources[0x80]	7610	1			T13	2		T14	13		T15	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018675

1

T2

31

T3

41

T6

5

values[0x0]

all_enables

biggest_size

71788

1

T1

3

T2

8

T3

14

values[0x1]

all_enables

biggest_size

51075

1

T2

7

T3

8

T4

9