Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	25414	1			T14	5		T15	5		T16	20
auto[PWRUP]	103	1			T16	1		T58	1		T56	1
auto[ONEST_0]	58	1			T58	1		T56	1		T57	2
auto[ONEST_021]	19	1			T209	1		T210	2		T211	1
auto[ONEST_1]	68	1			T59	1		T63	1		T209	2
auto[ONEST_DONE]	6	1			T36	1		T212	1		T213	1
auto[LP_0]	97	1			T58	1		T55	2		T56	2
auto[LP_021]	21	1			T56	1		T214	1		T91	1
auto[LP_1]	112	1			T16	1		T58	1		T55	1
auto[LP_EVAL]	50	1			T59	3		T63	1		T60	1
auto[LP_SLP]	392	1			T58	6		T55	4		T56	7
auto[LP_PWRUP]	20	1			T55	1		T59	1		T97	1
auto[NP_0]	150	1			T58	1		T55	3		T56	1
auto[NP_021]	26	1			T55	1		T56	1		T57	1
auto[NP_1]	142	1			T58	4		T55	1		T56	4
auto[NP_EVAL]	43	1			T55	2		T60	1		T209	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

3

1

T215

1

T216

1

T217

1

min

24908

1

T14

5

T15

5

T16

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24915	1			T14	5		T15	5		T16	19
pow[0x1]	3	1			T57	1		T218	1		T217	1
pow[0x2]	15	1			T56	1		T218	1		T209	1
pow[0x3]	32	1			T58	1		T56	1		T59	1
pow[0x4]	50	1			T55	2		T57	1		T59	1
pow[0x5]	109	1			T58	2		T55	2		T57	1
pow[0x6]	205	1			T58	3		T55	1		T56	2
pow[0x7]	465	1			T16	1		T58	3		T55	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

148

1

T16

1

T58

1

T56

6

min

24558

1

T14

5

T15

5

T16

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24558	1			T14	5		T15	5		T16	19
pow[0x1]	1	1			T219	1		-	-		-	-
pow[0x5]	3	1			T211	1		T220	1		T221	1
pow[0x8]	6	1			T218	1		T222	1		T212	1
pow[0x9]	8	1			T223	1		T224	1		T225	1
pow[0xa]	15	1			T63	2		T223	2		T226	1
pow[0xb]	22	1			T57	1		T209	1		T97	1
pow[0xc]	58	1			T58	2		T56	2		T57	1
pow[0xd]	125	1			T55	2		T56	3		T57	2
pow[0xe]	246	1			T16	1		T55	4		T57	4
pow[0xf]	499	1			T16	1		T58	7		T55	6