Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2061	1			T22	20		T6	2		T8	5
auto[PWRUP]	146	1			T9	1		T58	1		T55	1
auto[ONEST_0]	80	1			T9	1		T16	1		T28	1
auto[ONEST_021]	18	1			T59	1		T60	1		T62	1
auto[ONEST_1]	65	1			T55	1		T63	1		T209	1
auto[ONEST_DONE]	2	1			T370	1		T365	1		-	-
auto[LP_0]	132	1			T8	1		T13	1		T16	1
auto[LP_021]	31	1			T55	1		T57	1		T209	1
auto[LP_1]	120	1			T8	1		T58	1		T55	1
auto[LP_EVAL]	47	1			T55	1		T59	1		T63	1
auto[LP_SLP]	420	1			T8	1		T16	2		T58	3
auto[LP_PWRUP]	24	1			T57	1		T209	1		T91	1
auto[NP_0]	158	1			T13	3		T16	1		T17	1
auto[NP_021]	38	1			T17	1		T57	1		T209	1
auto[NP_1]	167	1			T8	1		T16	4		T17	1
auto[NP_EVAL]	20	1			T97	1		T31	1		T371	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T372

1

T224

1

T373

1

min

1712

1

T22

20

T6

2

T8

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1727	1			T22	20		T6	2		T8	8
pow[0x1]	8	1			T8	1		T16	1		T270	1
pow[0x2]	9	1			T373	1		T220	1		T315	1
pow[0x3]	22	1			T59	1		T60	1		T215	1
pow[0x4]	54	1			T56	1		T59	1		T63	1
pow[0x5]	110	1			T55	1		T56	1		T57	1
pow[0x6]	238	1			T13	1		T58	3		T55	3
pow[0x7]	490	1			T16	2		T58	4		T55	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

163

1

T55

1

T56

3

T63

3

min

1247

1

T22

20

T6

2

T8

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1256	1			T22	20		T6	2		T8	8
pow[0x1]	12	1			T13	1		T94	1		T374	1
pow[0x2]	18	1			T8	1		T13	1		T47	1
pow[0x3]	17	1			T16	4		T17	2		T28	3
pow[0x4]	15	1			T267	1		T264	1		T294	1
pow[0x5]	1	1			T375	1		-	-		-	-
pow[0x6]	1	1			T370	1		-	-		-	-
pow[0x7]	2	1			T376	1		T377	1		-	-
pow[0x8]	1	1			T378	1		-	-		-	-
pow[0x9]	3	1			T90	1		T220	1		T379	1
pow[0xa]	22	1			T63	1		T60	1		T218	1
pow[0xb]	33	1			T58	2		T57	1		T59	1
pow[0xc]	66	1			T58	1		T55	1		T59	1
pow[0xd]	123	1			T57	3		T59	1		T63	3
pow[0xe]	247	1			T58	2		T55	1		T56	2
pow[0xf]	525	1			T16	2		T58	4		T55	7