Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	31954888	31881362	0	0
FsmStateHwReset_A	1010	1010	0	0
FsmStateSwReset_A	31954888	6650	0	0
LpSampleCntHwReset_A	1010	1010	0	0
LpSampleCntSwReset_A	31954888	6650	0	0
NpSampleCntHwReset_A	1010	1010	0	0
NpSampleCntSwReset_A	31954888	6650	0	0
PwrupTimerCntHwReset_A	1010	1010	0	0
PwrupTimerCntSwReset_A	31954888	6650	0	0
WakeupTimerCntHwReset_A	1010	1010	0	0
WakeupTimerCntSwReset_A	31954888	6650	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31954888	31881362	0	0
T1	96	1	0	0
T2	1215	1117	0	0
T3	1120	1050	0	0
T4	724	643	0	0
T5	1119	1023	0	0
T6	820	560	0	0
T7	5658	5565	0	0
T8	74	1	0	0
T22	99	1	0	0
T23	88	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	3	3	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31954888	6650	0	0
T14	33653	5	0	0
T15	33618	5	0	0
T16	2130	0	0	0
T17	85	0	0	0
T18	34348	6	0	0
T19	32609	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T37	0	11	0	0
T38	0	8	0	0
T42	98	0	0	0
T43	5549	0	0	0
T44	63	0	0	0
T45	7317	0	0	0
T50	0	17	0	0
T81	0	9	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	3	3	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31954888	6650	0	0
T14	33653	5	0	0
T15	33618	5	0	0
T16	2130	0	0	0
T17	85	0	0	0
T18	34348	6	0	0
T19	32609	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T37	0	11	0	0
T38	0	8	0	0
T42	98	0	0	0
T43	5549	0	0	0
T44	63	0	0	0
T45	7317	0	0	0
T50	0	17	0	0
T81	0	9	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	3	3	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31954888	6650	0	0
T14	33653	5	0	0
T15	33618	5	0	0
T16	2130	0	0	0
T17	85	0	0	0
T18	34348	6	0	0
T19	32609	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T37	0	11	0	0
T38	0	8	0	0
T42	98	0	0	0
T43	5549	0	0	0
T44	63	0	0	0
T45	7317	0	0	0
T50	0	17	0	0
T81	0	9	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	3	3	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31954888	6650	0	0
T14	33653	5	0	0
T15	33618	5	0	0
T16	2130	0	0	0
T17	85	0	0	0
T18	34348	6	0	0
T19	32609	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T37	0	11	0	0
T38	0	8	0	0
T42	98	0	0	0
T43	5549	0	0	0
T44	63	0	0	0
T45	7317	0	0	0
T50	0	17	0	0
T81	0	9	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	3	3	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31954888	6650	0	0
T14	33653	5	0	0
T15	33618	5	0	0
T16	2130	0	0	0
T17	85	0	0	0
T18	34348	6	0	0
T19	32609	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T37	0	11	0	0
T38	0	8	0	0
T42	98	0	0	0
T43	5549	0	0	0
T44	63	0	0	0
T45	7317	0	0	0
T50	0	17	0	0
T81	0	9	0	0