Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1600	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1711	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1565	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1618	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1413	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1599	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1526	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1693	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1482	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1694	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1696	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1654	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1551	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1660	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1532	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1561	0	0
adc_en_ctl_rd_A	2147483647	1022	0	0
adc_fsm_rst_rd_A	2147483647	1092	0	0
adc_intr_ctl_rd_A	2147483647	1404	0	0
adc_lp_sample_ctl_rd_A	2147483647	998	0	0
adc_pd_ctl_rd_A	2147483647	1449	0	0
adc_sample_ctl_rd_A	2147483647	1032	0	0
adc_wakeup_ctl_rd_A	2147483647	1268	0	0
intr_enable_rd_A	2147483647	1474	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1600	0	0
T8	261486	26	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	16	0	0
T16	0	45	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	4	0	0
T29	0	20	0	0
T30	0	50	0	0
T31	0	65	0	0
T32	0	19	0	0
T33	0	4	0	0
T34	0	45	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1711	0	0
T8	261486	24	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	11	0	0
T16	0	42	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	5	0	0
T29	0	12	0	0
T30	0	36	0	0
T31	0	26	0	0
T32	0	20	0	0
T33	0	10	0	0
T34	0	41	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T8	261486	24	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	20	0	0
T16	0	43	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	6	0	0
T29	0	17	0	0
T30	0	51	0	0
T31	0	19	0	0
T32	0	14	0	0
T33	0	15	0	0
T34	0	26	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1618	0	0
T8	261486	16	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	7	0	0
T16	0	31	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	11	0	0
T29	0	7	0	0
T30	0	47	0	0
T31	0	41	0	0
T32	0	28	0	0
T33	0	11	0	0
T34	0	41	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1413	0	0
T8	261486	17	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	9	0	0
T16	0	32	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	9	0	0
T29	0	6	0	0
T30	0	30	0	0
T31	0	24	0	0
T32	0	24	0	0
T33	0	12	0	0
T34	0	49	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1599	0	0
T8	261486	25	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	25	0	0
T16	0	31	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	11	0	0
T29	0	13	0	0
T30	0	49	0	0
T31	0	45	0	0
T32	0	13	0	0
T33	0	10	0	0
T34	0	43	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1526	0	0
T8	261486	18	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	21	0	0
T16	0	49	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	5	0	0
T29	0	9	0	0
T30	0	44	0	0
T31	0	26	0	0
T32	0	23	0	0
T33	0	9	0	0
T34	0	38	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1693	0	0
T8	261486	15	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	13	0	0
T16	0	35	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	9	0	0
T29	0	16	0	0
T30	0	50	0	0
T31	0	40	0	0
T32	0	18	0	0
T33	0	2	0	0
T34	0	34	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1482	0	0
T8	261486	13	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	24	0	0
T16	0	26	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	5	0	0
T29	0	17	0	0
T30	0	35	0	0
T31	0	38	0	0
T32	0	17	0	0
T33	0	13	0	0
T34	0	37	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1694	0	0
T8	261486	15	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	14	0	0
T16	0	38	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	8	0	0
T29	0	14	0	0
T30	0	44	0	0
T31	0	38	0	0
T32	0	10	0	0
T33	0	21	0	0
T34	0	30	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1696	0	0
T8	261486	27	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	10	0	0
T16	0	39	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	12	0	0
T29	0	25	0	0
T30	0	37	0	0
T31	0	48	0	0
T32	0	21	0	0
T33	0	6	0	0
T34	0	39	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1654	0	0
T8	261486	27	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	16	0	0
T16	0	46	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	9	0	0
T29	0	14	0	0
T30	0	47	0	0
T31	0	50	0	0
T32	0	9	0	0
T33	0	9	0	0
T34	0	29	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1551	0	0
T8	261486	23	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	22	0	0
T16	0	34	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	15	0	0
T29	0	4	0	0
T30	0	43	0	0
T31	0	43	0	0
T32	0	9	0	0
T33	0	14	0	0
T34	0	45	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1660	0	0
T8	261486	12	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	11	0	0
T16	0	35	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	6	0	0
T29	0	17	0	0
T30	0	35	0	0
T31	0	23	0	0
T32	0	15	0	0
T33	0	11	0	0
T34	0	39	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1532	0	0
T8	261486	23	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	23	0	0
T16	0	39	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	8	0	0
T29	0	17	0	0
T30	0	38	0	0
T31	0	45	0	0
T32	0	6	0	0
T33	0	9	0	0
T34	0	26	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1561	0	0
T8	261486	13	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	26	0	0
T16	0	32	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	12	0	0
T29	0	20	0	0
T30	0	44	0	0
T31	0	46	0	0
T32	0	16	0	0
T33	0	3	0	0
T34	0	36	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1022	0	0
T8	261486	10	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	24	0	0
T16	0	24	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	14	0	0
T29	0	7	0	0
T30	0	22	0	0
T31	0	34	0	0
T32	0	30	0	0
T33	0	2	0	0
T34	0	40	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1092	0	0
T8	261486	23	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	16	0	0
T16	0	30	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	8	0	0
T29	0	16	0	0
T30	0	42	0	0
T31	0	34	0	0
T32	0	18	0	0
T33	0	10	0	0
T34	0	44	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1404	0	0
T8	261486	19	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	31	0	0
T16	0	45	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	4	0	0
T29	0	15	0	0
T30	0	49	0	0
T31	0	42	0	0
T32	0	26	0	0
T33	0	16	0	0
T34	0	38	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	998	0	0
T8	261486	18	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	19	0	0
T16	0	40	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	2	0	0
T29	0	14	0	0
T30	0	51	0	0
T31	0	38	0	0
T32	0	12	0	0
T33	0	29	0	0
T34	0	32	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1449	0	0
T8	261486	14	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	44	0	0
T16	0	44	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	12	0	0
T29	0	20	0	0
T30	0	44	0	0
T31	0	43	0	0
T32	0	16	0	0
T33	0	14	0	0
T34	0	44	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1032	0	0
T8	261486	25	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	16	0	0
T16	0	47	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	3	0	0
T29	0	14	0	0
T30	0	60	0	0
T31	0	51	0	0
T32	0	27	0	0
T33	0	12	0	0
T34	0	55	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1268	0	0
T8	261486	22	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	356762	14	0	0
T16	0	40	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T26	283326	0	0	0
T27	92361	0	0	0
T28	0	4	0	0
T29	0	13	0	0
T30	0	49	0	0
T31	0	30	0	0
T32	0	15	0	0
T33	0	7	0	0
T34	0	43	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1474	0	0
T6	103946	13	0	0
T7	452717	0	0	0
T8	261486	25	0	0
T9	135826	0	0	0
T10	577495	0	0	0
T11	819152	0	0	0
T12	395312	0	0	0
T13	0	16	0	0
T16	0	36	0	0
T23	44608	0	0	0
T24	360122	0	0	0
T25	9670	0	0	0
T28	0	17	0	0
T29	0	13	0	0
T30	0	42	0	0
T31	0	24	0	0
T35	0	15	0	0
T36	0	14	0	0