Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1172131	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1148963

1

T1

62

T2

178

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2043932	1			T1	81		T2	307		T3	1
values[0x0]	138329	1			T1	31		T2	18		T3	7
values[0x1]	138833	1			T1	32		T2	11		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	939069	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1382025

1

T1

79

T2

203

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6951	1			T1	2		T13	23		T14	1
valid_sources[0x01]	7585	1			T13	5		T23	2		T15	2
valid_sources[0x02]	9669	1			T1	5		T11	3		T13	31
valid_sources[0x03]	6940	1			T4	1		T22	1		T10	4
valid_sources[0x04]	10922	1			T1	2		T8	5		T11	3
valid_sources[0x05]	7884	1			T2	4		T4	1		T11	2
valid_sources[0x06]	6806	1			T1	1		T11	1		T13	22
valid_sources[0x07]	6632	1			T4	2		T11	1		T13	12
valid_sources[0x08]	7734	1			T1	2		T8	2		T11	1
valid_sources[0x09]	7691	1			T1	1		T8	1		T11	1
valid_sources[0x0a]	7256	1			T8	1		T11	4		T13	8
valid_sources[0x0b]	6869	1			T50	1		T11	1		T13	13
valid_sources[0x0c]	8596	1			T8	3		T13	12		T14	2
valid_sources[0x0d]	6975	1			T1	2		T2	15		T8	1
valid_sources[0x0e]	6757	1			T4	1		T8	4		T11	4
valid_sources[0x0f]	7742	1			T2	6		T11	1		T13	51
valid_sources[0x10]	11615	1			T1	1		T8	1		T11	2
valid_sources[0x11]	6998	1			T7	1		T12	36		T13	10
valid_sources[0x12]	6493	1			T9	1		T11	2		T13	24
valid_sources[0x13]	6920	1			T1	1		T2	3		T7	2
valid_sources[0x14]	11301	1			T1	2		T7	2		T11	1
valid_sources[0x15]	7246	1			T1	2		T8	3		T13	6
valid_sources[0x16]	7148	1			T1	1		T8	3		T11	4
valid_sources[0x17]	7786	1			T13	16		T14	2		T15	1
valid_sources[0x18]	7829	1			T9	2		T11	1		T13	12
valid_sources[0x19]	13590	1			T1	1		T7	1		T11	4
valid_sources[0x1a]	11930	1			T13	15		T14	7		T16	6
valid_sources[0x1b]	6727	1			T1	5		T10	2		T11	1
valid_sources[0x1c]	6694	1			T4	1		T11	2		T13	24
valid_sources[0x1d]	9315	1			T2	1		T13	15		T14	3
valid_sources[0x1e]	6693	1			T1	2		T3	1		T11	2
valid_sources[0x1f]	6680	1			T22	1		T11	3		T13	11
valid_sources[0x20]	7006	1			T1	1		T11	7		T13	13
valid_sources[0x21]	12432	1			T1	1		T4	1		T7	1
valid_sources[0x22]	6506	1			T4	1		T13	24		T23	1
valid_sources[0x23]	6722	1			T13	14		T23	1		T14	5
valid_sources[0x24]	6851	1			T47	1		T11	4		T13	9
valid_sources[0x25]	11214	1			T1	1		T3	1		T7	1
valid_sources[0x26]	12218	1			T4	1		T11	1		T13	25
valid_sources[0x27]	6689	1			T1	2		T11	2		T13	18
valid_sources[0x28]	11300	1			T8	2		T11	3		T13	30
valid_sources[0x29]	7080	1			T1	1		T2	21		T11	7
valid_sources[0x2a]	8934	1			T8	3		T10	4		T13	20
valid_sources[0x2b]	7879	1			T1	2		T8	4		T11	1
valid_sources[0x2c]	6720	1			T11	2		T13	20		T14	4
valid_sources[0x2d]	13880	1			T4	1		T11	2		T13	20
valid_sources[0x2e]	7596	1			T4	2		T7	1		T11	2
valid_sources[0x2f]	9926	1			T13	16		T23	1		T14	4
valid_sources[0x30]	7101	1			T2	15		T8	1		T11	2
valid_sources[0x31]	7337	1			T7	1		T11	1		T13	20
valid_sources[0x32]	6935	1			T22	1		T8	4		T11	1
valid_sources[0x33]	7129	1			T9	1		T11	2		T13	14
valid_sources[0x34]	19797	1			T10	3		T11	1		T13	18
valid_sources[0x35]	7366	1			T11	1		T13	15		T23	1
valid_sources[0x36]	16179	1			T1	1		T4	1		T13	13
valid_sources[0x37]	6708	1			T7	1		T11	3		T13	7
valid_sources[0x38]	15408	1			T1	1		T3	2		T7	1
valid_sources[0x39]	7399	1			T3	1		T8	1		T11	1
valid_sources[0x3a]	15424	1			T6	144		T7	1		T11	3
valid_sources[0x3b]	7181	1			T9	1		T11	3		T13	16
valid_sources[0x3c]	6861	1			T1	1		T11	2		T13	15
valid_sources[0x3d]	9607	1			T1	3		T2	15		T4	1
valid_sources[0x3e]	11514	1			T1	1		T8	2		T11	3
valid_sources[0x3f]	9397	1			T4	1		T8	2		T11	2
valid_sources[0x40]	6454	1			T22	1		T10	6		T11	4
valid_sources[0x41]	7859	1			T5	4		T11	3		T13	19
valid_sources[0x42]	10991	1			T2	8		T3	1		T13	16
valid_sources[0x43]	7606	1			T22	1		T7	1		T10	1
valid_sources[0x44]	6574	1			T1	4		T3	1		T4	1
valid_sources[0x45]	11245	1			T9	1		T13	10		T14	6
valid_sources[0x46]	7048	1			T11	3		T13	10		T14	3
valid_sources[0x47]	6763	1			T1	1		T13	10		T23	1
valid_sources[0x48]	6800	1			T2	2		T8	3		T11	4
valid_sources[0x49]	7935	1			T2	17		T7	1		T8	1
valid_sources[0x4a]	6695	1			T1	4		T8	1		T11	1
valid_sources[0x4b]	7472	1			T1	1		T22	1		T11	2
valid_sources[0x4c]	7013	1			T4	2		T11	3		T13	17
valid_sources[0x4d]	11514	1			T8	2		T9	1		T11	2
valid_sources[0x4e]	10226	1			T8	2		T10	1		T11	1
valid_sources[0x4f]	11165	1			T8	1		T9	1		T11	1
valid_sources[0x50]	9590	1			T1	2		T4	1		T10	2
valid_sources[0x51]	6666	1			T1	1		T4	1		T7	1
valid_sources[0x52]	8352	1			T11	4		T13	11		T23	2
valid_sources[0x53]	6747	1			T1	1		T11	1		T13	13
valid_sources[0x54]	11131	1			T5	3		T9	1		T11	1
valid_sources[0x55]	10953	1			T7	2		T8	3		T11	1
valid_sources[0x56]	11049	1			T7	1		T8	1		T13	20
valid_sources[0x57]	6930	1			T9	1		T50	2		T13	17
valid_sources[0x58]	7344	1			T5	7		T11	2		T13	9
valid_sources[0x59]	15661	1			T3	2		T11	1		T13	16
valid_sources[0x5a]	7670	1			T1	1		T2	8		T9	2
valid_sources[0x5b]	11096	1			T8	1		T11	4		T13	18
valid_sources[0x5c]	7678	1			T3	1		T8	5		T11	1
valid_sources[0x5d]	6941	1			T11	1		T13	21		T23	1
valid_sources[0x5e]	19887	1			T11	2		T12	20		T13	20
valid_sources[0x5f]	11394	1			T8	3		T11	1		T13	26
valid_sources[0x60]	6587	1			T1	2		T8	1		T13	11
valid_sources[0x61]	12787	1			T1	1		T2	15		T13	24
valid_sources[0x62]	6699	1			T11	3		T13	15		T23	2
valid_sources[0x63]	11514	1			T5	2		T11	2		T13	14
valid_sources[0x64]	9366	1			T2	17		T8	1		T10	3
valid_sources[0x65]	8640	1			T1	2		T13	18		T14	5
valid_sources[0x66]	6335	1			T11	6		T13	13		T14	1
valid_sources[0x67]	6654	1			T1	1		T8	1		T11	8
valid_sources[0x68]	6484	1			T11	2		T13	21		T23	3
valid_sources[0x69]	6899	1			T8	1		T11	4		T13	35
valid_sources[0x6a]	6782	1			T1	2		T22	1		T8	4
valid_sources[0x6b]	7968	1			T8	2		T11	3		T13	18
valid_sources[0x6c]	14135	1			T1	1		T8	5		T13	22
valid_sources[0x6d]	15361	1			T13	22		T14	7		T16	1
valid_sources[0x6e]	8023	1			T7	1		T8	1		T11	3
valid_sources[0x6f]	7709	1			T2	6		T8	3		T11	3
valid_sources[0x70]	13001	1			T11	4		T13	17		T23	3
valid_sources[0x71]	7018	1			T1	1		T47	1		T11	2
valid_sources[0x72]	7755	1			T1	1		T11	3		T12	51
valid_sources[0x73]	6567	1			T1	3		T7	1		T13	11
valid_sources[0x74]	6773	1			T11	3		T13	12		T23	1
valid_sources[0x75]	10824	1			T8	2		T11	5		T13	21
valid_sources[0x76]	6624	1			T7	2		T8	1		T10	3
valid_sources[0x77]	7634	1			T1	1		T9	1		T11	5
valid_sources[0x78]	7202	1			T1	1		T11	2		T13	24
valid_sources[0x79]	7041	1			T2	2		T3	1		T9	2
valid_sources[0x7a]	20837	1			T8	2		T50	1		T11	4
valid_sources[0x7b]	8389	1			T1	1		T2	6		T8	1
valid_sources[0x7c]	7353	1			T1	1		T13	16		T23	2
valid_sources[0x7d]	6823	1			T4	1		T9	1		T13	14
valid_sources[0x7e]	11340	1			T9	2		T11	1		T13	24
valid_sources[0x7f]	7412	1			T11	3		T13	32		T15	2
valid_sources[0x80]	11666	1			T8	1		T11	1		T13	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018948

1

T1

46

T2

158

T6

38

values[0x0]

all_enables

biggest_size

75558

1

T1

8

T2

10

T3

1

values[0x1]

all_enables

biggest_size

54457

1

T1

8

T2

10

T3

1